Abstract: A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment between the photodiode implant and the gate. In one embodiment a drain side implant is formed concurrently with the deep n-type implant of the photodiode. After the deep implant, the mask is removed and a shallow p+ implant is formed to complete the photodiode. In another embodiment, the polysilicon is etched to define only a drain side edge, a shallow drain side implant is performed, and then a thick mask is provided and used to complete the gate structure, and is retained during the subsequent high energy implant. Alternatively, the high energy implant is performed prior to the shallow drain side implant.

Abstract: A method of manufacturing a semiconductor element. A dislocation region is formed between a first layer and a second layer, the dislocation region including a plurality of dislocations. First interstitials in the first layer are at least partially eliminated using the dislocations in the dislocation region. Vacancies are formed in the second layer. Second interstitials in the second layer are at least partially eliminated using the vacancies in the second layer.

Abstract: According to one embodiment, a method for the production of a stop zone in a doped zone of a semiconductor body comprises irradiating the semiconductor body with particle radiation in order to produce defects in a crystal lattice of the semiconductor body. The semiconductor body is exposed to an environment containing dopant atoms, during which dopant atoms are indiffused into the semiconductor body at an elevated temperature.

Abstract: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and an ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form and SiO2 passivation layer to improve the self aligned process.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device that may be capable of obtaining a stable device characteristic by securing an optimal CD of a gate. In embodiments, a method may include forming a gate oxide layer on a semiconductor substrate, forming a photoresist pattern at a first region of an upper portion of the gate oxide layer, forming an insulating layer on the substrate of a second region except for the photoresist pattern, removing the photoresist pattern after a formation of the insulating layer, forming a polysilicon on the substrate from which the photoresist pattern is removed, planarizing the polysilicon to expose the insulating layer in order to form a gate, forming sidewalls at both sides of the gate: and implanting ions in a resulting object using the sidewalls as a mask to form source/drain.

Abstract: The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An embodiment includes a tantalum nitride gate electrode on a hafnium dioxide gate dielectric on the silicon film (TaN/HfO2/Si/Ge), which produces a reliable high dielectric constant (high k) electronic structure having higher charge carrier mobility as compared to silicon substrates. This structure may be useful in high performance electronic devices. The structure is formed by ALD deposition of a thin silicon layer on a germanium substrate surface, and then ALD forming a hafnium oxide gate dielectric layer, and a tantalum nitride gate electrode. Such a structure may be used as the gate of a MOSFET, or as a capacitor. The properties of the dielectric may be varied by replacing the hafnium oxide with another gate dielectric such as zirconium oxide (ZrO2), or titanium oxide (TiO2).

Abstract: In a method of manufacturing a semiconductor integrated circuit device, a gate electrode is formed over a semiconductor substrate. An insulating film is then formed on the gate electrode and on regions corresponding to a source and a drain of the semiconductor integrated circuit device. The source and the drain are then formed. A nitride film is then selectively formed over the source and the gate electrode via the insulating film so that the nitride film extends over the gate electrode to a position short of a center of the gate electrode in a length direction thereof and so that a width of the nitride film is shorter than a channel width of the semiconductor integrated circuit device.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g.

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract: A method for providing metallization upon a semiconductor substrate utilizing a stencil having at least one aperture extending from the contact side to the fill side, the contact side of the stencil being substantially flat and forming a sharp edge with a wall of the at least one aperture, the at least one aperture being tapered such that an area of a cross-section of the at least one aperture at the fill side is larger than an area of the cross-section of the at least one aperture at the contact side. A method of forming a stencil for depositing metallization lines on a semiconductor substrate is also disclosed.

Abstract: A method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material. The method can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating a semiconductor layer and the metallic layer from the substrate, wherein the semiconductor layer is a portion of the substrate. In a particular embodiment, the separation-enhancing species can be incorporated into a metallic layer and moved into the substrate, and in particular embodiment, the separation-enhancing species can be implanted into the substrate. In still another embodiment, both the techniques can be used. In a further embodiment, a dual-sided process can be performed.

Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.

Abstract: A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.

Abstract: A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the masking layer, performing an isotropic etching process on the layer of conductive material to thereby define a plurality of piercing bond structures positioned on the substrate.

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Abstract: The present invention relates to a manufacturing method of a semiconductor device having a size approximately same as the size of a semiconductor chip when viewed in a plan view, in which the semiconductor chip is flip-chip bonded to a wiring pattern, and an object of the invention is to provide the manufacturing method of a semiconductor device which allows reduction in the number of process steps to realize the minimization of manufacturing cost. An insulating resin 13 is formed so as to cover a plurality of internal connection terminals 12 and a surface of a plurality of semiconductor chips 11 on which the plurality of internal connection terminals are provided, then a metal layer 33 for forming a wiring pattern is formed over the insulating resin 13, and by pressing the metal layer 33, the metal layer 33 and the plurality of internal connection terminals 12 are pressure-bonded.

Abstract: A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.

Abstract: An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

Abstract: The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition.

Abstract: An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K dielectric layer and the low-K dielectric layer to the interconnect layer, depositing an interconnect metal in the opening, and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Abstract: A method for fabricating a semiconductor device includes forming an interlayer insulating film over a semiconductor substrate. The interlayer insulating film is selectively etched to form a hole defining a storage node region. A lower electrode is formed in the hole. A support layer is formed over the lower electrode. The support layer fills an upper part of the hole and exposes the interlayer insulating film. A dip-out process is performed to remove the interlayer insulating film. The supporting layer is removed to expose the lower electrode. A dielectric film is formed over the semiconductor substrate including the lower electrode. A plate electrode is formed over the semiconductor substrate to fill the dielectric film and the lower electrode.

Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.

Abstract: A method for forming an interconnect structure includes forming a dielectric layer above a first layer having a conductive region defined therein. An opening is defined in the dielectric layer to expose at least a portion of the conductive region. A metal silicide is formed in the opening to define the interconnect structure. A semiconductor device includes a first layer having a conductive region defined therein, a dielectric layer formed above the first layer, and a metal silicide interconnect structure extending through the dielectric layer to communicate with the conductive region.

Abstract: Methods and systems for forming electrical interconnects through microelectronic workpieces are disclosed herein. One aspect of the invention is directed to a method of manufacturing an electrical interconnect in a microelectronic workpiece having a plurality of dies. Each die can include at least one terminal electrically coupled to an integrated circuit. The method can include forming a blind hole in a first side of the workpiece, and forming a vent in a second side of the workpiece in fluid communication with the blind hole. The method can further include moving, e.g., by sucking and/or wetting, electrically conductive material into at least a portion of the blind hole by drawing at least a partial vacuum in the vent. In one embodiment, the blind hole can extend through one of the terminals on the workpiece. In this embodiment, the electrically conductive material forms an interconnect that extends through the workpiece and is electrically coupled to the terminal.

Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.

Abstract: A semiconductor device having a VIA hole without disconnection caused by step is achieved. A semiconductor device and its manufacturing method, the semiconductor device comprising: a semi-insulating substrate 11 in which an electrode (12) is formed on a surface (11a) of one side and in which an aperture (11c) passed through from the surface 11a of one side to a surface (11b) of another side is formed; and a conductive layer (17) formed in an inner surface of the aperture (11c), and electrically connected with the electrode (12); wherein the aperture (11c) has a tapered region (11d) where an inside diameter of a part located in the surface (11b) of another side is larger than an inside diameter of a part located in the surface (11a) of one side.

Abstract: Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material layer pattern; selectively etching the second material layer pattern and the first material layer pattern in a direction perpendicular to the first direction to form an etching mask; and etching the object layer to form minute patterns.

Abstract: A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

Abstract: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Abstract: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.

Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.

Abstract: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property. When the light absorbing layer absorbs energy of the laser beam, due to emission of gas that is within the light absorbing layer, or sublimation, evaporation, or the like of the light absorbing layer, a part of the light absorbing layer and a part of the layer having a light-transmitting property in contact with the light absorbing layer are removed. By using the remaining part of the layer having a light-transmitting property or the remaining part of the light absorbing layer as a mask and etching the first layer, the first layer can be processed into a desired shape.

Abstract: A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface of the wafer is exposed to an etchant to preferentially etch away the circumferential lip, while the circular recess is masked by the spin-on-glass. The spin-on glass is removed, and the front surface of the transfer wafer is polished. Other methods of removing the circumferential lip include applying a higher pressure to the circumferential lip in a polishing process, and directing a pressurized fluid jet at the base of the circumferential lip.

Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.

Abstract: The invention provides a method for reducing the roughness of a free surface of a semiconductor wafer that includes removing material from the free surface of the wafer to provide a treated wafer, and performing a first rapid thermal annealing on the treated wafer in a pure argon atmosphere to substantially reduce the roughness of the free surface of the treated wafer. The material removal is selected and conducted to improve the effectiveness of the subsequent rapid thermal annealing in reducing the roughness of the free surface of the treated wafer.

Abstract: A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.

Abstract: A method for fabricating a bulb-shaped recess pattern includes: forming an etch barrier layer over a substrate; forming a hard mask pattern in which a first polymer is attached to sidewalls of the hard mask pattern over the etch barrier layer; sequentially etching the etch barrier layer and the substrate to form a recess pattern in which a second polymer is attached to sidewalls of the recess pattern; removing the first and second polymers and the hard mask pattern; forming a plurality of spacers exposing a bottom portion of the recess pattern; and etching the exposed bottom portion of the recess pattern to form a ball pattern.

Abstract: A first silicon containing film, an organic material film, a second silicon containing film are formed. The second silicon containing film is patterned to have a narrow width pattern and a wide width pattern. The organic material film is patterned to have a narrow width pattern and a wide width pattern. A side wall is formed on a side surface of the second silicon containing film and the organic material film by coating with a third silicon containing film. The narrow width pattern of the second silicon containing film is removed by using a mask that covers the second silicon containing film patterned to have a wide width pattern and the side wall. Finally, the organic material film is removed.

Abstract: The present invention is a plasma etching method including: an arranging step of arranging a pair of electrodes oppositely in a chamber and making one of the electrodes support a substrate to be processed in such a manner that the substrate is arranged between the electrodes, the substrate having an organic-material film; and an etching step of applying a high-frequency electric power to at least one of the electrodes to form a high-frequency electric field between the pair of the electrodes, supplying a process gas into the chamber to form a plasma of the process gas by means of the electric field, and plasma-etching the organic-material film of the substrate by means of the plasma partway in order to form a groove having a flat bottom. A frequency of the high-frequency electric power applied to the at least one of the electrodes is 50 to 150 MHz in the etching step.

Abstract: A method of protecting a polymeric layer from contamination by a photoresist layer. The method includes: (a) forming a polymeric layer over a substrate; (b) forming a non-photoactive protection layer over the polymeric layer; (c) forming a photoresist layer over the protection layer; (d) exposing the photoresist layer to actinic radiation and developing the photoresist layer to form a patterned photoresist layer, thereby exposing regions of the protection layer; (e) etching through the protection layer and the polymeric layer where the protection layer is not protected by the patterned photoresist layer; (f) removing the patterned photoresist layer in a first removal process; and (g) removing the protection layer in a second removal process different from the first removal process.

Abstract: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.

Abstract: A method and apparatus for cleaning layers of solar cell substrates is disclosed. The substrate is exposed to a reactive gas that may comprise neutral radicals comprising nitrogen and fluorine, or that may comprise anhydrous HF and water, alcohol, or a mixture of water and alcohol. The reactive gas may further comprise a carrier gas. The reactive gas etches the solar cell substrate surface, removing oxygen and other impurities. When exposed to the neutral radicals, the substrate grows a thin film containing ammonium hexafluorosilicate, which is subsequently removed by heat treatment.

Abstract: Substrates in a reaction chamber are sequentially exposed to at least three gas atmospheres: a first atmosphere of a first purge gas, a second atmosphere of a process gas and a third atmosphere of a second purge gas. The gases are introduced into the reaction chamber from one end of the chamber and exit from the opposite end. Successive gases entering the chamber are selected so that a stable interface with the immediately preceding gas can be maintained. For example, when the gases are fed into the chamber at the chamber's top end and are exhausted at the bottom end, the gases are chosen with successively lower molecular weights. In effect, each gas atmosphere stays on top of and pushes the previous gas atmosphere out of the chamber from the top down. Advantageously, the gases can be more effectively and completely removed from the chamber.

Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.

Abstract: While a fine porous diamond particle film has been known as a high heat resistant and low dielectric constant film and also has high mechanical strength and heat conductivity, and is expected as an insulating film for multi-layered wirings in semiconductor integrated circuit devices, it is insufficient in current-voltage characteristic and has not yet been put into practical use. According to the invention, by treating the fine porous diamond particle film with an aqueous solution of a salt of a metal such as barium and calcium, the carbonate or sulfate of which is insoluble or less soluble, and a hydrophobic agent such as hexamethyl disilazane or triethyl monochloro silane, as well as a reinforcing agent containing one of dichlorotetramethyl disiloxane or dimethoxytetramethyl disiloxane, thereby capable of putting the dielectric breakdown voltage and the leak current within a specified range of a practical standard.

Abstract: A manufacturing method of a semiconductor element provided with a semiconductor layer containing a crystal of an organic semiconductor material of the invention includes the steps of (i) forming a frame (12) on a substrate (base) (11), and (ii) forming the semiconductor layer (crystal (13)) inside the frame (12). The step (ii) includes a crystal forming step in which a solution (21) containing the organic semiconductor material and a liquid medium is placed inside the frame (12) and then the crystal (13) is formed from the solution (21).

Abstract: The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions, morphologies and physical dimensions, including selected cross sectional dimensions, shapes and lengths along the length of a nanowire. Further, the present invention provides methods of processing nanowires capable of patterning a nanowire to form a plurality of conductance constricting segments having selected positions along the length of a nanowire, including conductance constricting segments having reduced cross sectional dimensions and conductance constricting segments comprising one or more insulating materials such as metal oxides.

Abstract: A facing laminate for insulation products includes: a foil or metallized polymeric film sheet layer forming an inner layer of the laminate that is adapted be bonded directly to a surface of an insulation product; a paper composite sheet layer, which may include synthetic and/or inorganic fibers, forming an outer exposed layer of the laminate; and a scrim intermediate and bonded to the foil or metallized polymeric film sheet and paper composite sheet layers. The facing laminate may include a humectant and/or a water, oil, and/or grease repellant component. The paper composite sheet layer of the laminate exhibits greater dimensional stability and reduced wrinkling when the laminate is exposed to conditions of high humidity. Insulation products to be faced with this facing laminate include pipe insulation, duct board, duct wrap insulation, metal building insulation, and other building insulation products.