Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.

Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: A time multiplex logic device is disclosed. The device comprises a single wire segment to couple a plurality of logic outputs to a plurality of logic inputs using a non-overlapping time multiplex sequence of global controls signals. The disclosure includes programmable logic blocks and wire structures that allow wire sharing. Time shared wires offer significant reduction in total wires needed for routing in programmable logic, which accounts for the single largest overhead and cost associated with programmable logic.

Abstract: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node.

Abstract: An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: An input voltage detecting circuit includes an input circuit, a signal processing circuit and an output circuit. The input circuit is used for processing the intensity and the waveform of an input voltage, thereby generating a first signal, wherein the first signal and the input voltage have similar time sequences. The signal processing circuit is connected to the input circuit for reducing a first delaying time of the first signal, thereby generating a second signal having a second delaying time shorter than the first delaying time. The output circuit is connected to the signal processing circuit for processing the intensity and the waveform of the second signal, thereby generating the power status signal. If the input voltage is uninterrupted, the power status signal is in an uninterrupted status. If the input voltage is interrupted, the power status signal is in an interrupted status.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals connected to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected in series with the first transistor, a fourth transistor of the second conductivity type connected in series with the second transistor, a fifth transistor of the second conductivity type through which a mirror current depending on a current flowing through the third transistor, a sixth transistor of the second conductivity type flowing a mirror current depending on a current flowing through th

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected between the first transistor and the fourth terminal, and a fourth transistor of the second conductivity type connected between the second transistor and the third terminal, the fourth transistor flowing a mirror current depending on a current passing through the third transistor.

Abstract: A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

Abstract: A circuit device has a first output buffer including a first adjustment circuit for adjusting a level of the first output signal, a first input buffer connected to the first output buffer, an adjustment controller for outputting a test signal to the first output buffer, outputting a control signal to the first adjustment circuit so that the level of the first output signal is adjusted on the basis of the control signal, monitoring an output of the first input buffer, and adjusting the control signal on the basis of the monitoring the output of the first input buffer, a second output buffer connected to the adjustment controller and operable to assume either an active or a non-active state, for outputting a second output signal when controlled to assume an active state, including a second adjustment circuit, and a second input buffer.

Abstract: The invention relates to a frequency adjusting apparatus and the method therefor comprising an adjusting module, a comparing module, a processing module and an operating module. The adjusting module generates a frequency signal according to a predetermined signal after receiving a trigger signal and generates N adjusting signal according to N processing signal. The comparing module compares the N adjusting signal with the predetermined signal according to a predetermined manner and generates N comparing result. The processing module generates N processing signal according to the N comparing result. The operating module executes a specific operation with M adjusting signal of the N adjusting signal matching the predetermined rule and generates a operation signal, wherein the frequency of the operation signal is approximately equal to which of the predetermined signal. Wherein N and M are natural numbers and N?M?1, the adjusting module adjusts the operation frequency according to the operation signal.

Abstract: A frequency error detecting circuit includes: an oscillator; a frequency converting unit for a received signal on the basis of the oscillation output and output the received signal; a time-to-frequency converting unit configured to convert the output of the frequency converting unit into a frequency domain signal; a frequency shift determining unit configured to determine presence or absence of a frequency shift between an output frequency of the frequency converting unit and a predetermined carrier frequency; and a control unit configured to repeat frequency conversion processing and time-to-frequency conversion processing while controlling an oscillation frequency of the oscillator on the basis of a determination result of the frequency shift determining unit and cause the output frequency of the frequency converting unit to converge on a predetermined value to thereby detect a frequency error between the frequency of the received signal and the predetermined carrier frequency.

Abstract: A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals.

Abstract: A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count.

Abstract: A charge pump includes a current source configured to generate a first current and a switch circuit including an output node and connected to the current source. The switch circuit is configured to be switched to provide one of the first current to the output node or discharge a second current from the output node according to a phase difference between a reference signal and a feedback signal. The switch circuit is further configured to compare a charge supplied to the output node and a charge discharged from the output node and to adjust an inflow time of the first current to the output node or an outflow time of the second current from the output node according to the comparison result.

Abstract: A method and a measuring device for synchronizing measuring channel assemblies are provided. A reference signal is produced by a reference signal source. The reference signal is supplied to the individual measuring channel assemblies of the measuring device. A clock signal generator is used to produce a clock signal at a low frequency, the clock signal generator being connected to each measuring channel assembly by a respective connecting line of the same length. The clock signal is supplied through a phase corrector element for the purpose of correcting the phase of the reference signal in each measuring channel assembly to the phase of the clock signal.

Abstract: A device includes a first circuit unit performing a detecting operation to detect a ratio of a first time period in which an input signal takes a first logic level to a second time period in which the input signal takes a second logic level. The first circuit unit includes a storing unit and storing a detection result of a detection thereby to the storing unit thereof. The device includes a first control circuit controlling the first circuit unit in response to the input signal. The device includes a current source circuit coupled to the first control circuit at a first circuit node thereof. The device includes an initialization circuit performing an initializing operation to initialize the detection result of the storing unit of the first circuit unit.

Abstract: The invention discloses a signal converting device, and more particularly, to a signal converting device that improves the signal quality. The signal converting device comprises a first input end, a second input end, an output end, a first circuit and a second circuit. The first circuit is coupled between the first input end and the output end. The first circuit determines whether to charge up the output end to generate an output signal or not according to a first differential input signal. The second circuit is coupled between the second input end and the output end. The second circuit determines whether to discharge the output end to generate the output signal or not according to a second differential input signal.

Abstract: A flop circuit comprises a precharge circuit for precharging a first node in response to an occurrence of a first phase of a timing signal, and a discharge circuit for conditionally discharging the first node in response to an occurrence of a second phase of the timing signal depending upon a data input signal. The flop circuit further comprises a voltage retention circuit, such as a latch, configured to store a retained logic value that depends upon a logic value present at the first node during at least a portion of the second phase of the timing signal, and an output circuit configured to generate an output signal that depends upon the data input signal. The output circuit may be configured to drive the output signal in a first logic state when the first node is discharged regardless of the retained logic value, and may be configured to drive the output signal in a logic state that depends upon the retained logic value when the first node is charged.

Abstract: This invention relates to a device, a method, a system, wherein at least two mixer units are associated with at least two different mixer frequencies, and wherein each of said mixer units comprises a first input configured to receive at least one input signal to be mixed, and wherein at least one amplifier is coupled to said at least two mixer units, wherein each of said at least one amplifier is coupled to at least two outputs of at least two different mixer units of said at least two mixer units.

Abstract: An object is to provide a conduction switching circuit, an operation method of a conduction switching circuit, and a conduction switching circuit block, which can prevent a leakage of a high frequency signal without insertion loss of a reactance. A conduction switching circuit includes a first MOSFET, a second MOSFET connected to the first MOSFET via a first node, and a first control terminal connected to the first node. The first MOSFET and the second MOSFET are provided so as to be electrically connected in series at ON state. The first control terminal is configured to apply a voltage to the first node so that capacitance of the first MOSFET and the second MOSFET is decreased when the first MOSFET and the second MOSFET are OFF state.

Abstract: To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.

Abstract: The present invention is directed to improve reliably of an on-chip redundancy system by preventing influence of a physical failure exerted on an entire semiconductor chip. A comparator measure for comparing outputs of an on-chip redundancy system is mounted on a semiconductor chip different from the on-chip redundancy system. The another semiconductor chip is, preferably, mounted on a semiconductor chip on which a power source circuit for supplying power to the on-chip redundancy system redundantly having the comparing function in the chip, a driver circuit for driving an output circuit, and the like are mounted. With the configuration, the influence of a failure occurring in the on-chip redundancy system can be prevented from being exerted on the comparator measure.

Abstract: A voltage conversion circuit with reduced power consumption can be used for a power supply device (100). The power supply device (100) is composed of a power supply circuit (3) including an alternating power supply (1) and a rectifying circuit (2); a voltage conversion circuit (6) including a plurality of capacitors (4) and a switching circuit (5); and a load circuit (7). The voltage conversion circuit (6) is connected between the power supply circuit (3) and the load circuit (7). The alternating power supply (1) is connected to a switching circuit (5) of the voltage conversion circuit (6) without having the rectifying circuit (2) in between. An output voltage (potential fluctuation: a potential difference generated in the signal waveform of the power supply voltage) from the alternating power supply (1) prior to rectification is applied to the switching circuit (5).

Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Abstract: A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

Abstract: Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.

Abstract: A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

Abstract: A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.

Abstract: A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Abstract: A noise suppression device includes: conversion means which converts an input signal into a frequency region signal for each predetermined first frame; frame generation means which generates a second frame which is different from the first frame; representative frequency region signal generation means which generates a representative frequency region signal from the frequency region signal of the first frame contained in the second frame; and noise suppression degree calculation means which obtains a noise suppression degree of the second frame according to the representative frequency region signal.

Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

Abstract: A phase mismatch compensation device comprises a first low pass filter unit, a second low pass filter unit and a phase compensation unit. The first low pass filter unit comprises a first input unit transferring the I-channel analog input signal to an input terminal of a first OP-amp, and the first self-feedback unit transferring the I-channel output signal to the input terminal of the first OP-amp. The second low pass filter unit comprises the second input unit transferring the Q-channel analog input signal to an input terminal of a second OP-amp, and a second self-feedback unit transferring the Q-channel output signal to the input terminal of the second OP-amp. The phase compensation unit comprises a first compensation unit transferring the Q-channel analog input signal to the input terminal of the first OP-amp, and a second compensation unit transferring the I-channel analog input signal to the input terminal of the second OP-amp.

Abstract: A bias circuit for applying a bias voltage to a nonlinear amplification circuit, including a constant-current source; and a first, second, third, and fourth transistors, wherein a current mirror circuit is configured by the first transistor and the second transistor, and the bias voltage is outputted from the drain of the second transistor, gate lengths and gate widths of the first and second transistor are the same, gate lengths of the first to fourth transistor are the same, and gate lengths and gate widths of the first, second, third, and fourth transistor are configured so that k4?0.5?k3?0.5 is approximately 1, where k3 stands for a ratio of a gate width of the third transistor to the gate width of the first transistor and k4 stands for a ratio of a gate width of the fourth transistor to the gate width of the first transistor.

Abstract: A frequency synthesizer with multiple tuning loops, e.g., a fine tuning loop and a coarse tuning loop, is described. The fine tuning loop may operate over a limited tuning range and may have fine frequency resolution. The coarse tuning loop may operate over a wide tuning range and may have coarse frequency resolution. The fine tuning loop may receive a reference signal at a reference frequency and generate a fine tuning signal at a first frequency adjustable in fine steps. The coarse tuning loop may receive the reference signal, generate an output signal at an output frequency, and generate a coarse tuning signal at a second frequency based on the output signal and the fine tuning signal. The second frequency may be adjustable in coarse steps, e.g., in integer multiples of the reference frequency. The output frequency may be determined based on the first frequency and the second frequency.

Abstract: A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal.

Abstract: In a Hartley voltage controlled oscillator (VCO) circuit comprising two inductors (Ld, Lg), a transistor (Q1) and a varactor (C), the two inductors (Ld, Lg) are arranged as a coupled inductor pair to enable positive mutual inductance (M) between them and reduce the size of the VCO.

Abstract: There is provided a piezoelectric vibrator that can hold the crystal plate parallel to the base substrate regardless of the shape of the crystal plate. A method for manufacturing the piezoelectric vibrator, and an oscillator are also provided. The piezoelectric vibrator includes a base substrate; a lid substrate; a piezoelectric vibrating piece including a crystal plate having on its outer surface excitation electrodes and mount electrodes; through electrodes provided in through holes formed through the base substrate; inner electrodes formed on the upper surface of the base substrate; and metal bumps formed at predetermined positions of the inner electrodes. The piezoelectric vibrating piece is tapered towards the ends along the longitudinal direction, and mounted on the metal bumps in a cantilever fashion.

Abstract: The invention provides a method for manufacturing a piezoelectric vibrator, a piezoelectric vibrator, and an oscillator, whereby mounting of the piezoelectric vibrating piece by flip-chip bonding is ensured. A manufacturing method of a piezoelectric vibrator is a method for manufacturing a piezoelectric vibrator that includes: a base substrate; a lid substrate bonded to the base substrate; a piezoelectric vibrating piece including a crystal plate having on its outer surface excitation electrodes, and mount electrodes electrically connected to the excitation electrodes; inner electrodes to be electrically connected to the piezoelectric vibrating piece; and metal bumps to provide electrical interconnections between the inner electrodes and the mount electrodes.

Abstract: The invention provides a method and an apparatus for manufacturing a glass-sealed package, whereby anodic bonding of a pair of wafers is ensured over substantially the whole area of the wafers, and whereby a vacuum is ensured inside the cavity during the anodic bonding of the wafers. The invention also provides an oscillator having such characteristics. The manufacturing method of a glass-sealed package includes the step of anodically bonding a pair of wafers by applying voltage to positions corresponding to circumferential portions of the wafers stacked in layers, and the step of dividing the pair of anodically bonded wafers into individual pieces. A through hole is formed at a central portion of at least one of the wafers, and the anodic bonding of the wafers is made by applying voltage using a plurality of electrodes disposed at the positions corresponding to the circumferential portions of the wafers.

Abstract: In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape.

Abstract: A micro-strip transmission line capable of reducing far-end crosstalk is provided. The micro-strip transmission line having a serpentine shape is capable of reducing the far-end crosstalk of the transmission line by increasing capacitive coupling between neighboring transmission lines by allowing parallel micro-strip transmission lines to have serpentine shapes. In the structure of the micro-strip transmission line having the serpentine shape, it is possible to reduce the far-end crosstalk of the transmission line by increasing capacitive coupling between neighboring transmission lines by allowing parallel micro-strip transmission lines to have serpentine shapes.

Abstract: A waveguide circulator which does not cause an arcing phenomenon and deterioration of microwave characteristic, even when a ferrite member generates heat to raise a temperature thereof. The waveguide circulator is composed of a waveguide formed substantially in Y-shape with rectangular waveguides which are provided so as to position horizontally on a predetermined plane, and further they are extended in different three directions from junction positions of the waveguide wherein two ferrite members are placed in the junction positions thereof so as to oppose to each other on the upper and lower sides in the height direction perpendicular to the predetermined plane wherein an extended section extending in the height direction in the vicinities of the junction positions of the waveguides is formed, and a distance between the ferrite members is expanded to compensate decreased impedance.

Abstract: The present invention relates to a multiband transmit-receive coupler-separator with a very wide band of the OMT (“OrthoMode Transducer”) type for microwave-frequency telecommunications antennae. This coupler comprises a port for propagating all of the frequencies, a body and a port for propagating high-frequency bands, these three portions being coaxial, and wide-band coupling slots for propagating the low-frequency bands made in the body and each associated with a waveguide, and it is characterized in that its body joining the two ports has a shape of revolution the profile of which changes according to a multipolynomial law, constantly decreasing from the port with the largest cross section to the port with the smallest cross section.

Abstract: Power amplifying systems and modules and components therein are designed based on CRLH structures, providing high efficiency and linearity.

Abstract: An electrical component, e.g., a diplexer or a duplexer, can have one of a number of diverse arrangements for terminal surfaces on the substrate bottom. For example, the terminal surfaces for first and second filters are not disposed at the maximum distance from one another. First and second filters can be disposed as one or two discrete components on the substrate, wherein one filter can be implemented as being integrated in a multilayer substrate.

Abstract: The present disclosure relates to telecommunication, and in particular, to a base station Radio Frequency (RF) duplexer, an RF module, and an RF system. A base station RF apparatus provided herein includes: an enclosure, an intermediate RF processing unit, and a duplexer. The enclosure is located on the duplexer; the intermediate RF processing unit is located inside a cavity enclosed by the enclosure and the duplexer, or on the duplexer; a duplexer cavity and a heat dissipation part exist on the surface of the duplexer; the opening of the duplexer cavity is opposite to or against the enclosure; the heat dissipation part is designed to dissipate heat of the intermediate RF processing unit; and the duplexer is integrally molded. The foregoing technical solution requires no external fasteners, reduces the time of production and assembly. In addition, waterproof design and shielding design are not required, and thus improves the reliability.

Abstract: A left-handed filter of the present invention includes an interstage coupling element connected to a first capacitor and a ground, a second capacitor connected to the interstage coupling element, a third capacitor connected to the second capacitor, a first inductor connected to the connection point of a fourth capacitor and the second capacitor, and the ground, a second inductor connected to a fifth capacitor and the ground, a first input and output coupling element connected to a sixth capacitor, and a second input and output coupling element connected to the third capacitor. The first and second capacitors, the third and sixth capacitors, the first and second inductors, and third and fourth inductors are respectively arranged in symmetrical positions with respect to an interstage coupling element.