Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.

Abstract: A method of manufacturing a reference sample substrate for analyzing a metal contamination level includes coating an organic silica solution including metal impurities on a semiconductor substrate and forming an oxide layer on the semiconductor substrate by thermally treating the semiconductor substrate having the coated organic silica solution. The metal impurities are substantially uniformly distributed in the oxide layer and the metal impurities are positioned at predetermined portions of the oxide layer.

Abstract: A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

Abstract: A high efficiency light-emitting diode and a method for manufacturing the same are described. The high efficiency light-emitting diode comprises: a permanent substrate; a first contact metal layer and a second contact metal layer respectively deposed on two opposite surfaces of the permanent substrate; a bonding layer deposed on the second contact metal layer; a diffusion barrier layer deposed on the bonding layer, wherein the permanent substrate, the bonding layer and the diffusion barrier layer are electrically conductive; a reflective metal layer deposed on the diffusion barrier layer; a transparent conductive oxide layer deposed on the reflective metal layer; an illuminant epitaxial structure deposed on the transparent conductive oxide layer, wherein the illuminant epitaxial structure includes a first surface and a second surface opposite to the first surface; and a second conductivity type compound electrode pad deposed on the second surface of the illuminant epitaxial structure.

Abstract: The present invention provides a semiconductor light emitting device and a method for manufacturing the same. The semiconductor device comprises (i) a semiconductor layer with convex portions in a shape selected from a cone and a truncated cone and (ii) electrodes, wherein in the case of the convex portions with the shape of the truncated cone, the convex portions has a height of from 0.05 to 5.0 ?m and a bottom base diameter of from 0.05 to 2.0 ?m; in case of the convex portions with the shape of the cone, the convex portions has a height of from 0.05 to 5.0 ?m and a base diameter of from 0.05 to 2.0 ?m. A method for manufacturing a semiconductor light emitting device comprising the steps of (a) growing a semiconductor layer on a substrate, (b) forming on the semiconductor layer a region having particles with an average particle diameter of 0.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: A semiconductor composite apparatus includes a semiconductor thin film and a metal layer formed on a substrate. The semiconductor thin film is bonded to the metal layer formed on the substrate. A region is formed between the semiconductor thin film and the metal surface, and contains an oxide of a metal that forms the metal surface. The metal surface is a surface of a metal layer provided on the substrate. The metal surface contains an element selected from the group consisting of Pd, Ni, Ge, Pt, Ti, Cr, and Au. The metal surface is coated with either a Pd layer or an Ni layer.

Abstract: Methods for fabricating light-emitting diode (LED) array structures comprising multiple vertical LED stacks coupled to a single metal substrate is provided. The LED array structure may comprise two, three, four, or more LED stacks arranged in any configuration. Each of the LED stacks may have an individual external connection to make a common anode array since the p-doped regions of the LED stacks are all coupled to the metal substrate, or some to all of the n-doped regions of the LED stacks may be electrically connected to create a parallel LED array. Such LED arrays may offer better heat conduction and improved matching of LED characteristics (e.g., forward voltage and emission wavelength) between the individual LED stacks compared to conventional LED arrays.

Abstract: A method of manufacturing an LED includes the following steps: preparing an LED wafer including a substrate and an epitaxial layer formed on the substrate; cutting the epitaxial layer of the LED wafer into a plurality of LED dies with a gap defined between every two neighboring dies; filling an electrically insulating material in each gap between neighboring LED dies such that the neighboring LED dies are separated from each other by the insulating material; providing a circuit board having a layer of anisotropic conductive adhesive coated thereon; pressing the LED dies against the adhesive to bring the top surfaces of the LED dies into contact with the adhesive such that the LED dies each are electrically connected to the circuit board via the adhesive; and encapsulating the LED dies with a light penetrable material.

Abstract: A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate.

Abstract: A method for manufacturing a light-emitting device comprising the steps of cutting a light-emitting unit by a laser beam, and cleaning the light-emitting unit by an acid solution to remove by-products resulted from the laser cutting.

Abstract: A method for fabricating an array of semiconductor devices comprising the steps of providing a non-metallic substrate, placing a layer of spheres on said substrate, reducing diameter of the spheres, encapsulating the spheres in a matrix of rigid material, finishing an upper surface of said matrix to expose a portion of said spheres, removing the spheres to form an array of cavities within said matrix, and forming features in said cavities in contact with said substrate so as to form the device.

Abstract: Because of a large lattice mismatch between a sapphire substrate and a group III-V compound semiconductor, a good crystal is difficult to grow. A high-quality AlN buffer growth structure A on a sapphire substrate includes a sapphire (0001) substrate 1, an AlN nucleation layer 3 formed on the sapphire substrate 1, a pulsed supplied AlN layer 5 formed on the AlN nucleation layer 3, and a continuous growth AlN layer 7 formed on the pulsed supplied AlN layer 5. Formed on the continuous growth AlN layer 7 is at least one set of a pulsed supplied AlN layer 11 and a continuous growth AlN layer 15. The AlN layer 3 is grown in an initial nucleation mode which is a first growth mode by using an NH3 pulsed supply method. The pulsed supplied AlN layer 5 is formed by using NH3 pulsed supply in a low growth mode which is a second growth mode that increases a grain size and reduces dislocations and therefore is capable of reducing dislocations and burying the nucleation layer 3.

Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.

Abstract: A method for fabricating a micro-electro-mechanical system (MEMS) device. The method comprises placing a guiding mask on an application platform, the guiding mask including an opening that defines the position of a MEMS part to be placed on the application platform. The method further comprises placing the MEMS part into the opening of the guiding mask on the application platform, and removing the guiding mask from the application platform after the MEMS part is bonded to the application platform.

Abstract: Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.

Abstract: A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.

Abstract: An organic semiconductor device with a vertical structure having both functions of an organic thin film transistor and light-emitting element, where the electrical characteristics as both the organic thin film transistor and light-emitting element can be controlled in the case of forming a gate electrode with an organic conductive film, and a manufacturing method thereof. The above organic semiconductor device has such a structure that organic semiconductor films are sandwiched between a pair of electrodes functioning as a source electrode and drain electrode of an organic thin film transistor and also functioning as an anode and cathode of a light-emitting element, a thin organic conductive film functioning as a gate electrode is sandwiched between the organic semiconductor films, and a part of the organic conductive film is electrically connected to an auxiliary electrode, thereby the electrical characteristics as both the organic thin film transistor and light-emitting element can be controlled.

Abstract: Methods directed to avoiding die cracking resulting from die separation are described herein. A method may include providing a substrate including a plurality of dies separated from each other by at least a dielectric material, removing the dielectric material substantially down to the substrate to form gaps between the plurality of dies, and singulating the plurality of dies along the gaps between the plurality of dies.

Abstract: A system is described that can assemble substrates over one another to form a stacked substrate. The various layers of the stacked substrate can be separated from each other by using Coulomb forces. In addition, a beam substrate can be used to increase the separation. In addition, a first substrate can be flipped around and connected to the edge of a second substrate. The instructions for assembly and a FSM (Finite State Machine) can be included in the stacked substrate to pave the way for a self-constructing 3-D automaton. The beam substrate can be used to carry heat, fluids, electrical power or signals between the various layers of the stacked cells besides providing a mechanical support. A stacked substrate can be assembled into 3-D structures. These structures can have applications in antennas and RF circuits, for example.

Abstract: A method for producing a matrix of electromagnetic radiation detectors made up of a plurality of elementary detection modules mounted on an interconnection substrate. The method includes depositing on the interconnection substrate a predefined number of quantities of solder or hybridization material, intended to constitute hybridization bumps for the elementary modules, in at least a first array for the nominal hybridization, and at least one second array, with the deposits of solder or hybridization material of the second array being lower in volume than those of the first array, depositing a liquid flux on the interconnection substrate, mounting the elementary modules to be hybridized on the interconnection substrate, and raising the temperature of a chamber in which the various elements to be hybridized are positioned until reaching at least the melting point of the solder or hybridization material to join the modules and interconnection substrate together by reflow effect.

Abstract: A method for manufacturing a semiconductor device, includes: mounting a semiconductor chip having an electrode on a wiring substrate having a base substrate and a wiring formed on the base substrate; forming a eutectic alloy by contacting the wiring with the electrode and by heating and pressurizing, and; forming the eutectic alloy so as a part of the eutectic alloy enters between the wiring and the base substrate.

Abstract: Insulating films (13, 14) are formed on the surface of a semiconductor wafer (30) on the side on which a plurality of devices are formed. Then, conductor layers (15, 16) are formed to cover opening portions from which electrode pads (12) of each device are exposed. Furthermore, a resist layer (R2) is formed to have opening portions from which terminal formation portions of the conductor layer are exposed, and metal posts (17) are formed on the terminal formation portions of the conductor layer (16) using the resist layer (R2) as a mask. Then, thinning of the semiconductor wafer (30) is performed to a predetermined thickness by grinding the back surface thereof. Thereafter, the resist layer (R2) is removed; an unnecessary portion (15) of the conductor layer is further removed; sealing with sealing resin is performed with the top portions of the metal posts (17) being exposed; metal bumps are bonded to the top portions of the metal posts (17); and the semiconductor wafer is divided into each device.

Abstract: A package and the method for making the same, and a stacked package, the method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.

Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package.

Abstract: A method for producing a device and a device is disclosed. In one embodiment, a component is surrounded by a material. A fluoropolymer-containing compound is produced at a surface of the material. A molding is produced from a material and a fluoropolymer-containing compound is produced at a surface of the molding by a vapor deposition.

Abstract: An image sensing device and packaging method thereof is disclosed. The packaging method includes the steps of a) providing an image sensing module, having a light-receiving region exposed, on a first substrate; b) forming a plurality of first contacts around the light-receiving region on the image sensing module; c) providing a second substrate, having a plurality of second contacts corresponding to the plurality of first contacts and an opening for allowing the light-receiving region to be exposed while the second substrate is placed over the image sensing module, the plurality of second contacts being disposed around the opening; d) connecting the plurality of first contacts and the plurality of second contacts; and e) disposing a transparent lid above the light-receiving region, on a side of the second substrate which is opposite to the plurality of second contacts.

Abstract: According to one embodiment, an electronic package includes a semiconductor die, a heat sink and a metallization layer interposed between the semiconductor die and the heat sink. The metallization layer attaches the semiconductor die to the heat sink. The metallization layer has a thickness of about 5 ?m or less and a thermal conductivity of about 60 W/m·K or greater.

Abstract: A method of making a semiconductor chip assembly includes mechanically attaching a semiconductor chip to a routing line, forming a metal pillar on the routing line, forming an encapsulant that covers the chip and the metal pillar, grinding the encapsulant without grinding the metal pillar, then grinding the encapsulant and the metal pillar such that the encapsulant and the metal pillar are laterally aligned, and then attaching a heat sink to the metal pillar.

Abstract: A semiconductor package of this invention achieves higher wiring densities and increases the degree of freedom of the wiring design. The semiconductor package includes a first substrate having first and second faces, and first wiring provided on the first face of the first substrate. The semiconductor package also includes a second substrate having first and second faces, and second wiring provided on the first face of the second substrate. The semiconductor package also includes a semiconductor chip connected to the first and second wiring. The first face of the first substrate faces the first face of the second substrate, and the first and second wiring intersect one another in three dimensions in an isolated state.

Abstract: A chip multiprocessor die supports optional stacking of additional dies. The chip multiprocessor includes a plurality of processor cores, a memory controller, and stacked cache interface circuitry. The stacked cache interface circuitry is configured to attempt to retrieve data from a stacked cache die if the stacked cache die is present but not if the stacked cache die is absent. In one implementation, the chip multiprocessor die includes a first set of connection pads for electrically connecting to a die package and a second set of connection pads for communicatively connecting to the stacked cache die if the stacked cache die is present. Other embodiments, aspects and features are also disclosed.

Abstract: An integrated circuit structure comprising a fuse and a method for forming the same are provided. The integrated circuit structure includes a substrate, an interconnection structure over the substrate, a fuse connected to the interconnection structure, and an anti-reflective coating (ARC) on the fuse. The ARC has an increased thickness and acts as a remaining oxide, and no further remaining passivation layer exists on the ARC.

Abstract: A method for manufacturing a pixel structure is provided. A gate and a gate insulating layer are sequentially formed on a substrate. A semiconductor layer and a second metal layer are sequentially formed on the gate insulating layer. The semiconductor layer and the second metal layer are patterned to form a channel layer, a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and drain are disposed on a portion of the channel layer. The gate, channel, source and drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.

Abstract: A method for manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line, forming a photoresist film, on the conductor layer, patterning the photoresist film to form a photoresist pattern including a first portion and a second portion having a greater thickness than the first portion, etching the upper layer and the lower layer by using the photoresist pattern as art etch mask, etching the silicon layer by using the photoresist pattern as an etch mask to form a semiconductor, removing the second portion of the photoresist pattern by using an etch back process, selectively wet-etching the upper layer of the conductor layer by using the photoresist pattern as an etch mask, dry-etching the lower layer of the conductor layer by using the photoresist pattern as an etch mask to form a data line and a drain electrode including remaining upp

Abstract: A fabrication method of a multi-domain vertical alignment pixel structure includes providing a substrate, forming a gate on the substrate, and forming an insulating layer on the substrate. A channel layer and a semiconductor layer are formed on the insulating layer. A source, a drain, and a capacitor-coupling electrode are formed. A passivation layer is formed to cover the source, the drain, a part of the channel layer, and a part of the semiconductor layer. A via hole is formed in the passivation layer to expose the drain, and a trench is formed in the passivation layer and the insulating layer. A lateral etched groove on the sidewall of the trench is formed to expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively.

Abstract: Provided is a liquid crystal display (LCD) device and a fabrication method thereof. An array substrate for the LCD includes a gate line formed on a substrate, and a gate electrode extending from the gate line; a data line intersected with the gate line, wherein the data line is configured with a gate insulating layer, a semiconductor layer and a data metal layer; a pixel electrode formed of a first transparent metal layer at a pixel which is defined by an intersection of the gate line and the data line; a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode by a predetermined distance to expose a channel; and a second transparent metal layer pattern formed on the data line, the source electrode and the drain electrode, wherein the second transparent metal layer connects the drain electrode and the pixel electrode to each other.

Abstract: Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

Abstract: An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.

Abstract: A method for fabricating MOS-FET using a SOI substrate includes a process of ion implantation of an impurity into a channel region in a SOI layer; and a process of channel-annealing in a non-oxidized atmosphere. In the ion implantation process, a concentration peak of the impurity is made to exist in the SOI layer. Moreover in the channel-annealing process, the impurity is distributed with a high concentration in the vicinity of the surface of the SOI layer under the following condition with the anneal temperature as T (K) and annealing time as t (minutes): 506×1000/T?490<t<400×1000/T?386.

Abstract: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

Abstract: Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.

Abstract: By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the memory region, thereby enhancing overall stability of respective memory cells. On the other hand, enhanced strain levels may be obtained in the speed-critical device region by performing an efficient amorphization process and re-crystallizing amorphized portions, for instance, in the presence of a rigid material to provide a desired high strain level.

Abstract: Methods of processing silicon substrates to form metal silicide layers thereover having more uniform thicknesses are provided herein. In some embodiments, a method of processing a substrate includes providing a substrate having a plurality of exposed regions comprising silicon, wherein at least two of the plurality of exposed regions have a different rate of formation of a metal silicide layer thereover; doping at least one of the exposed regions to control the rate of formation of a metal silicide layer thereover; and forming a metal silicide layer upon the exposed regions of the substrate, wherein the metal silicide layer has a reduced maximum thickness differential between the exposed regions.

Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Abstract: Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrificial cell gate stacks are then removed such that the spacer layers around the sacrificial cell gate stacks are still intact. BJT cell stacks are then formed in the space between the spacer layers where the sacrificial cell gate stacks were formed and removed, the BJT cell stacks including an emitter layer. A phase change layer above the emitter contacts and an electrode above the phase change layer are then formed.

Abstract: A memory cell of a memory device is fabricated by forming a first electrode on a substrate, positioning a photo mask at a first position relative to the substrate, and forming a first material layer on the first electrode based on a pattern on the photo mask. The photo mask is positioned at a second position relative to the substrate, and a second material layer is formed above the first material layer based on the pattern on the photo mask, the second material layer being offset from the first material layer so that a first sub-cell of the memory cell includes the first material layer and not the second material layer, and a second sub-cell of the memory cell includes both the first and second material layers. A second electrode is formed above the first and second material layers.

Abstract: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.

Abstract: A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.

Abstract: A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.

Abstract: When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.