Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

Abstract: Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the ILD. Next, a getter layer is formed on the protection layer to remove any native oxides on the protection layer. A capping layer is then deposited on the getter layer to prevent oxidation of the getter layer. Next, a semiconductor layer is formed on the capping layer. An oxide layer is then deposited on the semiconductor layer. Subsequently, a buffered oxide etch solution is used to remove the oxide layer. By removing the native oxides on the protection layer, the getter layer prevents the reaction between the buffered oxide etch solution and the native oxides which may cause delamination of the semiconductor layer and protection layer.

Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.

Abstract: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on a principal surface of the semiconductor substrate and having a multiple-layered interconnect layer; and a heterostructure magnetic shield covering the semiconductor element. The heterostructure magnetic shield includes a first magnetic shield layered structure and a second magnetic shield layered structure that covers the first magnetic shield layered structure. Each of a first and a second magnetic shield layered structures includes a magnetic shielding film composed of a magnetic substance and covering the semiconductor element and a buffer film disposed between the semiconductor element and the magnetic shield films and preventing a diffusion of the magnetic substance.

Abstract: A semiconductor device has a substrate containing a conductive layer. An interconnect structure is formed over the substrate and electrically connected to the conductive layer. A semiconductor component is mounted to the substrate. An encapsulant is deposited over the semiconductor component and interconnect structure. A channel is formed in the encapsulant to expose the interconnect structure. Solder paste is deposited in the channel prior to forming the shielding layer. A shielding layer is formed over the encapsulant and semiconductor component. The shielding layer can be conformally applied over the encapsulant and semiconductor die and into the channel. The shielding layer extends into the channel and electrically connects to the interconnect structure. A docking pin is formed on the shielding layer, which extends into the channel and electrically connects to the interconnect structure. A chamfer area is formed around a perimeter of the shielding layer.

Abstract: Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The packages also contain multiple chips that are stacked vertically. The chips are connected through stud bumps, printed interconnect structures, and conductive pillars formed with the package. The packages also contain two different moldings layers that together operate as an encapsulation material. The semiconductor packages contain a full land pad array at both the bottom and the top of the package, allowing the packages to be used in a package-on-package configuration. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described.

Abstract: A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.

Abstract: A semiconductor package capable of being efficiently stacked and a method of manufacturing the same is presented. The semiconductor package includes a semiconductor chip, an insulation layer, and a through-electrode. The semiconductor chip has a first surface and a second surface, a circuit section in the semiconductor chip, an internal circuit pattern electrically connected to the circuit section, and a through-hole that passes through the internal circuit pattern and through the first and second surfaces. The insulation layer is on a through-hole of the semiconductor chip and has an opening which exposes the internal circuit pattern which was exposed by the through-hole. The through-electrode is in the through-hole and electrically coupled to the internal circuit pattern which is exposed through the opening of the insulation layer.

Abstract: An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

Abstract: A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a second main face, with the second main face of the chip island defining at least one cavity.

Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: Various semiconductor chip packages and methods of assembling and making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a stiffener frame to a first side of a substrate. The stiffener frame has a central opening to accommodate a semiconductor chip and an outer edge surface. A semiconductor chip is coupled to the first side in the opening. A lid is coupled to the stiffener frame with an adhesive. The lid has a first edge surface set back from the outer edge surface of the stiffener frame. The adhesive is set back from the outer edge surface of the stiffener frame.

Abstract: A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.

Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire.

Abstract: A semiconductor element (101) includes an electrode section (102) and a bump (105), a circuit board (103) includes an electrode section (104) and a bump (106), and a conductive filler (108) having a lower melting point than the melting points of the bumps (105, 106) electrically bonds the bumps (105, 106) to each other.

Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.

Abstract: A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier.

Abstract: The electric component includes at least a set of electrode terminals 2, 3, a semiconductor element 4 electrically connected with the set of electrode terminals, and a package 6 made of synthetic resin and sealing the electrode terminals and the semiconductor element with part of a lower surface of each of the electrode terminals exposed at a lower surface of the package. A cover layer 11 made of synthetic resin is formed to cover a cut surface of a tip of a connector lead remainder extending integrally outward from the each of the electrode terminals. Thus, disadvantages resulting from exposure of the cut surface of the tip of the connector lead remainder are eliminated.

Abstract: T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.

Abstract: A semiconductor device is provided. A substrate is provided. A buried layer is formed in the substrate. The buried layer comprises an insulating region. A deep trench contact structure is formed in the substrate. The deep trench contact structure comprises a conductive material and a liner layer formed on a side wall of the conductive material. The conductive material is electrically connected with the substrate.

Abstract: At least one terminal contact surface (1) is formed on a topmost metal plane (2). Under it, in a secondmost metal plane (3), is a reinforcement region (8), in which the secondmost metal plane (3) is structured within its two-dimensional extent such that a part of the area of the vertical (with respect to the metal plane) projection of the terminal contact surface (1) onto the secondmost metal plane (3) that is occupied by the metal of the secondmost metal plane (3) amounts to at least one third of the area.

Abstract: A semiconductor device comprises a substrate, a conductive layer deposited on a substrate and an epitaxial layer deposited on the conductive layer. The conductive layer is patterned to include a first pattern. The first pattern includes a major surface and a plurality of grids defined in the major surface. The major surface includes a plurality of first lines and a connecting portion. The connecting portion is connected to an electrode. The epitaxial layer covers the grids and the first lines between the adjacent grids.

Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.

Abstract: Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed toward a method for packaging a microelectronic device that includes coupling an active side of a microelectronic die to a surface of a support member. The microelectronic die can have a backside opposite the active side, a peripheral side extending at least part way between the active side and the backside, and at least one through-wafer interconnect. The method can further include applying an encapsulant to cover a portion of the surface of the support member so that a portion of the encapsulant is laterally adjacent to the peripheral side, removing material from a backside of the microelectronic die to expose a portion of at least one through-wafer interconnect, and applying a redistribution structure to the backside of the microelectronic die.

Abstract: A method of manufacture of an integrated circuit communication system including providing a semiconductor wafer; and fabricating a cross-over current mirror driver on the semiconductor wafer for generating a crossing point at a reference voltage.

Abstract: Disclosed are a system and method of separate probe and bond regions of an integrated circuit (IC). An IC, an I/O region adjacent to the core region to enable the core region, and a die metal interconnect separating a bond pad area in the I/O region from a probe pad area outside the I/O region of the IC are disclosed. The die metal interconnect may have a length that is greater than the bond pad area length and/or the probe pad area length, and a width that is less than the bond pad area width and/or the probe pad area width. An in-front staggering technique may be used at a die corner of the IC to maintain the bond pad area in the I/O region, and a side staggering technique may be used at the die corner of the IC to maintain the bond pad area in the I/O region.

Abstract: A protective coating is formed on the surface of a semiconductor device. The surface is located on the side to which an extension portion of a wire connected to a pad of the semiconductor device is pulled. The protective coating is formed such that its height decreases toward the pad.

Abstract: The device includes at least one optoelectronic component positioned on a substrate and at least one transparent face. The component is covered by a packaging layer which includes at least one barrier layer and a moisture-reactive layer. The reactive layer includes a moisture-reactive material chosen from alkaline-earth metals, alkali metals and organo-metallic derivatives. The material can be positioned in the moisture-reactive layer in the form of a continuous layer or in the form of a plurality of nodules dispersed in an organic matrix.

Abstract: A microbubble gas-liquid mixing device is fitted and disposed in a sanitary fixture, wherein the sanitary fixture has at least one faucet and the water source treated by the microbubble gas-liquid mixing device is introduced into the faucet. The microbubble gas-liquid mixing device comprises a pump and a spiral tube, and air enters the pump and spiral tube through a first gas inlet valve disposed at the front end of the pump and is therein mixed with the water source in a gas-liquid phase to form a large amount of fine bubbles, thereby achieving the effect of increasing the oxygen content in water.

Abstract: A static fluid mixer which can perform processing such as generation of ultrafine uniform bubbles and has small pressure loss. A static fluid mixer has mixing units having outflow openings for allowing fluid having passed through mixing flow paths to flow through the outflow openings. The mixing units are arranged in a tubular casing body at intervals in the axis direction of the casing body. Adjacent mixing units and the casing body forma flow path forming space. Each mixing unit has an annular outflow path communicating with the end of each mixing flow path. The annular outflow path is open in a ring-like form having a substantially constant width along the entire circumference. The opening at the end of the annular outflow path functions as an outflow opening connecting to the flow path forming space.

Abstract: A vapor distributor for use in atmospheric or vacuum columns includes a new design of vapor inlet device, or vapor horn, to provide superior mixing and distribution of a tangential first feed and a vertical second feed. New vapor inlet device has an inlet dividing the first feed into two portions, each flowing in respective housings in opposed circulation directions, and a plurality of vanes for redirection of vapor. Mixing and distribution of feeds by the vapor distributor is further enhanced by inclusion in vapor distributor of a mixer and vapor directing plates.

Abstract: A rare earth-doped core optical fiber of the present invention includes a core comprising a silica glass containing at least aluminum and ytterbium, and a clad provided around the core and comprising a silica glass having a lower refraction index than that of the core, wherein the core has an aluminum concentration of 2% by mass or more, and ytterbium is doped into the core at such a concentration that the absorption band which appears around a wavelength of 976 nm in the absorption band by ytterbium contained in the core shows a peak absorption coefficient of 800 dB/m or less.

Abstract: The instant invention pertains to a method and a fluid composition for producing contact lenses with improved lens quality and with increased product yield. The method of the invention involves adding a phospholipid into a fluid composition including a lens-forming material in an amount sufficient to reduce an averaged mold separation force by at least about 40% in comparison with that without the phospholipids.

Abstract: The instant invention pertains to a method and a fluid composition for producing contact lenses with improved lens quality and with increased product yield. The method of the invention involves adding a phospholipid into a fluid composition including a lens-forming material in an amount sufficient to reduce an averaged mold separation force by at least about 40% in comparison with that without the phospholipids.

Abstract: In a method for manufacturing a lens mold, a raw mold is provided. The raw mold defines a cavity therein. The cavity defines a raw molding surface. The raw molding surface includes a molding surface portion. The molding surface portion includes a center. Photoresist material is filled in the cavity, covering the molding surface portion. A photo mask is provided. The photo mask defines a through hole. The size through hole is the same as the molding surface portion of the lens mold. The photo mask is placed above the photoresist material with the through hole aligned with the center. The photoresist material is exposed and developed to form a photoresist portion. A rigid molding material is filled in the cavity. The resist portion is removed to expose the molding surface.

Abstract: A method for producing a retardation film by a tenter method, in which a thermoplastic resin film 20 is stretched in the width direction thereof while heating the film with hot air supplied from blowout ports of a plurality of nozzles 30, 32 provided on the upper and lower portions of an oven 100, having a preheating step of heating the thermoplastic resin film 20 with hot air; a stretching step of stretching the thermoplastic resin film 20 preheated while heating it with hot air to obtain a stretched film 22; and a heat setting step of heating the stretched film 22 with hot air, in which, in the preheating step, the stretching step and/or the heat setting step, an air blow velocity at the blowout port of hot air to be used is 2 to 12 m/second and air blow amount per nozzle is 0.1 to 1 m3/second per meter of the length of the nozzle along the width direction of the film.

Abstract: A method for producing nanoparticles which includes dissolving a solute into a solvent forming a solution, feeding the solution through a liquid entrance port of a convergent-divergent nozzle; feeding a carrier gas into a gas entrance port of the nozzle, mixing the solution and the carrier gas prior to entering the nozzle, upon exiting the nozzle the solution is atomized to micron sized droplets, and the evaporating the solvent and leaving behind solid state nanoparticles of the solute.

Abstract: A resin infusion mold tool system for use in a vacuum assisted resin transfer molding process with a subsequent pressure bleed step. The mold tool system includes a mold assembly having an outer mold line tool connected to resin supply lines and supplying resin to the preform. A plurality of inner mold line tools form a hard interface with the inner mold line of the fiber preform and are held to within tight tolerances by an external locating fixture. Excess resin is drawn out of the fiber preform using a vacuum bag connected to vacuum lines and disposed over the inner mold line tools but not between the tools and the fiber preform. The mold assembly is placed in an autoclave, the resin supply lines are detached and the autoclave pressurized to bleed additional resin out of the preform to raise the fiber volume of the composite structure.

Abstract: Methods to fabricate high aspect ratio powder composite microstructures is provided by filling a molding composition containing a powdered material and a binder into a patterned mold, and releasing the cured composite microstructures from the mold. An alternate method is by filling a mix of powdered dense metals and low-melt alloys into a patterned mold, and releasing the melted and solidified composite microstructures from the mold. The mold is derived from lithographically defined parent mold. One example of the application is in the field of x-ray anti-scatter grids and nuclear collimators.

Abstract: Disclosed is a method for manufacturing a fiber-reinforced composite sabot for use in APFSDS (Armor Piercing Fin Stabilized Discarding Sabot) wherein a plurality of fiber mats are laminated instead of one-directional prepreg ply and whole part is reinforced by stitching through long fiber bundle in order to enhance circumferential shear strength, and high quality fiber-reinforced composite sabot is manufactured in a short time using resin-injection vacuum assisted resin transfer molding after stitching.

Abstract: A cold-shrinkable type rubber insulation sleeve includes a reinforced insulation sleeve, a semiconductive stress-relief cone, an internal semiconductive layer, and an external semiconductive layer. The reinforced insulation sleeve, the semiconductive stress-relief cone, and the internal semiconductive layer are formed by molding, and the external semiconductive layer is formed by coating.

Abstract: A compression molding which is high in both dimensional accuracy and mechanical strength is difficult to manufacture by a powder molding process. Especially, a molding including a soft magnetic material with high soft magnetic properties is difficult to manufacture. A composite metal molding according to the present invention includes metal particles and the carbide of a resin intervening among the particles. It is manufactured by coating metal particles with a resin, molding the prepared molding material under pressure into a predetermined shape, and heating the prepared pressurized preform to calcine the resin and weld mutually the particles. The carbide of the resin has a weight ratio of 0.001 to 2% to the metal particles when the particles have their proportion expressed as 100. The particles have a weld ratio of 10 to 80%. The particles preferably contain a soft magnetic material and the resin is preferably a furan resin.

Abstract: A decorative surface covering includes a fabric; and a layer of molded resin disposed on said fabric, where the resin is molded into decorative features of the covering. A method of forming a decorative surface covering includes molding resin disposed on a fabric to produce decorative features, the resin adhering to the fabric.

Abstract: The invention relates to a device for granulating plastic strands having a cutting wheel (15), the individual blades of which graze past a counter blade (2) disposed in a blade carrier (1) when the cutting wheel is rotated, thus cutting the plastic strands (13) being guided over the counter blade into a granulate (14), wherein a rail (3a, 3b) composed of hard material running parallel to the counter blade is disposed adjacent to the counter blade and after said counter blade in the rotational direction of the cutting wheel that collects cut granulate and conducts said granulate into a discharge channel.

Abstract: The present invention relates to a method of forming air holes in a hollow fiber membrane module for water treatment. A main object of the present invention is to easily form air holes in the potting material injected into the module housing to prevent contamination of the hollow fiber membranes in the module housing.

Abstract: The invention relates to a method and a device for producing parts that are made up of more than one component. The first part (17) is produced in a first plane (10) and then transported by a transfer system (15) into a second plane (11).