Abstract: The present invention relates to a device capable of producing a high resolution chemical analysis of a sample, such as fluid, based upon nuclear magnetic resonance (NMR) spectroscopy, where the nuclear magnetic polarizations of the sample are generated by sequentially illuminating the sample with a focused beam of light carrying angular orbital angular momentum (OAM) and possibly momentum (spin). Unlike in usual NMR used for magnetic nuclear resonance imaging (MRI) or spectroscopy, the invention does not make use of a strong magnet.

Abstract: In a method for examination subject-specific determination of parameters for activating gradient coils and radio-frequency of a coil array of a magnetic resonance device to generate a radio-frequency pulse with which nuclear spins in an examination region of an examination subject are moved out of a rest state by an arbitrary angle, a control unit activates phases and amplitudes of currents in the radio-frequency coils and respective currents in the gradient coils in a time-dependent manner in discrete steps to generate gradient fields. In a processor in communication with the control unit, parameters for the activation are automatically calculated dependent on measured sensitivity maps of the radio-frequency coils at the examination subject. The processor optimizes a non-linear equation system within the numerical calculation of the parameters involving a desired magnetization and a theoretical calculated real magnetization.

Abstract: In a device and a method to determine SAR for a magnetic resonance tomography transmission system with multiple antenna elements, a single-column cross-correlation matrix of an antenna element matrix of antenna element values of multiple antenna elements of the magnetic resonance tomography transmission system is determined for each of multiple points in time or time periods. These single-column cross-correlation matrices are added into a sum cross-correlation matrix over a summation time period and the sum cross-correlation matrix is multiplied with a hotspot sensitivity matrix. The hotspot sensitivity matrix represents the sensitivities in at least one direction at a number of hotspot points in a subject located in the magnetic resonance tomography transmission system. The product of the sum cross-correlation matrix and the hotspot sensitivity matrix is multiplied with a value representing the dielectricity at least one hotspot point in order to determine a respective SAR value for hotspot points.

Abstract: The ultra-sensitive susceptibility detection apparatus of anharmonic resonance measurement type using an atomic magnetometer detects a change in susceptibility by a specimen containing an object to be measured. The apparatus includes an atomic magnetometer. The atomic magnetometer includes a cell containing an alkaline metallic atom, a light source for magnetically polarizing the alkaline metallic atom of the cell, and a bias magnetic field applicator for applying a bias magnetic field to adjust a measuring resonance frequency of the alkaline metallic atom.

Abstract: In MR imaging, the patient is placed on the table in a configuration convenient for a surgical procedure and while in the configuration the patient is moved into the field of view by moving the magnet longitudinally and the table is moved in the bore relative to the magnet so as to optimize the part to be imaged within the field of view of the magnet. After imaging the table is moved back to the preset position and removed from the magnet for the surgical procedure to commence or continue. The movement includes movement along the longitudinal axis; transverse movement side to side; rolling movement about a longitudinal axis; tilting movement about a transverse axis and bending movement of the table relative to at least one transverse hinge line in the table at a position spaced from the ends of the table.

Abstract: A magnetic resonance imaging (MRI) apparatus sequentially transmits a plurality of radio frequency (RF) pulses for refocusing transverse magnetization of spins, and brings the transverse magnetization of the spins to longitudinal magnetization after the refocusing of the transverse magnetization of the spins.

Abstract: A life test device comprises an oven, a current source, a voltage meter, a control module, and a process module. A light-emitting diode (LED) is disposed in the oven. The temperature of the oven is gradually changed in a first period and remains at a set temperature in a second period. The current source provides a first current and a second current to the LED. The voltage meter measures forward voltages of the LED. The control module controls the current source to output the first or second current to the LED and controls the voltage meter to measure the forward voltages of the LED. The process module calculates a junction temperature of the LED according to the forward voltages and a variation relationship formula between the forward voltages and the temperature of the oven.

Abstract: Described herein is a method and apparatus for diagnosing processing equipment with a multi-diagnostic device. In one embodiment, a multi-diagnostic device is located in a plasma processing environment and includes an electronic circuitry. The device includes a first array of sensors and a second array of sensors. The circuitry is used to simultaneously (or nearly simultaneously) measure the distributions of ion saturation current and the potential at the device using the first array of sensors and to measure resistances of the second array of sensors to determine the distribution of the temperature at the surface of the device.

Abstract: According to one aspect, the disclosure is directed to an example embodiment in which a circuit-based arrangement includes a circuit-based substrate securing a channel, with an effective width that is not limited by the Debye screening length, along a surface of the substrate. A pair of reservoirs are included in or on the substrate and configured for containing and presenting a sample having bio-molecules for delivery in the channel. A pair of electrodes electrically couple a charge in the sample to enhance ionic current flow therein (e.g., to overcome the electrolyte screening), and a sense electrode is located along the channel for sensing a characteristic of the biological sample by using the electrostatic interaction between the enhanced ionic current flow of the sample and the sense electrode. Actual detection occurs by using a charge-signal processing circuit to process the sensed charge signal and, therefrom, provide an output indicative of a signature for the bio-molecules delivered in the channel.

Abstract: A system and method are provided for testing an integrated circuit (IC) using thermally induced noise analysis. The method provides an IC die and supplies electrical power to the IC die. The IC die surface is scanned with a laser, and the laser beam irradiated locations on the IC die surface are tracked. The laser scanning heats active electrical elements underlying the scanned IC die surface. A frequency response of an IC die electrical interface is measured and correlated to irradiated locations. IC die defect regions are determined in response to identifying location-correlated frequency measurements exceeding a noise threshold. For example, a frequency measurement may be correlated to a die surface location, and if frequency measurement exceeds the noise threshold, then circuitry underlying that surface area may be identified as defective. Typically, die defect regions are associated with measurements in the frequency range between about 1 Hertz and 10 kilohertz.

Abstract: A layout structure of electronic elements includes M*N electronic elements in a form of a matrix, a first test pad group disposed on a first side of the matrix and all electronic elements in the same linear section in the matrix electrically connect to a corresponding test pad in the first test pad group, and a second test pad group disposed on a second side of the matrix and all electronic elements in the same linear section in the matrix electrically connect to a corresponding test pad in the second test pad group.

Abstract: A radio frequency identification (RFID) device and a test method thereof are disclosed. In this test method, the RFID device receives different kinds of tag selection addresses and memory addresses according to a time sharing scheme, so that one or more RFID tags are tested. The RFID device includes a tag chip and a test chip. The tag chip performs a test operation upon receiving a test input signal from an external node, and externally outputs a test output signal indicating a result of the test operation. The test chip tests the tag chip upon receiving an address and data from an external node via a test pad during a test mode.

Abstract: A switch element is configured to decrease an impedance of a voltage-detection integrated circuit that detect voltage between both ends of unit cells of a higher-ordered battery block, for adjacently-connected pair of the higher-ordered battery block and a lower-ordered battery block. The voltage-detection integrated circuit is configured to detect disconnection of an electrical wire when voltage between both ends of a lowest-ordered unit cell that is detected with the switch element turned on is equal to or lower than a threshold.

Abstract: A circuit test jig used for a printed board that includes a circuit board on which a circuit is formed, the circuit test jig includes a holding plate disposed between the circuit board and the print board and holds a plurality of conductive members that transmit signals between a group of terminals of the printed board and a group of terminals of the circuit board, and an elastic plate in which through holes are formed therein disposed at least one of between the holding plate and the circuit board or between the holding plate and the printed board.

Abstract: At least one embodiment is directed to a sensor for measuring a parameter. A signal path of the system comprises an amplifier (612), a sensor element, and an amplifier (620). The sensor element comprises a transducer (4), a waveguide (5), and a transducer (30). A parameter such as force or pressure applied to the sensor element can change the length of waveguide (5). A pulsed energy wave is emitted by the transducer (4) into the waveguide (5) at a first location. The transducer (30) is responsive pulsed energy waves at a second location of the waveguide (5). The transit time of each pulsed energy wave is measured. The transit time corresponds to the pressure or force applied to the sensor element.

Abstract: A noise reducing device for a capacitive touch panel and a method of reducing noise for a capacitive touch panel are disclosed to solve problems related to noise generated by a conventional filter circuit and an integrating circuit or external noise. In the invention, at least one switch circuit is used so that the conventional filter circuit and integrating circuit used in the prior are omitted. Signals output from a current measurement circuit are transmitting to a control unit to calculate the location of a touch point, reducing any noise.

Abstract: In a method of determining interference in a capacitance sensor, a signal is transmitted on a transmitter sensor channel of the capacitive sensor. The signal is received on a receiver sensor channel of the capacitive sensor, the receiver sensor channel being coupled with an amplifier. Behavior of the amplifier is examined for non-linearity to determine if a level of interference has been received by the receiver sensor channel in conjunction with receipt of the signal.

Abstract: A measuring device has a sensor unit and an evaluation unit which is electrically isolated from the sensor unit by a partition wall. The sensor unit includes a first capacitive sensor which is electrically connected to a first coil to form a first oscillating circuit, and a reference capacitor which is electrically connected to a second coil to form a second oscillating circuit. The evaluation unit includes a third coil which is inductively coupled to the first coil and the second coil, and the evaluation unit is designed to determine and output a beat frequency of a beat signal which is inductively injected into the third coil by the first oscillating circuit and the second oscillating circuit.

Abstract: A liquid level, composition and contamination sensor generates an RF signal across a resonant circuit that includes a variable inductor and capacitor. The resulting electromagnetic radiation is propagated into the liquid and changes in impedance and resonance of the resonant circuit that result from changes in the conductivity and dielectric properties of the liquid, which are proportional to liquid content and volume, are detected. The conductivity and dielectric properties of the liquid are measured, based on the changed impedance and resonance of the resonant circuit, and are compared to determine aging and contamination of the urea solution by other liquids. Also, an optical sensor may be submerged in the liquid to determine the refractive index of the liquid. The refractive index of the liquid may be used to determine: if the liquid is water or a urea solution; the concentration of a urea solution.

Abstract: A method for determining resistivity distribution of formations below a bottom of a body of water from transient electromagnetic signals acquired by imparting a transient electromagnetic field into the water and detecting an electromagnetic response thereto at a plurality of spaced apart positions from a place of the imparting includes simulating an air wave response at each of the plurality of spaced apart positions. The simulated air wave response is subtracted from the detected response to produce a subsurface impulse response at each of the plurality of positions. The subsurface impulse responses are used to determine the resistivity distribution.

Abstract: A first measurement device is a measurement device for measuring the concentration of a target substance in a sample deposited on a biosensor, and more particularly is constituted such that at least two kinds of voltage of mutually different levels are applied at mutually different timings to the electrode system of the biosensor, and the concentration is corrected on the basis of the amount of change in the current value.

Abstract: In general, this disclosure is directed to a mixer amplifier that can be utilized within a chopper stabilized instrumentation amplifier. The chopper stabilized instrumentation amplifier may be used for physiological signal sensing, impedance sensing, telemetry or other test and measurement applications. In some examples, the mixer amplifier may include a current source configured to generate a modulated current at a modulation frequency for application to a load to produce an input signal, an amplifier configured to amplify the input signal to produce an amplified signal, and a demodulator configured to demodulate the amplified signal at the modulation frequency to produce an output signal indicating an impedance of the load.

Abstract: In a method for determining the size and shape value (M) for a solid material (S), in particular scrap metal, in an arc furnace (1), an electrode flow fed to an electrode (3a, 3b, 3c) for forming an arc furnace (L) between the electrode (3a, 3b, 3c) and the solid (S) is measured (30) and from the measured electrode flow (I (t)), an effective measurement value of the electrode flow is determined (31) and from the measured electrode flow (I (t)) (32), a flow part associated with a frequency range of the measured electrode flow is determined (32), and a quotient of the flow part and an effective measurement value is formed as a measurement of the shape and size value of the flow (M). Thus, a method is provided that enables a property of a fusible element introduced into one of the arc furnaces to be determined.

Abstract: A selector switch is provided which always connects a receiving side electrode to one of a positive electrode input terminal and a negative electrode input terminal of a differential amplifier section. This selector switch is controlled so as to form a positive electrode region in which a plurality of electrode elements connected to the positive electrode input terminal are arranged, a negative electrode region in which a plurality of electrode elements connected to the negative electrode input terminal are arranged, and an insensitive region in which electrode elements are alternately connected to the positive electrode input terminal and the negative electrode input terminal.

Abstract: A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower.

Abstract: Embodiments of probe cards and methods for fabricating and using same are provided herein. In some embodiments, an apparatus for testing a device (DUT) may include a probe card configured for testing a DUT; a thermal management apparatus disposed on the probe card to heat and/or cool the probe card; a sensor disposed on the probe card and coupled to the thermal management apparatus to provide data to the thermal management apparatus corresponding to a temperature of a location of the probe card; a first connector disposed on the probe card and coupled to the thermal management apparatus for connecting to a first power source internal to a tester; and a second connector, different than the first connector, disposed on the probe card and coupled to the thermal management apparatus for connecting to a second power source external to the tester.

Abstract: A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

Abstract: An integrated circuit probing structure (40) is provided for evaluating functional circuitry (42), such as a slow slew-rate square wave signal from a low power circuit, where the probing structure includes two or more probe pads (48, 49) for testing the functional circuitry which are formed to be electrically separate from one another, and a probe test circuit (46) connected to the functional circuitry (42) for conveying a signal from the functional circuitry to a probe needle (47) only when the probe needle (47) electrically connects the two or more probe pads (48, 49).

Abstract: A dual tip test probe assembly for use in both cantilever and vertical probe applications includes first and second elongated test probes, each having a body portion and a tip portion with a tip configured to make contact with a device under test. An electrically-insulating material is disposed between but not in contact with the body portions of the first and second elongated test probes to electrically isolate the first and second elongated test probes. The first and second elongated test probes are held in alignment with respect to each other so that the tip of the first elongated test probe is adjacent to and not in contact with the tip of the second elongated test probe for making simultaneous contact with the device under test. The dual tip test probe assembly provides a low inductance and a small, stable footprint for testing small and/or non-flat test points.

Abstract: The invention relates to a module for a parallel tester for the testing of circuit boards, and to a parallel tester comprising such modules. The modules have circuit boards standing at right-angles to the plane of the basic grid of the parallel tester, and on which contact pins are arranged along one side edge. The contact pins lie with their peripheral surfaces on flat sides of the circuit boards and protrude a short distance beyond the side edge of the circuit board. They are connected electrically and physically to contact fields formed on the circuit board. This arrangement of the contact pins is cost-effective to produce, mechanically stable, and permits the production of modules with a high density of contact pins.

Abstract: A probe assembly has insertion holes formed in a base layer provided on a circuit board. Probe pins are inserted into the insertion holes and fixed by a conductive adhesive filled in the insertion holes. The probe pins can be arranged with small pitch without mechanically electrically interfering with neighboring pins using the insertion holes. Furthermore, the base layer is formed of a semiconductor material to prevent a problem caused by a difference in the coefficient of thermal expansion between the base layer and a wafer. Moreover, coplanarity and alignment accuracy of the probe pins can be improved using aligning mask layers or aligning mask in a process of manufacturing the probe assembly. In addition, probe assembly manufacturing time can be reduced by using a pin array frame into which a large number of probe pins are temporarily inserted.

Abstract: A wiring substrate that allows wiring at a fine pitch and has a coefficient of thermal expansion close to the coefficient of thermal expansion of silicone, and a probe card that includes the wiring substrate are provided. To this end, there are provided a wiring substrate that includes a ceramic substrate having a coefficient of thermal expansion of 3×10?6 to 5×10?6/° C. and one or more thin-film wiring sheets stacked on one surface of the ceramic substrate, and a probe head on which a plurality of conductive proves are arranged in accordance with wiring on the thin-film wiring sheet, which holds individual probes while preventing the probes from coming off and allowing both ends of each probe to be exposed, and which is stacked on the wiring substrate while one end of each probe is brought into contact with the thin-film wiring sheet.

Abstract: An automatic switching mechanism is controlled by a probe card independent from a tester without limitation of the number of control signals from the tester. A probe card and an inspection apparatus include probes to be brought into contact with electrodes of inspection targets and a power supply channel electrically connecting the probes to a tester. The automatic switching mechanism divides each of the power supply channels into a plurality of power supply wiring portions, which are respectively connected to the probes; and shuts off the power supply wiring responsive to electrical fluctuation such as overcurrent. An electrical fluctuation detection mechanism detects an electrical fluctuation due to a defective product among the inspection targets. A control mechanism, responsive to detection of an electrical fluctuation, shuts off the power supply wiring portion if the electrical fluctuation is caused by the automatic switching mechanism.

Abstract: According to one embodiment, a design support apparatus includes a first detector configured to detect a cable connected to the printed circuit board, a second detector configured to detect a conducting component from components of a housing, a third detector configured to detect an electromagnetic wave radiating component from electronic components mounted on the printed circuit board, a fourth detector configured to detect a path which propagates the electromagnetic waves, a first setting module configured to set, as sources, the electromagnetic wave radiating component and the path, a second setting module configured to set, for the sources, intensity attributes corresponding to an operation clock frequency of the electromagnetic wave radiating component, a calculator configured to calculate spaces of the sources, the spaces includes volumes corresponding to the intensity attributes, and a determining module configured to determine whether at least one of the cable passes at least one of the spaces.

Abstract: A polishing head is tested in a test station having a pedestal for supporting a test wafer and a controllable pedestal actuator to move a pedestal central wafer support surface and a test wafer toward the polishing head. In another aspect of the present description, the test wafer may be positioned using a positioner having a first plurality of test wafer engagement members positioned around the pedestal central wafer support surface. In another aspect, the wafer position may have a second plurality of test wafer engagement members positioned around an outer wafer support surface disposed around the pedestal central wafer support surface and adapted to support a test wafer. The second plurality of test wafer engagement members may be distributed about a second circumference of the ring member, the second circumference having a wider diameter than the first circumference. Additional embodiments and aspects are described and claimed.

Abstract: A testing system for testing a conversion efficiency of a power supply unit (PSU) includes a power meter, a plurality of switches, a multimeter, a microcontroller unit, and a data processing device. The power meter is utilized to measure an input power supplied to the power supply unit. The multimeter is utilized to measure an output power of PSU. The microcontroller unit is configured for automatically switching the plurality of switches for enabling the multimeter to measure the output power of power supply. The data processing device is utilized to read data measured from the power meter and the multimeter and calculate a conversion efficiency of the PSU.

Abstract: The present invention provides power saving methods by replacing termination resistors used to support SSTL DRAM interfaces with RC termination circuits; the RC termination circuits consumes significant less power relative to prior art termination resistors at low frequency and behave as a matching impedance at high frequency. Similar methods and structures are also applicable for PCIe, SATA, or MIPI differential interfaces.

Abstract: A circuit for calibrating impedance includes an enable signal generator, a code generator and a connection controller. The enable signal generator generates an enable signal in response to a chip selection signal. The code generator generates an impedance calibration code in response to the enable signal by using an external resistance coupled to an electrode. The connection controller controls connection between the code generator and the electrode in response to the enable signal.

Abstract: A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

Abstract: In one embodiment, an integrated circuit has an L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors and (L+2) levels of conductors for L at least equal to one. An (i?1)-th level of conductors comprising Ii?1 number of conductors selectively couple to the i-th level of conductors comprising Ii number of conductors which comprise of D[i] sets of conductors in the L-PSN, where i is selected from [1:L+1], through ((Ii?1×D[i])+Ii×Q) number of switches where each conductor of the Ii?1 number of conductors selectively couples to at least (D[i]+Q) number of conductors of the Ii number of conductors, at least one conductor from each of the D[i] sets of conductors, for Q at least equal to one and D[i] greater than one. The integrated circuit can be used in various electronic devices.

Abstract: An integrated circuit includes switching circuits for selectively connecting the bond pads to functional core logic and isolating the bond pads from second conductors, and the switch circuits for selectively connecting the bond pads to the second conductors to provide bi-directional connections between the bond pads on opposite sides of the substrate and isolating the bond pads from the functional core logic.

Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.

Abstract: An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits a differential signal to the differential signal receiver via a differential signal line including a first signal line and a second signal line. The first coupling capacitor is communicatively coupled to the first signal line and to the differential signal transmitter. The second coupling capacitor is communicatively coupled to the first signal line and to the differential signal receiver. The DC signal transmitter transmits a DC signal via the first signal line. The DC signal receiver receives the DC signal via the first signal line.

Abstract: The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision.

Abstract: A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract: A hysteretic comparator is proposed for comparing input signals and producing an output signal VOT with a hysteresis window Vhys. The hysteretic comparator includes a differential input stage with current output (DICO) having input transistors with transconductance Gmin, for converting the input signals, with an input stage transconductance Gmin, into intermediate signal currents. A steerable offset current generator, driven by a steering control signal, steers an offset current source IOS to alternative offset currents. A current-to-voltage summing converter (IVSC) sums up the intermediate signal currents and the offset currents and converts the result into VOT plus the steering control signal causing Vhys=IOS/Gmin. A feedback resistance RNF is connected to the input transistors to form a negative feedback loop. The RNF is sized such that GMin, hence Vhys, becomes essentially solely dependent upon the feedback conductance GNF=1/RNF independent of the Gmtnx, thus its process and environmental variation.

Abstract: An object is to provide a semiconductor device within which a signal which can be used as a reset signal or a mode signal is produced at an arbitrary timing to reduce the number of pads of the semiconductor device. To achieve the object, in a semiconductor device (10), first and second pads (101, 102) are respectively supplied with an external supply voltage and a ground potential. A signal generating circuit (12) outputs a signal at a predetermined logic level when the voltage supplied to the first pad (101) reaches a predetermined voltage higher than a voltage supplied to the first pad (101) during a normal operation of the semiconductor device (10).