Abstract: The present disclosure concerns a magnetic random access memory-based ternary content addressable memory cell, comprising a first and second magnetic tunnel junction respectively connected to a first and second straps extending on each side of the first and second magnetic tunnel junctions, respectively; a first and second selection transistors, respectively connected to one extremity of the first and second straps; a first and second current lines; and a conductive line electrically connecting in series the first and second magnetic tunnel junctions at their ends opposed to the ones connecting the first and second straps. The cell disclosed herein has smaller size and can be advantageously used in memory devices having a high cell density array.

Abstract: Memories, systems, and methods for repairing are provided. A memory with extra digit lines in end arrays with an open digit architecture can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group four adjacent digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. To repair memories including folded digit end arrays, a row in a core array that includes a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.

Abstract: The invention relates to a method for making a stack of memory circuits, wherein the method includes the step of testing the validity of at least two memory circuits. According to the invention, the method includes the phase of configuring each memory circuit, the configuration phase including the step of writing, within a configuration device of each memory circuit included in the stack, a piece of information on an identifier allocated to the memory circuit in the stack, and a piece of information on the results of the validity test of the memory circuit. The invention also relates to a method for addressing a memory circuit, to a stack of memory circuits, and to an electronic device including such a stack.

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8<y<2.0) are stacked together.

Abstract: A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises ?-tungsten.

Abstract: A semiconductor memory device includes a plurality of first wirings; a plurality of second wirings; a plurality of memory cells positioned at respective intersections of the first wirings and the second wirings, each of the memory cells having a variable resistance element and a selective element connected to the variable resistance element in series; a first selection portion selecting the first wiring; a second selection portion selecting the second wiring; and a power source portion applying predetermined selected-wiring-voltages to a selected first wiring being selected by the first selection portion and a selected second wiring being selected by the second selection portion, respectively, and applying predetermined unselected-wiring-voltages to unselected first wirings other than the selected first wiring and unselected second wirings other than the selected second wiring, respectively.

Abstract: A resistance change type memory includes first, second and third drive lines, a resistance change element having one end connected to the third drive line, a first diode having an anode connected to the first drive line and a cathode connected to other end of the first resistance change element, a second diode having an anode connected to other end of the first resistance change element and a cathode connected to the second drive line, and a driver/sinker which supplies a write current to the resistance change element. A write control circuit is arranged such that when first data is written, the write current is caused to flow in a direction from the first drive line to the third drive line, and when second data is written, the write current is caused to flow in a direction from the third drive line to the second drive line.

Abstract: A method of programming a variable resistance element to be operated with stability and at a high speed is provided. The method programs a nonvolatile variable resistance element (10) including a variable resistance layer (3), which changes between a high resistance state and a low resistance state depending on a polarity of an applied electric pulse, and a lower electrode (2) and an upper electrode (4). The method includes: writing steps (S11) and (S15) to cause the variable resistance layer (3) to change from the low resistance state to the high resistance state by applying a write voltage pulse; and an erasing step (S13) to cause the variable resistance layer (3) to change from the high resistance state to the low resistance state.

Abstract: Provided are a memory array excellent in noise characteristics and small in size and a semiconductor integrated circuit device having such a memory array. Memory cells each have two transistors and one storage element connected in series in this order between a corresponding one of bit lines and a constant voltage. The two transistors respectively have gate electrodes respectively connected to a corresponding one of first word lines and a corresponding one of second word lines. A memory array includes mats each having the memory cells disposed at all intersections between the bit lines and the first word lines, sense amplifiers each input with a corresponding pair of the bit lines in the same mat as a bit line pair, and first and second word drivers adapted to activate the first and second word lines, respectively.

Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

Abstract: A memory cell comprising a phase-change memory cell stacked in series with a resistive switch. The resistive switch has a material switchable between a high resistance state and a low resistance state by the application of a voltage. A plurality of memory cells are used to form a memory array.

Abstract: This invention describes a circuit and method to limit the stress caused by gate voltages required to write a one or zero in magnetic memory elements using the Giant magneto-resistive effect, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, which require high programming currents. The circuit and method selects one cell at a time for writing a one or a zero, different voltages to write a one or a zero, and a precharge circuit to limit the stress on non selected cells.

Abstract: A semiconductor device includes: a first magnetic random access memory including a first memory cell and a second magnetic random access memory including a second memory cell operating at higher speed than the first memory cell and is provided on the same chip together with the first magnetic random access memory. The first memory cell is a current-induced domain wall motion type MRAM and stores data based on a domain wall position of a magnetization free layer. A layer that a write current flows is different from a layer that a read current flows. The second memory cell is a current-induced magnetic field writing type MRAM and stores data based on a magnetic field induced by a write current.

Abstract: A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write voltage. A memory circuit stops application of the write voltage to a memory cell during the test period, and applies the write voltage to the memory cell after end of the test period. A high voltage detection unit compares the write voltage and a predetermined voltage to determine whether or not the write voltage is increased to the predetermined voltage. If the write voltage is less than the predetermined voltage at the end of the test period, the high voltage detection unit activates a disable signal. If the disable signal is activated, the charge pump circuit stops the boosting operation.

Abstract: A flash memory according to a present embodiment includes a memory cell array. The memory cell array includes a plurality of memory cells. Each of the memory cells can store n-bit data (n is an integer equal to or larger than 2). A plurality of word line are connected to gate terminals of the memory cells. A plurality of bit lines are connected to the memory cells. Sense amplifiers are configured to detect data stored in the memory cells via the bit lines. A data latch circuit of m×n bits can store n-bit data stored in each of m memory cells (m is an integer equal to or larger than 2) connected to one of the word lines. A multi-level interface can simultaneously transfer data of two or more bits between the data latch circuit and outside.

Abstract: A memory array comprises a semiconductor substrate, two-bit memory cells, word lines, a gate voltage source, bit lines and bit line control cells. The memory cells have a first and a second source/drain regions, each memory cell includes a dielectric trapping layer, and the dielectric trapping layer is disposed between a first oxide layer and a gate layer. The word lines are coupled to the gate layer. The gate voltage source is coupled to the word lines and configured to apply erase voltages between 14 and 20 volts to the word lines. The bit lines are in electrical communication with the first and the second source/drain regions. The bit line control cells are disposed at the beginning and end of each bit line, the bit line control cells are configured to control the electrical communication of each bit line with the first and the second source/drain regions.

Abstract: A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second potential, a drain, and a gate. A switch transistor has a gate coupled to a switch node, a source, and a drain. A stress transistor has a source and drain coupled between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit. Where one of the first or second potentials is a bit line, an isolation transistor is coupled between the other of the second potentials and one of the non-volatile transistors.

Abstract: Embodiments disclosed herein generally relate to switches that utilize micro-electromechanical systems (MEMS). By replacing transistors in many devices with switches such as MEMS switches, the devices may be used for logic applications. MEMS switches may be used in devices such as FPGAs, NAND devices, nvSRAM devices, AMS chips and general memory logic devices. The benefit of utilizing MEMS devices in place of transistors is that the transistors utilize more space on the chip. Additionally, the MEMS devices can be formed in the BEOL without having any negative impacts on the FEOL or necessitating the use of additional layers within the chip.

Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described.

Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array in which a plurality of nonvolatile memory cells are arrayed, and a program voltage generator that switches current supply amount based on the number of memory cells that are programmed at the same time, among the plurality of memory cells. The nonvolatile semiconductor memory device further includes a selection circuit that selects, among the plurality of memory cells, one or more memory cells that are programmed, to flow a current outputted by the program voltage generator.

Abstract: A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.

Abstract: A semiconductor memory device includes: a repair node; a fuse one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse; and a voltage drop unit coupled between the pull-up unit and the fuse and configured to lower a voltage level of the driving voltage.

Abstract: A semiconductor memory device includes a repair node; a fuse, one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse; a latch unit configured to latch a signal at the repair node; and a switch unit coupled between the latch unit and the repair node and configured to selectively transfer the signal from the repair node to the latch unit.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Abstract: A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.

Abstract: A circuit for generating a data strobe signal includes: a control signal generation unit configured to generate a strobe control signal defining an activation time period where a first data strobe signal and a second data strobe signal, which is an inverted signal of the first data strobe signal, are toggled; and a strobe signal output unit configured to output the first and second data strobe signals as a final strobe signal in the activation time period where the strobe control signal is activated.

Abstract: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (??) modulator to operate at a low frequency without generating false lock and glitch noise.

Abstract: A semiconductor memory device includes a source signal generation unit configured to generate a source pulse signal having a pulse width which is determined depending on an interval between an input of an active signal and an input of a column command signal, which is inputted after an active command, and a column decoding unit configured to generate a column select signal in response to an address and the source pulse signal.

Abstract: A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals to effectively charge a bit line pair to one half a power voltage using charge sharing between the capacitors.

Abstract: A memory device having a plurality of memory cells employs a method to detect a light attack on the memory device. The method utilizes at least one memory cell to detect a light attack when the memory cell is in an inactive state, and outputs a signal indicating whether a light attack is detected. In one case, the method includes turning off all of the memory cells of memory blocks of the memory device that are not currently being accessed for a read/write operation; sensing a leakage current of at least one of the memory cells of the memory blocks that are not currently being accessed for a read/write operation; and detecting a light attack on the memory device when a leakage current of the one of the memory cells of the memory blocks that are not currently being accessed for a read/write operation is greater than a threshold.

Abstract: A device includes a first circuit, a second circuit, and a control circuit controlling the first and the second circuits. The control circuit controls a plurality of output signals of the second circuit so as to have the same potential when the control circuit activates the first circuit and inactivates the second circuit.

Abstract: An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element.

Abstract: A latch type fuse circuit includes a non-volatile memory, a PMOS transistor, and an output circuit. The non-volatile memory cell stores a logic bit. A voltage level of a source of the PMOS transistor determines the latch type fuse operating in the data program status or the data read status. In the data program status, a gate of the PMOS transistor receives a first signal including an address and the logic bit for determining the logic bit written in the non-volatile memory cell. The output circuit includes two NMOS transistors and an inverter. In the data read status, the output circuit can latch the logic bit.

Abstract: Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.

Abstract: It is intended to provide a kneading extruder which makes it possible to prevent breakage due to resonance regardless of the rotating speed of kneading screws.

Abstract: Methods for forming composite materials containing fiber in an extruder are described. A first method includes introducing a polymeric material, an inorganic filler, and a fiber to an extruder. A fiber metering device is used to control the rate the fiber is introduced to the extruder based on the extrusion rate of the extruder. A further method is described that includes introducing a polymeric material and an inorganic filler to an extruder. Then, downstream of the polymeric material and inorganic filler, a fiber metering device introduces a constant weight percentage of fiber to the extruder based on the amount of polymeric material and inorganic filler introduced to the extruder. After the polymeric material, inorganic filler, and fiber are introduced to the extruder by either method, the components are mixed to produce a composite material.

Abstract: An active sonar detection system may include a transmitter, which may project into the transmissive medium signals of any frequency, amplitude or phase using one or more transducers. A transmit beamformer to provide transmission directionality may also be included. Generated transmit waveforms may have different temporal and frequency spectra that are adapted for different purposes.

Abstract: A technique includes representing actual measurements of a seismic wavefield as combinations of an upgoing component of the seismic wavefield and ghost operators. Interpolated and deghosted components of the seismic wavefield are jointly determined based at least in part on the actual measurements and the representation.

Abstract: Systems and methods for automatic steering of marine seismic sources are described. One system comprises a marine seismic spread comprising a towing vessel and a seismic source, the seismic source comprising one or more source arrays each having a center of source array, each source array having one or more source strings; a seismic source deployment sub-system on the towing vessel, the sub-system controlled by a controller including a software module, the software module and the deployment sub-system adapted to control an inline distance between one of the centers of source array and a target coordinate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, allowing a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: Method for transforming geologic data relating to a subsurface region between a geophysical depth domain and a geologic age domain. A set of topologically consistent surfaces (252a) is obtained that correspond to seismic data (252). The surfaces are enumerated in the depth domain. An age is assigned to each surface in the depth domain (255). The age corresponds to an estimated time of deposition of the respective surface. An age mapping volume is generated (256). An extent of the age domain is chosen. A depth mapping volume is generated (260). Both the age mapping volume and the depth mapping volume are used to transform geophysical, geologic, or engineering data or interpretations (258, 263) between the depth domain and the age domain (268) and vice versa (269). The geophysical, geologic, or engineering data or interpretations transformed by at least one of the age or depth mapping volume are outputted.

Abstract: A towed array is provided with hot-film sensors and anemometer circuitry to calculate the angle of inclination of the towed array in real time during deployment of the towed array in a sea water environment. The hot-film sensors are arranged in pairs along the length of the towed array to increase the sensitivity of the inclination angle determinations and are located flush with an exterior surface of the towed array to minimize interference with the operation of the towed array. The pairs of hot-film sensors determine the local shear stresses on the towed array, and these measurements are converted to inclination angles using an empirically derived look-up table.

Abstract: A rodent repeller having an audio signal generator configured to generate a chattering sound that mimics a distressed rodent. The audio signal generator produces a variable sound frequency to generate the chattering sound of distressed rodents.

Abstract: In response to a system reset signal inputted into a system reset port, a control circuit sets a general-purpose port to a high level first. Then, when a mode A is set in an integrated circuit for electronic timepiece, the control circuit sets the general-purpose output port to a low level after an elapse of a first time and when a mode B is set, it sets the general-purpose output port to a low level after an elapse of a second time. In this manner, a mode information signal having a pulse width corresponding to the mode is outputted from the general-purpose output port. It thus becomes possible to reduce the size without adding a special configuration for mode confirmation and to perform a confirmation in a short time.

Abstract: Timepiece (1) including a case (11) in which systems (3, 5, 7, 9) are mounted for operating the timepiece, controlled by control members (15, 21, 19) that project from the case, at least one of the control members (15, 19, 21) cooperating with an anti-shock device (33, 35) mounted in the case (11) and including a main component (91, 111), which is moveably mounted relative to the case (11), characterized in that the main component (91, 111) includes a permanent mechanical connection with the part (63, 41) of each system (25, 23) to which the at least one control member is attached, which enables the component to be reversibly uncoupled from the at least one control member (15, 19, 21) when a force greater than a predetermined threshold is exerted on the at least one control member and in that the mechanical connection is of the sliding type, and includes a jumper spring (95, 115) elastically mounted relative to a pin (96, 116).

Abstract: Provided is a near-field light generator capable of avoiding a noise to the generated near-field light. The generator comprises a waveguide and a plasmon antenna comprising a propagation surface or edge, for propagating surface plasmon, extending to a near-field light generating end. A portion of one side surface of the waveguide is opposed to a portion of the propagation surface or edge, so as for the waveguide light to be coupled with the plasmon antenna. And an end surface of the waveguide is inclined in such a way as to become away from the plasmon antenna toward the near-field light generating end side. The light that propagates through the waveguide and is not transformed into surface plasmon is refracted or totally reflected in the inclined end surface, does not come close to the generated near-field light, thus does not become a noise for the generated near-field light.

Abstract: A method and an apparatus for controlling data access rate of an optical disc player are disclosed. The method includes steps of (1) utilizing a micro-controller to decide whether an action of an instruction of a predetermined data processing is an extraction operation or a play operation; (2) driving the spindle motor and a pick-up head to retrieve data from an optical disc at a first data access rate by the micro-controller while the action of the instruction of the predetermined data processing is an extraction operation; and (3) driving the spindle speed and the pick-up head to retrieve data from the optical disc at a second data access rate which is less than the first data access rate by the micro-controller while the action of the instruction of the predetermined data processing is a play operation.