Abstract: A text input method is described for an electronic apparatus having a user interface with text input means and a display screen. Word completion functionality is provided for predicting word candidates for partial word inputs made by the user with the text input means. The method involves receiving a partial word input from the user and deriving a set of word completion candidates using the word completion functionality. Each of the word completion candidates in the set has a prefix and a suffix, wherein the prefix corresponds to the partial word input. The method also involves presenting the suffices for at least a sub set of the word completion candidates in a predetermined area on the display screen, wherein each of the presented suffices is made selectable for the user.

Abstract: Methods for generating an embedded target image to be stored in a non-volatile memory device of an embedded system as firmware thereof are disclosed. A graphical user interface (GUI) editor is generated to facilitate a user in providing settings information for multiple pins of a chip installed in the embedded system. Source code is generated in response to operating results of the user of the GUI editor. Linking an object file compiled from the generated source code generates the embedded target image.

Abstract: A real-time interactive document summarization system which allows the user to continuously control the amount of detail to be included in a document summary.

Abstract: Gesture feedback techniques are discussed that provide prompt feedback to a user concerning the recognition of one or more gestures. The feedback may be employed to confirm to a user that a gesture is being correctly recognized.

Abstract: A method in a computer-aided design system for generating a functional design model of a circuit that compensates for changes in resistance of a buried resistor by using a waveform that is representative of the thermal characteristics of the buried resistor.

Abstract: Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.

Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.

Abstract: Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.

Abstract: A system for the automated formation and control and execution of an electronic device design flow is disclosed which can enable more efficient electronic device design methodology with higher quality of results. Such a system as analysis methods, techniques, and tools, a knowledge database, a design database a controller and reasoner, are described.

Abstract: In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.

Abstract: The present invention presents a hybrid approach for manufacturability analysis that integrates both a rules-based approach and a models-based approach. For example, a rules-based analysis can be used to optimize the performance of a model-based analysis. The rules analysis can be used to identify specific areas of a layout that can then be analyzed in detail using models. This approach provides numerous advantages. It allows the models-based analysis tool to concentrate upon portions of the layout that requires greater attention and allocate fewer resources towards the areas less critical to the yield.

Abstract: An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Abstract: A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

Abstract: Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of the failing slack to each of a plurality of variables and comparing each sensitivity to a respective sensitivity threshold. If the sensitivity of at least one of the variables is greater than the respective sensitivity threshold, then the at least one timing test is considered to fail.

Abstract: In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for at-speed testing includes computing a process coverage metric for a plurality of paths in the integrated circuit chip and selecting at least one path that maximizes the process coverage metric.

Abstract: The present invention is a method that a redundant via is never added afterwards for a signal wiring or a clock wiring, but layout is performed using a multi-cut via from the beginning, which is used for laying out a semiconductor integrated circuit by a step (S32) of searching a wiring route that layout is possible using a multi-cut via regarding a net in a net list, a step (S33) of laying out a wiring corresponding to the net on the wiring route with using the multi-cut via, and a step (S70) of creating layout data of the semiconductor integrated circuit by repeating the steps S32 and S33.

Abstract: Printed circuit board (PCB) design support apparatus and method are provided. The target element disposed on a front surface of the printed circuit board is mirror-copied, and then the straight line distance between the mirror copied element and a back element disposed on the back surface of the PCB is calculated under the condition that the thickness of the PCB is zero. The resultant creepage distance between the target element and the back element is obtained by adding the thickness of the PCB to the straight line distance. The creepage distance can be obtained accurately and quickly by a calculation on a straight line distance.

Abstract: The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs. A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.

Abstract: An invention is provided for building configurable designs synthesizable to gates. The invention includes creating a configurable design using an HDL. The configurable design has a plurality of instantiated configurable constructs that can be optionally included in a design. Basically, the configurable design is an all-inclusive design having a large set of features, including varying interfaces, FIFO depths, and other features. Then, a derived design is generated by removing configurable constructs from the configurable design based on a specification, typically a customer specification received from a customer for a particular design. The specification indicates which configurable constructs are to be included in a derived design. Thereafter, the derived design is synthesizable in logic.

Abstract: A same sub-graph detection apparatus for data flow graph is disclosed. An embodiment of the present invention detects a sub-graph at a high speed, in which an area-size reduction effect is large.

Abstract: A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer readable medium and has the capability to initially synthesized an integrated circuit design to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.

Abstract: A method for amending layout patterns is disclosed. First, a layout pattern after an optical proximity correction is provided, which is called an amended pattern. Later, a positive sizing procedure and a negative sizing procedure are respectively performed on the amended pattern to respectively obtain a positive sizing pattern and a negative sizing pattern. Then, the positive sizing pattern and the negative sizing pattern are respectively verified to know whether they are useable. Afterwards, the useable positive sizing pattern and the negative sizing pattern are output for the manufacture of a reticle when they are verified to be useable.

Abstract: A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria. The method selects a number of datapath clusters to avoid too many input/output ports in data registers.

Abstract: Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.

Abstract: Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a method for noise analysis in an electronic circuit such as a digital CMOS circuit. The method includes identifying a cell and identifying the inputs of the cell. For each of the inputs of the cell, a corresponding first upstream circuit component is identified. The identified component is the first component upstream from the cell's input and is directly connected to the input. A noise analysis for the cell is performed based upon the configuration of the cell in combination with the identified upstream circuit components. The result of the analysis for the combination of the cell and the upstream circuit components can then be stored.

Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.

Abstract: The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used as an indicator of the power supply noise. Thereby, a real-time power supply noise monitoring can be carried out at any point of a power distribution network of an observed circuitry.

Abstract: Embodiments employ a method to define points on selected nets in a netlist for a focused ion beam (FIB) to create open circuits. A selected net is partitioned into a set of sub-segments, and after considering all metal layers at and above that of the selected net, a subset of the set of sub-segments is formed as those sub-segments having minimum distances from the considered metal layers greater than some threshold. All contiguous sub-segments in the subset of the set of sub-segments are grouped into groups. The midpoints of such groups, and any isolated sub-segments, are possible candidate for FIB points. For some embodiments, the midpoint of the longest (or one of the longest) groups of sub-segments is chosen as the FIB point for the selected net. Other embodiments are described and claimed.

Abstract: A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.

Abstract: A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The modification of layout is performed adaptively and iteratively to make an IC layout less susceptible to yield issues while maintaining design rule correctness and minimal circuit performance impact.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: A computer-implemented method and an apparatus for use in a computing programming environment are disclosed. The method includes: receiving a plurality of user inputs, each user input specifying an action in a workflow; identifying a data type incompatibility between two of the specified actions; and generating a script for executing the actions in the workflow responsive to the user inputs, the script including code for performing a action for converting one of the two identified, incompatible data types to the second. The apparatus, in a first aspect, includes a program storage medium encoded with instructions that, when executed by a computing device, performs the method. In a second aspect, the apparatus includes a computing apparatus programmed to perform the method.

Abstract: The embodiments of the invention described herein employ sophisticated techniques for managing distributed processes in a process automation system. Specifically, one embodiment of the invention implements a general purpose property mechanism in which arbitrary data is attached to any object in the system (e.g., projects, procedures, jobs, job steps, resources, etc), thereby providing a convenient way to configure the system without modifying the underlying program code. In addition, in one embodiment, a three-tier hierarchy of data object is employed: “projects,” “procedures,” and “steps” (or “projects,” “jobs” and “job steps” during runtime). A property may be attached to any object on any tier of the hierarchy to configure that object and (potentially) all of the objects which reference the property. The properties and property sheets may be attached both statically (before runtime) and dynamically (during runtime).

Abstract: The subject disclosure pertains to systems and methods for personalization of a recognizer. In general, recognizers can be used to classify input data. During personalization, a recognizer is provided with samples specific to a user, entity or format to improve performance for the specific user, entity or format. Biased regularization can be utilized during personalization to maintain recognizer performance for non-user specific input. In one aspect, regularization can be biased to the original parameters of the recognizer, such that the recognizer is not modified excessively during personalization.

Abstract: Disclosed herein are systems and methods providing for autonomous extraction of original natural language strings from source code and insertion of translated strings therein. Some of the examples described herein additionally utilize a database suitable for containing translations of user -viewable material and for accessing that material from developer project sandboxes. Individual developer projects may provide for the extraction of natural-language strings from source code to a shared translations database. Detailed information on various example embodiments of the inventions are provided in the Detailed Description below, and the inventions are defined by the appended claims.

Abstract: An activation program first activates a basic program and a first functional program, which realizes a specific function, among a plurality of functional programs, and then activates at least one second functional program among the functional programs after the first functional program is completely activated.

Abstract: An extensible markup language (XML) application framework (XAF) may be provided. XAF applications are data driven such that all operations with a computer system are data focused. In addition, the components used in the XAF application are instantiated and connected according to how data is displayed and what data type is used. Applications within XAF comprise a user interface (UI) connector, an action module, and a data connector. UI connectors receive UI events and connect the UI event to an action module. The action module generates a standard format action from the UI event and sends it to the data connector. The data connector translates the standard format action into a data-specific action that changes data in a data store. A data connector then sends a standard format data representation corresponding to the changed data back to the UI connector to provide the changed data to the UI.

Abstract: Methods, systems, and computer program products for file version control management are provided. Methods include receiving a loadset of at least one data file and activating the loadset. For each data file in the loadset, the data file is written to a target system and identified by a base name and a generation number. A symbolic link with an activation number is created in a version control file index (VCFX) to the data file written to the target system. An application view to the symbolic link is provided as the base name of the data file, and the application view to the symbolic link is limited based on an activation number of the application corresponding to the activation number of the symbolic link.

Abstract: When events are traced, the timing stream is used to associate events with instructions and indicate pipeline advances precluding the recording of stall cycles. Additional information is needed in the trace stream to identify an overlay whose execution of code is in a system where overlays or a memory management unit are used. In the case of PC trace, additional information is added when the memory system contents is changed. Information describing the configuration change is inserted into the export streams by placing this information in a message buffer. As long as a message word is available for output, it becomes the next export word as the output of message words is continuous.

Abstract: The present invention is directed to automatically analyzing software systems for identifying faults or bugs and/or detection of malicious code. In various embodiments, the present invention measures code coverage for high priority invocable program elements, uses a relaxed coverage estimation technique that, instead of guaranteeing which code units will be executed, guarantees that at least a certain number of code units will be executed, determines and solves constraints in code to identify infeasible paths containing one or more selected nodes, determines, for a composite data type, a range of values for each of at least two non-composite data fields, and/or translates, prior to code analysis complex code into simpler code having fewer operators.

Abstract: Described herein is a method that produces fully (mathematically) tractable development of policies for autonomic systems from requirements through to code generation. This method is illustrated through an example showing how user formulated policies can be translated into a formal mode which can then be converted to code. The requirements-based programming method described provides faster, higher quality development and maintenance of autonomic systems based on user formulation of policies. Further, the systems, methods and apparatus described herein provide a way of analyzing policies for autonomic systems and facilities the generation of provably correct implementations automatically, which in turn provides reduced development time, reduced testing requirements, guarantees of correctness of the implementation with respect to the policies specified at the outset, and provides a higher degree of confidence that the policies are both complete and reasonable.

Abstract: Comparison indices each for two components incorporated in a source program are used for easy and quantitative evaluation of functional redundancy in the program, effective and accurate extraction of redundant code segments from the program and also effective and accurate extraction of components to be modified simultaneously. A tree T is entered and an initial level of functional redundancy m(P) is set at 0 in a program P expressed by the tree T. The top node of the tree T is selected as a node N. A specific computation is performed for the top node selected as the node N with attribute information including the similarity and the number of children of the node N to obtain a level ?. The level ? is added to the functional redundancy m(P). The specific computation is performed for every node in the tree T, to obtain functional redundancy m(P) including the total of ? for all nodes.

Abstract: In a process for providing run time information for computer programs for controlling industrial robots (robot control programs), a first system time of a computer system executing the program is determined after the calling and before the execution of an individual command or a sequence of individual commands (subroutine). The individual command or the subroutine is subsequently executed, and a second system time of the computer system is determined after the execution. The determination of the system times is carried out on the basis of access times to certain areas of a program memory of the computer system, which areas characterize the individual commands or the subroutine. It is thus possible to carry out run time measurements on robot control programs in a simple and efficient manner, and the results of these run time measurements can be used to optimize such programs.

Abstract: A method, program, and information processing apparatus for detecting an inconsistency in an application program before the application program is implemented. The described is detecting a consistency or inconsistency in the design of screen transition of an application program, by generating a control flow graph for the application program, calculating from the control flow graph the solution of dataflow problem which occurs in the application program, detecting an inconsistency in the application program on the basis of the calculated solution, and displaying information concerning a detected inconsistency.

Abstract: A system and method in a data processing system for error checking and resolving failed input/output open calls. A configuration mechanism configures the options, such as the information stored in databases, details of how each error check is performed, and what actions should be taken when improper error checking occurs. Based on data stored in databases, such as an I/O calls database, a rules with syntax database, and an usage calls database, a code analyzer analyzes code in software programs for an error check of a failed input/output open call. A reporting mechanism reports data from the analyzed code to a report file, such as why software programs have proper and improper error-checking instances, sends errors from the analyzed code to an error file, and enables these files to be displayed on a display. Finally, the code analyzer enables resolving an improper error check for the failed input/output open call.

Abstract: A system and method for object reference monitoring. In one embodiment of the invention, a method includes running a computer application, monitoring a configuration point of the computer application during runtime, determining that a program object is accessed by the computer application at the configuration point, and storing data regarding the program object.

Abstract: An information processing apparatus executes a first module, a second module, and a third module for mediating a call from the first module to a function in the second module and obtaining the log of processing in the second module in response to the call. The apparatus obtains the log from the third module, extracts, from the obtained log, attribute information of functions and identifiers assigned to the functions, and determines, on the basis of attribute information of a first function and a second function among the extracted functions, identifiers assigned to the first function and the second function, whether processing in the second module has normally ended.

Abstract: There is disclosed a system for flattening hierarchically structured flows using a breadth-first approach. At each level of hierarchy of a hierarchically structured source flow, complex nodes are flattened by one level across the entire breadth of the flow. The results of this flattening are placed in a target flow, and any connections that existed in the source flow are re-established in the target flow in such a way that any data input into the target flow will be processed as if it had been input into the source flow. After a processing iteration, if there are still complex nodes remaining in the target flow, the target flow becomes the next source flow, and the process is repeated until the flow has been completely flattened.

Abstract: The disclosure is directed to a method of tracing processing of software instructions associated with a transaction. The method includes writing an access data stream addressed to a receiving application on a remote application server and writing a transaction identifier to the end of the access data stream. The receiving application is configured to read the access data stream and the transaction identifier when an instrumented version of the receiving application is implemented on the remote application server.

Abstract: Techniques for verifying a signature of an executable file are disclosed. In one particular exemplary embodiment, the techniques may be realized as a computer-implemented method for verifying a signature of a first executable file, comprising creating a first functional flow graph from the first executable file, storing the first functional flow graph, receiving, using a processor, a rule for the first executable file, and storing the rule. The techniques may also comprise receiving a second executable file, creating a second functional flow graph from the second executable file, determining whether a difference between the first functional flow graph and the second functional flow graph is less than a tolerance, and when it is determined that the difference between the first functional flow graph and the second functional flow graph is less than the tolerance, applying the rule to the second executable file.