Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract: A method for the synchronization of network neighbor reachability between a host networking stack and a peripheral device, which offloads one or more network protocols is provided. The network neighbor reachability represents the reachability of another computer on the network. This invention enables conventional neighbor reachability to be extended to seamlessly support some network connections to a specific remote host to be offloaded to a peripheral device, while other network connections are not.

Abstract: Optimizing collective operations using direct memory access controller on a parallel computer, in one aspect, may comprise establishing a byte counter associated with a direct memory access controller for each submessage in a message. The byte counter includes at least a base address of memory and a byte count associated with a submessage. A byte counter associated with a submessage is monitored to determine whether at least a block of data of the submessage has been received. The block of data has a predetermined size, for example, a number of bytes. The block is processed when the block has been fully received, for example, when the byte count indicates all bytes of the block have been received. The monitoring and processing may continue for all blocks in all submessages in the message.

Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.

Abstract: A method and an apparatus are provided for restricting input/output device peer-to-peer operations in a data processing system to improve reliability, availability, and serviceability. A peer-to-peer (P2P) control logic is provided to perform a lookup of P2P lookup table entries. Each P2P lookup table entry comprises bus, device and function number fields, optional control fields, and an accept/reject bit. Upon receiving a communication request from a requesting I/O device, P2P control logic implemented in either a logical bridge or an I/O device identifies the requester ID of the request and determines if a match exists in the P2P lookup table entries. If a match is found and the accept/reject bit is enabled, I/O operations can be received from the requester.

Abstract: A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction.

Abstract: A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices.

Abstract: The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.

Abstract: A method for managing under-runs and a device having under-run management capabilities. The method includes retrieving packets from multiple buffers, monitoring a state of a multiple buffers, determining whether an under-run associated with a transmission attempt of a certain information frame from a certain buffer occurs; if an under-run occurs, requesting a certain information frame transmitter to transmit predefined packets while ignoring packets that are retrieved from the certain buffer, until a last packet of the information frame is retrieved from the certain buffer; and notifying a processor that an under-run occurred after at least one predefined packet was transmitted; wherein each buffer out of the multiple buffers is adapted to store a fraction of a maximal sized information frame.

Abstract: A method for creating a complete data path between a user interface device (UID) and a second system device. The UID is coupled to a first system device via a UID switch prior to creating the UID, the first system device, and the second device being coupled to the UID switch. The method includes receiving from the UID at the first system device a connect request. The connect request represents a request to form the complete data path between the UID and the second system device via the UID switch. The method also includes formulating a switch command that is configured to cause the UID switch to create the complete data path when the switch command is executed by the UID switch. The method further includes transmitting the switch command from the first system device to the UID switch.

Abstract: A keyboard includes a keyboard control circuit, a card reader unit, at least one universal serial bus (USB) interface, a switch, and a BLUETOOTH unit. The USB interface is capable of coupling to the card reader unit. The BLUETOOTH unit is selectively connected to the keyboard control circuit or the card reader unit via the switch.

Abstract: Disclosed herein is an electronic device network including a plurality of electronic devices. The electronic devices may each have update agents capable of selectively decompressing compressed code and/or compressed data segments. The update agents may also be adapted to employ the decompressed code and data segments in conjunction with additional update information to update the firmware and/or software, compressed or otherwise, resident in the electronic devices. An update generator may be adapted to employ compression and decompression techniques to extract compressed code and data segments from a plurality of memory images stored in the electronic devices. The update generator may also be adapted to process the extracted information and generate update packages using the decompressed code and data segments and the additional update information. The update generator may also be adapted to selectively compress the update information in generated update packages usable for updating the electronic devices.

Abstract: A system for implementing handshaking configuration to enable coordinated data execution in a computer system. The system includes a core logic component coupled to a system memory and a graphics processor coupled to the core logic component via a graphics bus. The graphics processor and the core logic component implement a configuration communication to selectively configure coordinated data execution between the graphics processor and the core logic component via communication across the graphics bus.

Abstract: To minimize the restriction on the number of available PCI devices although the assignable size of I/O space is limited, an arithmetic unit is provided with a configuration information acquisition device for acquiring the configuration information about PCI devices, an available space determination device for determining available space for each PCI device, and a configuration information notification device for notifying an operating system of the configuration information.

Abstract: A method, system, and apparatus to hardware initiated throughput (HITM) measurement inside an OCP system using OCP side band signals are disclosed. In one embodiment, a system of an integrated circuit includes a signal line located in the integrated circuit to communicate an electrical signal, a receiver circuit located in the integrated circuit coupled to the signal line, a transmitter module located in the integrated circuit to communicate a data stream to the receiver circuit through the signal line, and a throughput monitor circuit coupled to the signal line to measure a throughput value during a communication period of the data stream from the transmitter module. The system may include a processor module located in the integrated circuit configured to interrupt an operation of the transmitter module and a receiver module if the throughput monitor circuit generates the interrupt signal.

Abstract: A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.

Abstract: A data processing apparatus and method for generating access requests is provided. A bus master is provided which can operate either in a secure domain or a non-secure domain of the data processing apparatus, according to a signal received from external to the bus master. The signal is generated to be fixed during normal operation of the bus master. Control logic is provided which, when the bus master device is operating in a secure domain, is operable to generate a domain specifying signal associated with an access request generated by the bus master core indicating either secure or non-secure access, in dependence on either a default memory map or securely defined memory region descriptors. Thus, the bus master operating in a secure domain can generate both secure and non-secure accesses, without itself being able to switch between secure and non-secure operation.

Abstract: In some embodiments, a system comprises a system memory module and an access card. The system memory module connects to a memory bus on a motherboard for a personal computer, while the access card connects to an expansion bus. The access card couples to the system memory module to provide power when the personal computer is unpowered. When the personal computer boots, the system memory module operates in a cloaked mode that hides the system memory module from a memory bus. The access card switches the system memory module from the cloaked mode to a normal mode in response to a command received via the expansion bus. For long-term power outages, the access card may copy data from the system memory module to a nonvolatile information storage device. Energy storage and nonvolatile information storage may be provided by a separate longevity unit that couples to the access card.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: An interruption control system includes two sense elements, a microprocessor, and a controller. The microprocessor includes two registers, two flip-latches, a multiplexer, and a microcontroller. Each sense element senses a device and sends a sense signal. The corresponding register receives and stores the sense signal. The microcontroller sets an identity signal for each of the registers and controls the each of the flip-latch units to record a data signal of the device. The multiplexer alternately outputs the ID signals and the corresponding data signals to the microcontroller to encode into a datagram. The microcontroller sends the datagram to the controller. The controller is interrupted for decoding the datagram.

Abstract: Embodiments are generally directed to an apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.

Abstract: Embodiments of an I/O module, processing platform, and method for extending a memory interface are generally described herein. In some embodiments, the I/O module may be configured to operate in a memory module socket, such as a DIMM socket, to provide increased I/O functionality in a host system. Some system management bus address lines and some unused system clock signal lines may be reconfigured as serial data lines for serial data communications between the I/O module and a PCIe switch of the host system.

Abstract: A detachable adapter is provided for being detachably connected to a data bus of a receptacle of a portable device to form a portable system. The adapter includes a conversion circuit and can inform the portable device that whether a power source is available and inform the portable device of connection status of the adapter through the data bus. The portable device can be connected to the power source through one of the receptacles of the adapter so that the portable device is powered or charged, and the portable device can be connected to at least one client device through the other receptacle of the adapter simultaneously.

Abstract: Apparatus, systems, and methods for coupling Fiber Channel (FC) storage devices and serial attached SCSI (SAS) storage device to a computer system through a single host bus adapter (HBA). The HBA includes a SAS storage controller four coupling to one or more SAS storage devices and an FC interface for coupling to one or more FC storage devices. The HBA also includes translation logic to translate information exchanged between the SAS storage controller and the FC storage device(s). Translation may include translation of addressing information between FC protocols and formats used by the SAS storage controller, may include use of a buffer to enable exchanges at different data rates, and may include use of a buffer to aggregate an inbound FC multiframe sequence into a single data buffer for use by the SAS storage controller.

Abstract: A USB printer sharing switch device with automatic switching capabilities is provided for multiple computers to share a USB printer. The sharing switch device transfers USB data between the computers and the printer without changing the data format. The automatic switching function is performed by hardware and firmware of the sharing switch device in cooperation with driver software on the computers. In one implementation, the sharing switch device includes multiple USB device controllers corresponding to the multiple computers, and employs multiple switches and a USB hub so that each computer is connected to its corresponding controller and the computer that is currently connected to the printer can communicate with its controller while printing. The current computer transmits a spooling finished command to its controller when spooling is finished. After receiving the spooling finished command, the sharing switch device automatically switches the printer to another computer.

Abstract: A data processor that erases data stored in a storage device includes an erase information storage unit that stores an erase information indicating a description of an erasing process having been performed, corresponding to an erase-specified area, after the erasing process for the erase-specified area, being an area specified to be subjected to the erasing process, is performed.

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract: A computer system, storage system, and device control method which keep and operate long-term data stored in a disk device using its characteristics for a long time and at low cost, in a storage system or in a storage system using an external storage connection method. A computer system comprises a host computer, a storage system, and a management server, which are connected to one another via a network. The storage system receives a request to detach a logical device, specifies a logical device to be processed with information included in the request and a physical device corresponding to the relevant logical device, releases a definition of a host path of the logical device, and stops the physical device.

Abstract: A dynamic cache policy manager for a mass memory may be used to decide whether a data request is to be routed to the cache or directly to the mass memory, based on estimated delays in processing the request. The choice may be based, at least partially, on the size of the respectively queues for the cache and mass memory. For write requests, the choice may be based on how many erase blocks are available in the cache.

Abstract: The present disclosure relates to systems and methods for RAID Restriping. One method includes selecting an initial RAID device for migration based on at least one score, creating an alternate RAID device, moving data from the initial RAID device to the alternate RAID device, and removing the initial RAID device. The method may be performed automatically by the system or manually. The method may be performed periodically, continuously, after every RAID device migration, upon addition of disk drives, and/or before removal of disk drives, etc. One system includes a RAID subsystem and a disk manager configured to automatically calculate a score for each RAID device, select a RAID device based on the relative scores of the RAID devices, create an alternate RAID device, move data from the selected RAID device to the alternate RAID device, and remove the selected RAID device.

Abstract: Methods and apparatus provide a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; provide a software implemented cache refill function also for managing the at least one address translation table cache; and simultaneously refill the at least one address translation table cache using the hardware implemented cache refill circuit and the software implemented cache refill function.

Abstract: A method for managing access to a data element involves storing a first copy of the data element in a cache location, obtaining a request to modify the data element, where the request to modify the data element is associated with a first execution thread, marking the cache location as dirty based on the request to modify the data element, modifying the cache location according to the request to modify the data element once the cache location is marked as dirty, obtaining a request to read the data element while the cache location is marked as dirty, where the request to read the data element is associated with a second execution thread, providing a second copy of the data element in response to the request to read the data element based on the cache location being marked as dirty, and marking the cache location as clean after modifying the cache location is complete.

Abstract: When a first channel processor from among a plurality of channel processors receives an I/O request from a host system, a second channel processor, which is to execute a part of the processing to respond to the I/O request, is selected from among the channel processors based on the LM directories of the respective channel processors. The selected second channel processor checks whether there is a cache hit. If there is a cache hit, it transfers the data from the cache memory to the buffer memory. The first channel processor then processes the I/O request using the data transferred to the buffer memory.

Abstract: Some embodiments include a storage device with a storage medium having a memory capacity. The storage device also includes virtual storage device firmware that is configured to directly respond to commands from a guest operating system in a virtual machine for accesses to a subset of the memory capacity of the storage medium when a virtual storage device is enabled.

Abstract: Embodiments of the present invention set forth systems and methods for compressing thread group data written to frame buffer memory to increase overall memory performance. A compression/decompression engine within the frame buffer memory interface includes logic configured to identify situations where the threads of a thread group are writing similar scalar values to memory. Upon recognizing such a situation, the engine is configured to compress the scalar data into a form that allows all of the scalar data to be written to or read from the frame buffer memory in fewer clock cycles than would be required to transmit the data in uncompressed form to or from memory. Consequently, the disclosed systems and methods are able to effectively increase memory performance when executing thread group STORE and LOAD operations.

Abstract: A method of memory management is disclosed. The invention increases bank diversity by splitting requests and is also integrated with re-ordering and priority arbitration mechanisms. Therefore, the probabilities of both bank conflicts and write-to-read turnaround conflicts are reduced significantly, so as to increase memory efficiency.

Abstract: A method, computer program product, and data processing system for preventing the occurrence of undetectable dangling pointers through memory reallocation are disclosed. Allocated memory regions that are no longer needed are deallocated but are not immediately freed for reallocation, being designated as “retained.” A memory retention metric is computed as a measure of an extent of the retained memory regions in the computer's memory space. Once the memory retention metric exceeds a pre-determined threshold, some or all of the retained memory regions are freed for reuse. In this manner, improper accesses to deallocated memory regions can be detected more easily, since reuse of those regions is delayed, while at the same time excessive resource usage and heap fragmentation is avoided by only retaining deallocated regions for a limited time (determined by the threshold and retention metric chosen).

Abstract: A chain of snapshots includes a more recent snapshot with a data block copied from a base volume, a less recent snapshot with a skip-pointer that leads to the data block in said more recent snapshot, and one or more intermediate snapshots between the more recent snapshot and the less recent snapshot in the chain of snapshots.

Abstract: A method, system and computer program product for data backup such that: for each block of a storage device to be backed up to an image, generating a hash function value corresponding to contents of that block; generating a map of links between blocks in the image and corresponding blocks the storage device; using the hash function values to identify blocks of the storage device with identical contents, such that links for the blocks in the storage device with identical contents point to a single block in the image; and modifying the link in the map when a block in the storage is moved (for example, due to defragmentation) but its contents is not altered, so that the link points to the same backed up block.

Abstract: In a computer system including a plurality of data storage apparatuses and a management computer, a given data storage apparatus, upon receipt of a control request for a local data storage apparatus from a management computer, accesses the hierarchical relation information between the storage areas in the local data storage apparatus and the storage areas of the other data storage apparatuses, and in the case where a storage area in the local data storage apparatus is set to correspond to a level lower than the other data storage apparatuses, transmits an approval request to the other data storage apparatuses. The given data storage apparatus, upon receipt of the approval from the other data storage apparatuses, executes the control request of the management computer.

Abstract: Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock signal may be less than the frequency of the second clock signal. The method further includes performing two or more data access operations using the second clock signal. One of the two or more data access operations may include a read operation and one of the two or more data access operations may include a write operation. The method also includes performing a command processing operation using the first clock signal.

Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.

Abstract: Disclosed is a system and method for implementing space management for large objects stored in the computing system. According to some approaches, storage of large objects are managed by dynamically creating contiguous chunks of storage space of varying lengths. The length of each chunk may vary depending upon object size being stored, fragmentation of the storage space, available free space, and/or expected length of the object.

Abstract: Method, apparatus and article of manufacture for determining memory requirements for a partition manager based on a given configuration. In one embodiment, a quantity of memory required for each of a plurality of components is determined, where each component is a collection of function-related code portions. Then, a total quantity of memory required for the partition manager based on the quantities of memory required for the plurality of components is determined.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Abstract: A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any source operand addresses or target operand addresses. The source operands and target operands for arithmetic/logic execution units are provided by independent load instruction operations and independent store instruction operations.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

Abstract: A multithreaded processor with dynamic thread based throttling, more specifically, based at least in part on the aggregated execution bandwidth requests of the threads, is disclosed herein. In various embodiments, the multithreaded processor may throttle by scaling clock frequency and/or voltage provided to the processor, based at least in part on the aggregated execution bandwidth requests of the threads. The aggregation and scaling may be performed when a bandwidth allocation request of an instruction execution thread is modified or when a computation intensive instruction execution thread is activated or re-activated. Other embodiments and/or features may also be described and claimed.