Abstract: A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.

Abstract: The present invention relates to a gigitaol phaselocked loop DPLL (300, 400) having a phase-to-digital P2D (60) with an enhanced bang-bang phase detector BBPD. Such a P2D (60) comprises a BBPD (62), an additional digital circuit (200) including a sign detector (210), a counter (220) and a mapping function (230), and a summer block (64). During the locking process, the BBPD (62) may-output a repeating value, namely a string of data bits of same polarity value either “+1” or “?1”. The polarity sign is detected by the sign detector (210), and the data string length is determined by the counter (220) that is reset to zero whenever the BBPD output changes sign. The mapping function (230) is configured for mapping the data string length in input to the phase correction level in output Its output is added to that of the BBPD (62) through the summer block (64), such that the phase correction level is increased to enhance the locking process whenever a data string is detected.

Abstract: A pump system that can dynamically increase its current capability includes: a pump circuit, for producing an output voltage; an oscillator, for driving the pump circuit to pump at a particular frequency according to a pump enable signal; a limiter, coupled to both the oscillator and the output voltage fed back from the pump circuit, for generating the pump enable signal to the oscillator according to the output voltage feedback signal; and an edge timer, coupled to both the oscillator and the pump enable signal, for driving the oscillator to operate at an increased frequency according to a threshold parameter of the pump enable signal.

Abstract: A phase locked loop (PLL) and a voltage controlled oscillator (VCO) thereof are provided. The VCO includes a ring oscillator circuit and a control circuit. The ring oscillator circuit is used for providing an output clock signal; and the control circuit is coupled to the ring oscillator circuit, and used for receiving an output voltage to respectively provide a first voltage-frequency gain and a second voltage-frequency gain so as to control a frequency of the output clock signal provided by the ring oscillator circuit, wherein the first voltage-frequency gain is larger than the second voltage-frequency gain.

Abstract: Read data that are output from core chips are accurately captured into an interface chip. Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that adjusts the period of time required from the reception of the read command to the outputting of the read data from the data output circuit. The interface chip includes a data input circuit that captures read data, and an input timing adjustment circuit that adjusts the timing for the data input circuit to allow the capturing of the read data after issuing the read command. In this manner, a sufficient latch margin for read data on the interface chip side can be secured.

Abstract: An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage.

Abstract: This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal.

Abstract: A voltage converting circuit for converting an input voltage into an output voltage is disclosed. The voltage converting circuit includes a modulation signal generator, a comparator and a logic unit. The modulation signal generator is configured for generating a pulse width modulation (PWM) signal responsive to a feedback signal corresponding to the output voltage and a load coupled thereto. The comparator is configured for comparing the feedback signal with a reference signal to output a comparing signal. The logic unit is configured for performing a logical conjunction of the PWM signal and the comparing signal to generate a control signal for adjusting an input current corresponding to the input voltage to regulate the output voltage. A method for converting an input voltage into an output voltage is also disclosed herein.

Abstract: A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.

Abstract: A semiconductor device comprising timer logic for generating a first modulated waveform signal, and delay logic, operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic; and provide a second delay in a falling edge of the first modulated waveform generated by the timer logic. The first delay and second delay of the first modulated waveform forms a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal.

Abstract: Provided is a modulation apparatus that outputs an output signal having a designated amplitude and a designated phase, comprising a first variable delay section that outputs a first delayed signal obtained by delaying a periodic signal by a set delay time; a second variable delay section that outputs a second delayed signal obtained by delaying the periodic signal by a set delay time; an adding section that adds together the first delayed signal and the second delayed signal, and outputs the result as the output signal; and a setting section that sets the delay times for the first variable delay section and the second variable delay section according to the designated amplitude and the designated phase.

Abstract: The invention relates to an interfacing device for transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention comprises signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source and delivers, when the transmitting circuit is in the activated state, currents to the signal terminals, each of the currents being mainly determined by one or more of the input signals of the transmitting circuit, one or more of the currents being not mainly determined by only one of the input signals of the transmitting circuit. The balancing circuit is such that, when the transmitting circuit is in the activated state, the current flowing out of the common terminal approximates the opposite of the sum of the currents flowing out of the signal terminals.

Abstract: Systems and methods for maintaining a drive signal to a resonant circuit at a resonant frequency are provided. A system for maintaining a drive signal to a resonant circuit at a resonant frequency can include: an oscillator configured to provide an output to a phase comparator and a drive circuit, the drive circuit configured to provide a drive signal to a resonant circuit; a phase detector configured to receive a filtered version of the drive signal from the resonant circuit and provide a phase-indicating signal to the phase comparator; and the phase comparator, wherein the phase comparator is configured to provide a signal based on the phase difference between the oscillator output and the phase-indicating signal, wherein the signal from the phase comparator is used to control the frequency of the oscillator such that the phase difference converges to a fixed value.

Abstract: A system for addressing electrical signals is disclosed, comprising an electromagnetically conductive control element, at least one control signal, at least one electromagnetic pulse modulator associated with the control element, and a threshold element positioned proximate to the control element, having an electromagnetic resistance that is conditional and changes as a result of fluctuations in the electromagnetic field of the control element.

Abstract: In an exemplary aspect of the invention, a clock signal amplifier circuit includes an amplifier circuit, a first switch part, and a second switch part. The amplifier circuit amplifies a clock signal. The first switch part controls ON/OFF of the amplifier circuit according to a select signal. The second switch part opens and closes complementarily to the first switch part according to the select signal. The amplifier circuit receives a test clock signal used in a test mode operation state through the second switch part. Further, the amplifier circuit outputs a signal generated by amplifying an input signal serving as the clock signal, or the test clock signal, according to the select signal.

Abstract: An analog switch (100) of the present invention is characterized by being constructed by MOS transistors and comprising a switch (102) connecting an input terminal VIN(104) and the substrate voltage of the NMOS transistor (101), a switch (103), being operated in a reverse phase to that of the switch (102), connecting the substrate voltage of the NMOS transistor(101) and the ground (VSS), and a voltage follower circuit (106) which, having a high input impedance and being connected between the input terminal (104) and the switch (102), suppresses the flow of the input current from the input terminal (104). According to the present invention, in an analog switch which is constituted by MOS transistors, it is possible to suppress that the input current flows into the substrate when the analog switch repeats the ON state and the OFF state.

Abstract: Systems and methods to achieve a charge pump for generating from single supply voltage energy efficient supply voltages that are symmetrical around ground voltage have been disclosed. The charge pump requires two flying capacitors only. The charge pump generates positive and negative supply voltages following a 1/N ratio of Vdd voltage, i.e. +?Vdd/N, and can be generalized to generate +/?Vdd/2N voltages. This is especially useful for supplying class-G amplifiers.

Abstract: Systems and methods to achieve a charge pump for generating from single supply voltage energy efficient supply voltages having a value of ±1/6 Vdd, ±1/5 Vdd, ±1/4 Vdd, ±1/3 Vdd, ±1/2 Vdd or ±1 Vdd that are symmetrical around ground voltage have been disclosed. The charge pump requires two flying capacitors only. The charge pump generates positive and negative supply voltages following a 1/N ratio of Vdd voltage, i.e. +?Vdd/N, and can be generalized to generate +/?Vdd/2N voltages. This is especially useful for supplying class-G amplifiers with a voltage or power, which is just enough e.g. for an audio signal to be correctly generated at the output of the amplifier.

Abstract: To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.

Abstract: This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair.

Abstract: A highly efficient class-G amplifier includes an amplifier circuit coupled between a positive power rail and a negative power rail to amplify an audio input signal of the class-G amplifier, and a boost inverting power converter to convert a supply voltage to a positive rail voltage and a negative rail voltage on the positive and negative power rails. The boost inverting power converter includes a boost inverting power stage coupled to the positive and negative power rails, and a controller to switch the boost inverting power stage between a boost mode and an inverting mode. An audio level detector detects the audio input signal for the controller to adjust the positive and negative rail voltages. The class-G amplifier has higher efficiency and requires lower cost because it does not need a charge pump.

Abstract: An output amplifier includes an amplifier circuit, a driving stage circuit, an output stage circuit, a first unity gain buffer, and a second unity gain buffer. The amplifier circuit provides an inverted signal and a non-inverted signal, in which the amplifier circuit amplifies an input pixel signal to generate the inverted signal and the non-inverted signal. The output stage circuit passes a supply voltage or a ground voltage to the pixel circuit according to the inverted signal and the non-inverted signal. The driving stage circuit passes the supply voltage or the ground voltage to the pixel circuit. The first unity gain buffer enhances and passes the inverted signal from the amplifier circuit to the driving stage circuit. The second unity gain buffer passes and enhances the non-inverted signal from the amplifier circuit to the driving stage circuit.

Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.

Abstract: An amplifier is provided with continuously-variable analog control that exhibits a highly linear gain control curve in db/volts, while preserving high dynamic range, low third order distortion, and low noise. This amplifier has a control mechanism that preserves a varied linear or log linear curve over a wide range and is inherently insensitive to process variations thereby allowing more accurate gain control and higher signal fidelity for amplifying high dynamic range signals.

Abstract: A signal filter circuit, an amplifier circuit, combinations thereof and methods for configuring and using the same are provided. Embodiments of the amplifier circuit may provide precise reproduction and amplification of input signals. The amplifier may be built entirely with discrete components or an integrated circuit may be configured to provide some or all of the modules included in the amplifier.

Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

Abstract: A broadband active circuit with a feedback structure includes: an active load unit providing a load varied according to a control voltage; an active circuit unit connected between the active load unit and a ground and outputting a signal corresponding to a pre-set bandwidth, among input signals; and a feedback circuit unit formed between an output terminal of the active circuit unit and the active load unit and providing a signal from the output terminal of the active circuit unit to the active load unit.

Abstract: An active bias control circuit for an amplifier includes a low dropout regulator for providing a regulated voltage to provide an input current to the amplifier, and a current sense circuit responsive to the low dropout regulator for sensing a scaled down replica of the input current to the amplifier. An amplifier control circuit adjusts a control voltage to the amplifier in response to the sensed, scaled down replica of the input current to regulate the input current to the amplifier. A method for power up sequencing an amplifier for an active bias control circuit for the amplifier is also disclosed.

Abstract: A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error.

Abstract: A device comprises an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit comprises a frequency control input and is configured to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input.

Abstract: An oscillator is provided. The oscillator comprises a flip-flop module, a first and a second setting module. The first setting module comprises: a first switch device to generates a first switch signal according to a first oscillating signal, an NMOS and an inverter. The NMOS comprises a drain to receive a first charging current and a gate to receive the first switch signal, wherein the drain is charged or discharged according to the first switch signal. The inverter is connected to the drain to generate a first setting signal. The second setting module comprises a second switch device to generate a second switch signal according to a second oscillating signal and a comparator to generate a second setting signal according to the second switch signal and a reference voltage. The flip-flop module generates the first and the second oscillating signal according to the first and the second setting signal.

Abstract: Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.

Abstract: An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Abstract: A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Abstract: An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels.

Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Abstract: A vibrating reed includes: a base; and a vibrating arm which is extended from one end portion of the base, the vibrating arm having an arm portion which is disposed on the base side, a weight portion which is disposed on a tip side of the arm portion and has a larger width than the arm portion, main surfaces which are respectively disposed on front and back sides of the vibrating arm, side surfaces each of which extends in a longitudinal direction of the vibrating arm to connect the main surfaces on the front and back sides and which are formed so as to face each other, a first groove portion which is a bottomed groove formed at least one of the main surfaces along the longitudinal direction of the vibrating arm, a first excitation electrode which is formed on groove side surfaces each connecting a bottom of the first groove portion with the one main surface, a second excitation electrode which is formed on the both side surfaces, and a projection-in-groove which is disposed on the tip side of a bisector bise

Abstract: A circuit includes a phase shifter configured to selectively shift a phase of a baseband phase signal in accordance with a zero crossing signal to output a selectively phase-shifted signal, a phase modulator configured to provide a phase modulated carrier signal in accordance with the selectively phase-shifted signal, and an inverter configured to selectively invert the phase modulated carrier signal in accordance with the zero crossing signal.

Abstract: A termination block for connecting a first signal device and a second signal device. The termination block includes a housing, first and second connectors, and an electrical circuit having passive elements that connect the first and second connectors and provide impedance matching.

Abstract: An acoustic resonator with improved quality factor and electro-mechanical coupling is disclosed. In one embodiment, the acoustic resonator includes an acoustic mirror formed on the top surface of a substrate or in the substrate, a first electrode having a end portion, formed on the acoustic mirror, a piezoelectric layer formed on the first electrode; and a second electrode formed on the piezoelectric layer, where at least one of the first electrode and the second electrode and the piezoelectric layer define an air gap in a region that overlaps the end portion of the first electrode. In one embodiment, a dielectric film is deposited on the surface of the end portion of the first electrode to form completely planarized surface before the piezoelectric layer deposition. In another embodiment, an air gap between the second electrode and the piezoelectric layer, so that the piezoelectric coupling in the end portion area of the first electrode is minimally contributed into the whole resonator.

Abstract: The filter includes at least one acoustic track formed on a piezoelectric substrate. At least one SAW input transducer and at least one SAW output transducer are arranged in each track. Each track has a RSPUDT structure and thus a distributed excitation. The excitation function includes sources arranged in a main lobe and a tail function including at least one tail lobe. A fine and precise approximation to the desired continuous excitation function is obtained by decreasing the excitation strength in the tail function by a factor of at least 2.

Abstract: MEMS resonators containing a first material and a second material to tailor the resonator's temperature coefficient of frequency (TCF). The first material has a different Young's modulus temperature coefficient than the second material. In one embodiment, the first material has a negative Young's modulus temperature coefficient and the second material has a positive Young's modulus temperature coefficient. In one such embodiment, the first material is a semiconductor and the second material is a dielectric. In a further embodiment, the quantity and location of the second material in the resonator is tailored to meet the resonator TCF specifications for a particular application. In an embodiment, the second material is isolated to a region of the resonator proximate to a point of maximum stress within the resonator. In a particular embodiment, the resonator includes a first material with a trench containing the second material.

Abstract: The electromagnetic filter according to the present invention includes a shield opening 102 provided in a shield conductor 101, a plurality of conductive strips 111 connected to the shield conductor 101 at both of two ends for dividing the shield conductor 101 into a plurality of divided openings 112, and a plurality of band-stop filters 113 located on each of the conductive strips 111 at a prescribed interval. By dividing the shield opening 102 into the plurality of divided openings 112, the amount of noise leaking via the shield opening 102 can be suppressed. Each of the band-stop filters 113 prevents a flow of an electric current of a prescribed frequency in each of the conductive strips 111, which would otherwise be caused by a magnetic field of the prescribed frequency passing the shield opening 102, and thus the wireless electric power transmission characteristic which uses coupling of magnetic fields of the prescribed frequency can be prevented from being deteriorated.

Abstract: A waveguide filter comprises a dielectric board on at least one of the two E-planes of a rectangular waveguide. The dielectric board comprises a conductive pattern formed on one surface thereof and having a slit extending in a signal propagation direction, and a ground pattern formed on the other surface.

Abstract: A multiple tap attenuator microchip device is disclosed. The device includes a substrate having two or more attenuator taps formed on a surface of the substrate. One or more ground contacts are also formed on the substrate surface and operatively connected to the attenuator taps. The attenuator taps each include a resistive network that is configured to provide a level of attenuation of an rf signal applied to the attenuator tap that is different from the attenuation level provided by the other attenuator tap(s).

Abstract: Resettable circuit interrupting devices, such as GFCI devices, that include reverse wiring protection, and optionally an independent trip portions and/or a reset lockout portion are provided. The reverse wiring protection operates at both the line and load sides of the device so that in the event line side wiring to the device is improperly connected to the load side, fault protection for the device remains. The trip portion operates independently of a circuit interrupting portion used to break the electrical continuity in one or more conductive paths in the device. The reset lockout portion prevents the reestablishing of electrical continuity in open conductive paths if the circuit interrupting portion is non-operational or if an open neutral condition exists.

Abstract: A first coil constitutes a first coil unit by placing an iron core plate between the first coil and an auxiliary yokes and engaging stopping parts provided in two holding members to an end surface in an axial direction of the auxiliary yoke. A second coil constitutes a second coil unit by forming magnetic path members by insertion to a resin member provided in a second bobbin unitarily, and fixing two terminals to the resin member. The first and the second coil units are united by connecting one terminal lead line of the first coil taken out from holding members to the first terminal, and connecting another terminal lead line to a surface of the magnetic path member.

Abstract: A photosensitive resin composition which is capable of reducing stress occurring due to thermal history, such as a heat treatment, a metal-base-containing circuit board production method which suppresses the warpage of a circuit board by employing the photosensitive resin composition and a metal-base-containing circuit board. The photosensitive resin composition comprises a polyamide acid, a 1,4-dihydropyridine derivative and an amide compound.

Abstract: The invention is a processing component used in electrophoresic conversion of coal fired flue gas carbon dioxide and nitrogen emissions into useful products in lieu of the more costly geosequestration of pollutant by-products produced in the electrical generating and transportation sectors of the economy. Carbon dioxide and facility stack nitrogen imbalance of coal-fired furnace emissions are chemically reacted with electric vehicle fuel cell spent electrolyte in the commercial production of plastic carbon polymers and nitrogen fertilizers.

Abstract: A transformer includes: a bobbin on which a coil is wound; a core coupled with the bobbin to provide a magnetic flux and installed on the PCB in a penetrating manner; and a base plate electrically connected to the coil and having a lead frame connected to the PCB, wherein the lead frame is formed such that the base plate is separated from an upper surface of the PCB.