Patents Issued in September 6, 2011
  • Patent number: 8012756
    Abstract: Methods and apparatus for direct detection of chemical reactions are provided. In a preferred embodiment, electric charge perturbations of the local environment during enzyme-catalyzed reactions are sensed by an electrode system with an immobilized target molecule. The target molecule is preferably DNA. The charge perturbation caused by the polymerase reaction can uniquely identify a DNA sequence. The polymerization process generates local perturbations of charge in the solution near the electrode surface and induces a charge in a polarazible gold electrode. This event is detected as a transient current by a voltage clamp amplifier. Detection of single nucleotides in a sequence can be determined by dispensing individual dNTPs to the electrode solution and detecting the charge perturbations. Alternatively, multiple bases can be determined at the same time using a mix of all dNTPs with subsequent analysis of the resulting signal.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: September 6, 2011
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Nader Pourmand, Miloslav Karhanek, Ronald W. Davis
  • Patent number: 8012757
    Abstract: Provided are a method for preparing a standard sample in which a uniform dispersion of a predetermined concentration of red phosphorus is guaranteed even in a very small amount, and an analytical method for quantitatively determining red phosphorus contained in a resin by pyrolysis-GC/MS, in which the standard sample is used. The method for producing a standard sample for quantitatively determining red phosphorus contained in a resin includes the steps of preparing a red-phosphorus-containing compound by weighing a predetermined amount of red phosphorus and uniformly mixing the red phosphorus in a resin; decreasing the number of particles having a maximum diameter of 5 ?m or more to 1/20 or less of the number of particles having a maximum diameter of 1 ?m or more and less than 5 ?m by pulverizing the red-phosphorus-containing compound; and obtaining a standard sample by weighing about 0.05 to 10 mg, preferably about 0.1 to 0.5 mg of the pulverized red-phosphorus-containing compound.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: September 6, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masuo Iida
  • Patent number: 8012758
    Abstract: An apparatus and method for monitoring microbiological activity in a process stream by measuring dissolved oxygen is disclosed. Bulk microbiological activity and surface associated biological activity are measured using this apparatus and method.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: September 6, 2011
    Assignee: Nalco Company
    Inventors: Michael V. Enzien, Laura E. Rice, Stephen B. Ashton
  • Patent number: 8012759
    Abstract: Provided are a method and an apparatus that enable rapid and automatic determination of the coagulant injection rate in a process of water treatment through coagulation and sedimentation. Using a coagulation analyzer comprising sample tanks 1A to 1D each for keeping a predetermined amount of raw water, a water supply pump 7, water supply/discharge valves 4, 6 for raw water and washing water, mixers 3A to 3D, a coagulant injection unit 21, and a detector 30 for determining the particle size and the particle number of flocs, the time within which the coagulant 20 injected into the sample tanks is dispersed by mixing and the particles begin to agglomerate (agglomeration start time) is determined, and based on the thus-determined agglomeration start time, the coagulant injection rate is determined, or the amount of the coagulant to be injected is controlled.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: September 6, 2011
    Assignee: Metawater Co., Ltd.
    Inventors: Dabide Yamaguchi, Yoshiharu Tanaka, Tokio Ohto, Takashi Nakayama
  • Patent number: 8012760
    Abstract: A system and associated methodology to directly measure the concentration of carbonate ions in seawater by ultraviolet absorbance spectroscopy. Metal ions are added to seawater and the absorbance spectra of the added ions are measured in the ultraviolet. The spectral absorbance (light attenuation) of ions such as divalent lead or copper in seawater is predominantly determined by the carbonate ion content of seawater. Through a knowledge of (1) the strength of association between carbonate and either divalent lead or divalent copper and (2) the spectral characteristics of these cations in seawater (e.g., Pb2+ complexed solely as PbCO3 and Pb2+ complexed solely in the form of chloride complexes), it is possible to directly determine seawater carbonate ion concentrations from absorbance measurements at a variety of wavelengths in the ultraviolet.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: September 6, 2011
    Assignee: University of South Florida
    Inventor: Robert H. Byrne
  • Patent number: 8012761
    Abstract: A method for rapidly detecting the presence of formaldehyde in a urine sample (e.g., urine or a urinary material associated therewith, such as headspace gas located associated with urine) is provided. The method includes contacting the urine sample with a substrate on which is disposed a colorant that is capable of undergoing a detectable color change in the presence of formaldehyde. Without intending to be limited by theory, it is believed that oxidation of the colorant by formaldehyde induces either a shift of the absorption maxima towards the red end of the spectrum (“bathochromic shift”) or towards the blue end of the spectrum (“hypsochromic shift”). The absorption shift provides a color difference that is detectable, either visually or through instrumentation, to indicate the presence of formaldehyde within the urine sample. For example, prior to contact with a urine sample, the colorant may be colorless or it may possess a certain color.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: September 6, 2011
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Rameshbabu Boga, Stephanie M. Martin, Molly K. Smith, Kevin Peter McGrath
  • Patent number: 8012762
    Abstract: Test device for detection and visual indication of a specific analyte in a liquid sample such as a body fluid. The device includes a biodegradable housing, a test strip and a lid. The device is configured for placement in concentrate or dilute test liquid that is for example contained in a vessel. One end of the test strip wicks the liquid being tested into the housing and across a control site and test site which provide visual indication that the device is working correctly and whether the analyte being tested is present in the test liquid. An antibody specific to the antigen being tested may be provided on the test strip. The test device for example detects specific antigens in dilute urine, such that the device may be placed in a toilet bowl after urination.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: September 6, 2011
    Inventor: Steve Lee
  • Patent number: 8012763
    Abstract: A stationary medium is employed both to separate chemicals from a sample solution and also to generate surface-enhanced Raman scattering, so that spectral analysis of the separated analyte chemical can be performed. Applied driving force causes the sample to flow into the stationary medium and to distribute therethrough, thereby causing rapid separation of the analyte chemical, and surface-enhanced Raman scattered radiation is quickly detected, at a plurality of locations along a flow path defined by the stationary medium, for ultimate analysis.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: September 6, 2011
    Assignee: Real-Time Analyzers, Inc.
    Inventors: Chetan S. Shende, Stuart Farquharson, Paul Maksymiuk
  • Patent number: 8012764
    Abstract: A mass spectrometer and method of mass spectrometry are disclosed wherein two separate samples are mass analysed and then the relative intensity, concentration or expression level of one or more components, molecules or analytes in a first sample is quantitated relative to the intensity, concentration or expression level of one or more components, molecules or analytes in a second sample. The relative quantitation is performed probabilistically without the need to resort to using internal calibrants.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: September 6, 2011
    Assignee: Micromass UK Limited
    Inventors: Richard Denny, Keith Richardson, John Skilling
  • Patent number: 8012765
    Abstract: A method and apparatus is provided for mixing a film of fluid, particularly a film of chemical, biochemical, or biological fluids undergoing a reaction. The apparatus comprises a means for nucleating a bubble using a discrete heat source, such as a resistor, and moving the bubble in the fluid by creating a temperature gradient, thereby mixing the fluid.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: September 6, 2011
    Assignee: Agilent Technologies, Inc.
    Inventor: Carol T. Schembri
  • Patent number: 8012766
    Abstract: Aspirating a liquid, includes: providing an aspirating probe comprising probe tip and piston pump, wherein the probe tip and piston pump are in fluid communication; measuring an initial gas pressure in the probe prior to liquid entering the liquid being aspirated; moving the tip into the liquid; moving the piston a distance corresponding to the volume of liquid being aspirated; measuring gas pressure in the volume of gas when the piston stops moving and the liquid pulled into the tip has equilibrated; determining piston volume created by movement of the piston; and determining volume of liquid aspirated by the following formula: Vliquid aspirated=Vpiston volume?((Pinitial?Pfinal)*Volume/unit pressure), wherein Pinitial is initial gas pressure before liquid enters the tip, Pfinal is the final pressure of volume of gas after the liquid has equilibrated, and Volume/unit pressure is the change of gas volume for each change of unit pressure.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: September 6, 2011
    Assignee: Ortho-Clinical Diagnostics, Inc.
    Inventor: Edward J. Graham
  • Patent number: 8012767
    Abstract: A method of loading a plurality of pipette tips on a plurality of mandrels of a pipetter is provided. A plurality of pipette tips are inserted in a plurality of receptacles of a tip loading assembly. The plurality of pipette tips are oriented with respect to each other by a plate. The tip loading assembly includes, but is not limited to, an insertion surface. The insertion surface includes the plurality of receptacles configured to accept the plurality of pipette tips. A receptacle from among the plurality of receptacles includes a receptacle wall and a beveled surface that extends from at least a portion of the insertion surface. A retention force is applied to the plate. The plurality of pipette tips are attached to a plurality of mandrels of a pipetter and are separated from the plate.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: September 6, 2011
    Assignee: Amgen Inc.
    Inventors: Brian Rasnow, Chuck Z. Li, Stephen Robert Wilson
  • Patent number: 8012768
    Abstract: The present invention provides a system and method for the simultaneous detection of multiple analytes in a sample. The detection system includes a housing that holds a reagent carousel rotatably coupled thereto. Further included in the housing is an incubator carousel rotatably coupled thereto. The housing also includes magnetic material that is associated with the incubation carousel for assisting in separation beads from reagent and wash solution. A robot, associated with the housing is configured to manipulate at least either the reagent carousel or the incubator carousel and transfer materials between these carousels. Reaction vessels hold samples and reaction vessels handlers move the reaction vessels. Sample analysis is determined by at least one laser based detector.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: September 6, 2011
    Assignee: Bio-Rad Laboratories, Inc.
    Inventors: Nasser Jafari, Chan Patrick, Lawrence J. Blecka, Chris Tsai
  • Patent number: 8012769
    Abstract: A non-radioisotopic method of detecting thyroid analytes comprising detecting T3, Free T3, T4, Free T4 and thyroglobulin autoantibody in a sample of a non-human species. Each one of these analytes in an assay profile includes non-radio isotopic measurement of T3, Free T3, T4, Free T4 and thyroglobulin autoantibody in the sample from the non-human species. A non-radioisotopic method detects T3AA and T4AA thyroid autoantibodies in a sample from a non-human species such as the canine species. Antibodies and autoantibodies are bound, and a precipitated or bound antigen-antigen or antibody-autoantibody complex is formed. The supernatant or surrounding fluid of the bound or precipitated antigen-antigen or antibody-autoantibody complex is then removed. The thyroid activity of the bound complex, precipitate, supernatant or surrounding fluid is measured. The thyroid analyte is at least one of T3, Free T3, T4 or Free T4.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: September 6, 2011
    Assignee: Hemopet
    Inventors: W. Jean Dodds, Ferdie S. Ongchangco
  • Patent number: 8012770
    Abstract: Devices and methods for the detection of antigens are disclosed. Devices and methods for detecting food-borne pathogens are disclosed.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: September 6, 2011
    Assignee: Invisible Sentinel, Inc.
    Inventors: Nicholas A. Siciliano, Martin Joseph Bouliane
  • Patent number: 8012771
    Abstract: A method for manufacturing magnetic field detection devices comprises the operations of manufacturing a magneto-resistive element comprising regions with metallic conduction and regions with semi-conductive conduction. The method comprises the following operations: forming metallic nano-particles to obtain regions with metallic conduction; providing a semiconductor substrate; and applying metallic nano-particles to the porous semiconductor substrate to obtain a disordered mesoscopic structure. A magnetic device comprises a spin valve, which comprises a plurality of layers arranged in a stack which in turn comprises at least one free magnetic layer able to be associated to a temporary magnetisation (MT), a spacer layer and a permanent magnetic layer associated to a permanent magnetisation (MP). The spacer element is obtained by means of a mesoscopic structure of nanoparticles in a metallic matrix produced in accordance with the inventive method for manufacturing magneto-resistive elements.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: September 6, 2011
    Assignee: C.R.F. Societa Consortile per Azioni
    Inventors: Daniele Pullini, Brunetto Martorana, Piero Perlo
  • Patent number: 8012772
    Abstract: A substrate treating apparatus, in which a voltage is applied to between a treatment electrode and a target substrate in such a state that the treatment electrode is opposed to the target substrate to thereby perform substrate treatment for removing undesired substances on the target substrate, has a reference electrode, a transfer unit which transfers at least one of the treatment electrode and the reference electrode to thereby provide the treatment electrode so that the treatment electrode is opposed to the reference electrode, and a check unit for applying a voltage to between the treatment electrode and the reference electrode in such a state that the treatment electrode is opposed to the reference electrode and thereby checking an adhesion level of undesired substances onto the treatment electrode surface.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: September 6, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Koide, Yasushi Iseki, Akira Ishii
  • Patent number: 8012773
    Abstract: A method for manufacturing a liquid discharge head includes providing a first layer containing a metal nitride to at least a portion on one surface of a silicon substrate corresponding to a supply port; providing a second layer on the first layer, the second layer including any one of aluminum, copper, and gold, or an alloy thereof; etching a portion of the silicon substrate corresponding to the supply port by reactive ion etching in a direction from the reverse surface towards the one surface so that the etched region reaches the first layer; and removing a portion of the first layer corresponding to the supply port and then removing a portion of the second layer corresponding to the supply port, thus forming the supply port.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: September 6, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuhiro Hayakawa
  • Patent number: 8012774
    Abstract: A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength-converting layer coupled to the n-type semiconductor.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: September 6, 2011
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: Chuong A. Tran, Trung T. Doan, Jui-Kang Yen, Yung-Wei Chen
  • Patent number: 8012775
    Abstract: The present invention provides a method of forming an optically triggered switch. Embodiments of the method include forming a silicon layer, forming one or more trenches in the silicon layer, and forming one or more silicon diodes in the silicon layer. Embodiments of the method also include forming a first thyristor in the silicon layer such that the first thyristor is physically and electrically isolated from the silicon diode(s) by the trench(es). The first thyristor is configured to turn on in response to electromagnetic radiation generated by the silicon diode(s).
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: September 6, 2011
    Assignee: Zarlink Semiconductor (US), Inc.
    Inventor: Thomas Joseph Krutsick
  • Patent number: 8012776
    Abstract: Methods of manufacturing an imaging device package are provided. In accordance with an embodiment a sensor die may be coupled to bond pads on a transparent substrate. Electrically conductive paths comprising bond wires are formed through the bond pads from the sensor die to an outer surface of the imaging device package.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: September 6, 2011
    Assignee: Micron Technology, Inc.
    Inventor: James Derderian
  • Patent number: 8012777
    Abstract: A packaging process of a light emitting diode (LED) is provided. First, an LED chip is bonded with a carrier to electrically connect to each other. After that, the carrier is heated to raise the temperature thereof. Next, an encapsulant is formed on the heated carrier by a dispensing process to encapsulate the LED chip, wherein the viscosity of the encapsulant before contacting the carrier is lower than that of the encapsulant after contacting the carrier. Thereafter, the encapsulant is cured.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: September 6, 2011
    Assignee: Lextar Electronics Corp.
    Inventors: Wen-Sung Chang, Cheng-Ta Kuo
  • Patent number: 8012778
    Abstract: The invention provides an LED package capable of effectively releasing heat emitted from an LED chip out of the package and a fabrication method thereof. For this purpose, at least one groove is formed on an underside surface of the substrate to package the LED chip and the groove is filled with carbon nanotube material. In the LED package, a substrate having at least one groove on the underside surface is prepared. A plurality of electrodes are formed on a top surface of the substrate. Also, at least the one LED chip is mounted over the substrate to have both terminals electrically connected to the upper electrodes. In addition, carbon nanotube filler is filled in the groove of the substrate.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: September 6, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Yong Suk Kim, Young Soo Oh, Hyoung Ho Kim, Taek Jung Lee, Seog Moon Choi
  • Patent number: 8012779
    Abstract: A vertical GaN-based LED comprises an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having an irregular-surface structure which includes a first irregular-surface structure having irregularities formed at even intervals and a second irregular-surface structure having irregularities formed at uneven intervals, the second irregular-surface structure being formed on the first irregular-surface structure; an active layer formed under the n-type GaN layer; a p-type GaN layer formed under the active layer; a p-electrode formed under the p-type GaN layer; and a structure support layer formed under the p-electrode.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: September 6, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Seok Beom Choi, Bang Won Oh, Jong Gun Woo, Doo Go Baik
  • Patent number: 8012780
    Abstract: There is provided a method of fabricating a semiconductor laser including a two-dimensional photonic crystal. The method comprises the steps of growing an InX1Ga1?X1N (0<X1<1) layer on a gallium nitride-based semiconductor region in a reactor; after taking out a substrate product including the InX1Ga1?X1N layer from the reactor, forming a plurality of openings for a two-dimensional diffraction grating of the two-dimensional photonic crystal in the InX1Ga1?X1N layer to form a patterned InX1Ga1?X1N layer; and growing an AlX2Ga1?X2N (0?X2?1) layer on a top surface of the patterned InX1Ga1?X1N layer to form voids associated with the openings.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: September 6, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Susumu Yoshimoto, Hideki Matsubara
  • Patent number: 8012781
    Abstract: A nanocrystal electroluminescence device comprising a polymer hole transport layer, a nanocrystal light-emitting layer and an organic electron transport layer wherein the nanocrystal light-emitting layer is independently and separately formed between the polymer hole transport layer and the organic electron transport layer. According to the nanocrystal electroluminescence device, since the hole transport layer, the nanocrystal light-emitting layer and the electron transport layer are completely separated from one another, the electroluminescence device provides a pure nanocrystal luminescence spectrum having limited luminescence from other organic layers and substantially no influence by operational conditions, such as voltage. Further, a method for fabricating the nanocrystal electroluminescence device.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Joo Jang, Shin Ae Jun, Sung Hun Lee, Tae Kyung Ahn, Seong Jae Choi
  • Patent number: 8012782
    Abstract: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. the semiconductor integrated circuit has substantially the same length as one side of a display screen (i.e., a matrix circuit) of the display device and is obtained by peeling it from another substrate and then forming it on the first substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate, includes a matrix circuit and a peripheral driver circuit and has at least a size corresponding to the matrix circuit and the peripheral driver circuit.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: September 6, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Yasuyuki Arai
  • Patent number: 8012783
    Abstract: The object of the present invention is to provide a semiconductor element containing an n-type gallium nitride based compound semiconductor and a novel electrode that makes an ohmic contact with the semiconductor. The semiconductor element of the present invention has an n-type Gallium nitride based compound semiconductor and an electrode that forms an ohmic contact with the semiconductor, wherein the electrode has a TiW alloy layer to be in contact with the semiconductor. According to a preferable embodiment, the above-mentioned electrode can also serve as a contact electrode. According to a preferable embodiment, the above-mentioned electrode is superior in the heat resistance. Moreover, a production method of the semiconductor element is also provided.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: September 6, 2011
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Tsuyoshi Takano, Takahide Joichi, Hiroaki Okagawa
  • Patent number: 8012784
    Abstract: Provided is a method for producing a group III nitride semiconductor light emitting device capable of producing a group III nitride semiconductor light emitting device with excellent light emitting properties with excellent productivity; a group III nitride semiconductor light emitting device; and a lamp. Provided is a method in which a buffer layer 12 composed of a group III nitride compound is laminated on a substrate 11 and then an n-type semiconductor layer 14 provided with an underlying layer 14a, a light emitting layer 15, and an p-type semiconductor layer 16 are sequentially laminated on the buffer layer 12, and is a method in which the buffer layer 12 is formed so as to have a composition of AlXGa1-XN (0?X<1) by activating, with plasma, and thereby reacting at least a metallic Ga source and a gas containing a group V element, and the underlying layer 14 is formed on the buffer layer 12.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: September 6, 2011
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Yasunori Yokoyama, Takehiko Okabe, Kenzo Hanawa
  • Patent number: 8012785
    Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: September 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Hua-Shu Wu, Li-Chun Peng, Tsung-Cheng Huang, Mingo Liu, Nick Y. M. Shen, Allen Timothy Chang
  • Patent number: 8012787
    Abstract: The manufacturing method includes: forming a P-type silicon substrate and a high-concentration N-type diffusion layer, in which an N-type impurity is diffused in a first concentration, on an entire surface at a light-incident surface side; forming an etching resistance film on the high-concentration N-type diffusion layer and forming fine pores at a predetermined position within a recess forming regions on the etching resistance film; forming recesses by etching the silicon substrate around a forming position of the fine pores, so as not to leave the high-concentration N-type diffusion layer within the recess forming region; forming the low-concentration N-type diffusion layer, in which an N-type impurity is diffused in a second concentration that is lower than the first concentration, on a surface on which the recesses are formed; and forming a grid electrode in an electrode forming region at a light-incident surface side of the silicon substrate.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: September 6, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masato Yonezawa, Kimikazu Hazumi, Akihiro Takami, Hiroaki Morikawa, Kunihiko Nishimura
  • Patent number: 8012788
    Abstract: A method is provided for producing a film of compound material. The method includes providing a substrate and depositing a film on the substrate. The deposited film has a first chemical composition that includes at least one first chemical element and at least one second chemical element. At least one residual chemical reaction is induced in the deposited film using a source containing at least one second chemical element to thereby increase the content of at least one second chemical element in the deposited film so that the deposited film has a second chemical composition. The content of at least one second element in the second chemical composition is larger than the content of at least one second element in the first chemical composition.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: September 6, 2011
    Assignee: Sunlight Photonics Inc.
    Inventors: Sergey Frolov, Allan James Bruce, Michael Cyrus
  • Patent number: 8012789
    Abstract: A nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Bong Ko, Yong-Ho Ha, Doo-Hwan Park, Bong-Jin Kuh, Hee-Ju Shin
  • Patent number: 8012790
    Abstract: A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Chung H. Lam
  • Patent number: 8012791
    Abstract: The invention relates to a method for producing electronic components comprising adjacent electrodes interspaced at distances ranging between 10 nanometers and several micrometers on a substrate of any type. According to the invention, the electrodes are structured by means of overlapping edges on the deposited layer or by undercutting the deposited layers. The electronic components are then produced either in the conventional manner or using a lithographic process from the underside of the transparent substrate and finally by means of a succession of known method steps for the production of electronic components.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: September 6, 2011
    Assignee: Cantrele Telecom Co., L.L.C.
    Inventors: Theodor Doll, Susanne Scheinert, Axel Scherer, Gernot Paasch
  • Patent number: 8012792
    Abstract: The invention provides a high quality composite phosphor powder which ensures diversity in emission spectrum, color reproduction index, color temperature and color, a light emitting device using the same and a method for manufacturing the composite phosphor powder. The composite phosphor powder comprises composite particles. Each of the composite particles includes at least two types of phosphor particles and a light transmitting binder. The phosphor particles have different emission spectrums. In addition, the light transmitting binder is formed between the phosphor particles and binds them together.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: September 6, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Chulsoo Yoon, Joon Ho Yoon, Chang Hoon Kwak, Yun Seup Chung
  • Patent number: 8012793
    Abstract: A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chung Hon Lam, Gerhard Ingmar Meijer, Alejandro Gabriel Schrott
  • Patent number: 8012794
    Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: September 6, 2011
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8012795
    Abstract: The method enables an assembly of chips, initially formed on a wafer, to be formed. Each chip comprises two parallel main faces joined by side faces. At least one of the side faces comprises at least one groove for housing a thread element. The wafer is first of all stuck onto a flexible film and the chips are then cut. The film is then deformed to space the chips apart from one another and to make the grooves accessible. A daisy chain is then formed joining the chips via at least one thread element, each chip being inserted in the daisy chain by inserting the thread in the groove of said chip and then removing the chip from the deformable film.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: September 6, 2011
    Assignee: Commissariat à l'Energie Atomique
    Inventors: Jean Brun, Benoît Lepine, Bruno Mourey, Dominique Vicard
  • Patent number: 8012796
    Abstract: Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, John M. Cotte, John U. Knickerbocker, Cornelia K. Tsang
  • Patent number: 8012797
    Abstract: In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: September 6, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Wen-Hsiung Chang, Chi-Chih Chu, Cheng-Yi Weng
  • Patent number: 8012798
    Abstract: A method for manufacturing a semiconductor device includes forming a first opening in a substrate to expose an interconnect structure, forming a seed film on the substrate, forming a first projecting electrode buried inside the first opening protruding outward from the substrate, forming a first metal film on the first projecting electrode, attaching a first supporting substrate to the substrate with a first adhesion layer, forming a second opening in the substrate to expose the interconnect structure, forming a second projecting electrode buried inside the second opening and protruding outward from the substrate, forming a second metal film on the second projecting electrode, attaching a second supporting substrate to the substrate with a second adhesion layer, removing the first supporting substrate, the first adhesion layer, and an exposed part of the seed film, removing the second supporting substrate and the second adhesion layer, and cutting the substrate into the plurality of chips.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: September 6, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Toru Miyazaki
  • Patent number: 8012799
    Abstract: A method for packaging a semiconductor die or assembling a semiconductor device that includes a heat spreader begins with attaching the heat spreader to a film and dispensing a mold compound in granular form onto the film such that the mold compound at least partially covers the film and the heat spreader. The film with the attached heat spreader is placed in a first mold section. A substrate having a semiconductor die attached and electrically coupled to it are placed in a second mold section and then the first and second mold sections are mated such that the die is covered by the heat spreader. The granular mold compound is then melted so that the mold compound covers the die and sides of the heat spreader. The first and second mold sections then are separated. The film, which adheres to the substrate, is removed to expose a top surface of the heat spreader, and thus a semiconductor device is formed.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: September 6, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ruzaini Ibrahim, Seng Kiong Teng
  • Patent number: 8012800
    Abstract: A method of fabricating a stacked type chip package structure is provided. The method includes following steps. First, a substrate, a first chip, and a second chip are provided. A number of bumps are disposed on a surface of the second chip. The second chip is then fixed on a surface of the first chip. Next, the second chip and the first chip on the substrate are turned upside down, and then the second chip is electrically connected to the substrate through the bumps by using a flip chip bonding technique. After that, the first chip is electrically connected to the substrate. Finally, a molding compound is formed on the substrate for encapsulating the first chip, the second chip, and the bumps.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: September 6, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chau-Chin Yang
  • Patent number: 8012801
    Abstract: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (II), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. The heating step is carried out at a temperature that is higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21).
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Patent number: 8012802
    Abstract: In a method of manufacturing a layered chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages. The layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces facing each other, and then the second surface of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: September 6, 2011
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8012803
    Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: September 6, 2011
    Assignee: Aprolase Development Co., LLC
    Inventors: Keith Gann, Douglas M. Albert
  • Patent number: 8012804
    Abstract: A method and system for providing energy assisted magnetic recording (EAMR) heads including EAMR transducers are described. The method and system include aligning a laser bar to the EAMR heads on a substrate. The laser bar includes lasers in locations corresponding to a portion of the EAMR transducers. The method and system also include bonding the laser bar to the substrate and removing a portion of the laser bar to separate the plurality of lasers. The substrate is separated into the EAMR heads.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 6, 2011
    Assignee: Western Digital (Fremont), LLC
    Inventors: Lei Wang, Shing Lee
  • Patent number: 8012805
    Abstract: In a manufacturing method for performing plasma etching on a second surface of a semiconductor wafer that has a first surface where an insulating film is placed in dividing regions and the second surface which is opposite from the first surface and on which a mask for defining the dividing regions is placed thereby exposing the insulating film from etching bottom portions by removing portions that correspond to the dividing regions and subsequently continuously performing the plasma etching in the state in which the exposed surfaces of the insulating film are charged with electric charge due to ions in the plasma thereby removing corner portions put in contact with the insulating film in the device-formation-regions, isotropic etching is performed on the semiconductor wafer at any timing.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Kiyoshi Arita, Akira Nakagawa
  • Patent number: 8012806
    Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: September 6, 2011
    Assignee: Icemos Technology Ltd.
    Inventors: Takeshi Ishiguro, Kenji Sugiura, Hugh J. Griffin