Abstract: According to an example embodiment, a chip includes a plurality of circuit blocks, a power switch unit configured to supply power to the plurality of circuit blocks, and a power switch controller configured to control the power switch unit in response to an external control signal. The external control signal selectively control supply of power to at least one circuit block of the plurality of circuit blocks.

Abstract: Provided is an apparatus for automatically detecting a failure position on a specified wiring line. The apparatus and a method for automatically detecting the failure position even on a long wiring line by applying a probe and an electron beam onto a sample and using an image of the current absorbed by the sample are provided. The apparatus obtains an absorbed current image, while laterally moving at right angle with the probe applied onto the sample, and based on the obtained absorbed current image, correction is performed by means of both an image shift and a stage. Countermeasures are taken, using a stage not having a sample rotating stage, against factors including a hardware factor of not moving at a correct angle, such as backlash, the wiring line is accurately and continuously displayed even when the apparatus moves to the ends of the long wiring line, and the failure position is detected, while the apparatus automatically reciprocates several times between the both ends of the wiring line.

Abstract: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

Abstract: According to one embodiment, a television apparatus includes a circuit board, a conductive portion, and an easily broken portion. The circuit board is mounted with an electronic component. The conductive portion is located on a surface or the inside of the circuit board. A breakage detection mechanism detects breakage of the conductive portion by conduction. The easily broken portion is provided to at least part of the conductive portion. The easily broken portion is broken easier than other portions of the conductive portion when a stress is applied to the circuit board.

Abstract: A monitoring device for an electric power system includes a detection unit and a display unit. The detection unit has a power module, a current detecting module and a transmission module. The power module includes positive and negative electrodes and is coupled to the current detecting module. The current detecting module includes a first switching unit and a second switching unit. The first and second switching units are coupled between the positive and negative electrodes to detect currents on detection points of the electric power system. The transmission module includes a micro-controller unit and a transmission device coupled to the micro-controller unit. The micro-controller unit includes a first end and a second end. The first end is coupled to the first switching unit and the second end is coupled to the second switching unit. The display unit is coupled to the transmission device for receiving signals from the detection unit.

Abstract: A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.

Abstract: A digital logic circuit and a manufacture method of the digital logic circuit thereof are provided. The digital logic circuit includes a voltage rail, a ground rail, and a plurality of logic circuit rails, wherein each of the logic circuit rails is electrically connected to the voltage rail and the ground rail. The logic circuit rail includes a logic unit and an auxiliary unit electrically connected to the voltage rail and the ground rail. The logic unit includes a logic voltage end electrically connected to the voltage rail and a logic ground end electrically connected to the ground rail. The auxiliary unit includes an auxiliary voltage end electrically connected to the voltage rail and an auxiliary ground end electrically connected to the ground rail. At least one of the width ratio between the auxiliary voltage end and the logic voltage end and the width ratio between the auxiliary ground end and the logic ground end is greater than 1.

Abstract: An impedance adjusting device includes a calibration unit configured to generate an impedance code for adjusting a termination impedance value, a plurality of termination units configured to be enabled by resistance selection information and terminate an interface node in response to the impedance code, a resistance providing unit coupled in parallel to the plurality of termination units and configured to provide a resistance in response to the resistance selection information, and a selection signal generation unit configured to generate the resistance selection information according to a target impedance value.

Abstract: An impedance code generation circuit includes a first code generation unit configured to compare a voltage of a calibration node with a reference voltage and generate a first impedance code, a code modification unit configured to generate a modified impedance code by performing an operation on the first impedance code according to a setting value, and a second code generation unit configured to generate a second impedance code based on the modified impedance code.

Abstract: A semiconductor integrated circuit includes an impedance control signal generation block configured to transmit first impedance control signals and second impedance control signals through same signal lines at predetermined time intervals, and input/output blocks configured to separately receive the first impedance control signals and the second impedance control signals at corresponding time intervals and perform a data input/output operation based on set impedance.

Abstract: A high speed flip-flop circuit and a configuration method thereof are provided. A small number of transistors may be used to configure a flip-flop circuit, so that the flip-flop circuit may be operated at a high-speed. Additionally, an area occupied by the flip-flop circuit may be reduced, and power consumption may be reduced. Accordingly, the flip-flop circuit may be integrated together with a microwave frequency integrated circuit using a Gallium Arsenide (GaAs) compound semiconductor process.

Abstract: A signal transmission system according to the present invention includes a first data conversion circuit (10) that converts first parallel data into first serial data (Ds) according to a first clock signal (CLKi); a clock multiplexing circuit (11) that outputs to a transmitting node a transmission signal (Dsm) obtained by multiplexing the first clock signal (CLKi) with the first serial data (Ds); a clock data recovery circuit (14) that extracts second serial data (Ds) corresponding to the first serial data and a second clock signal (CLKs) corresponding to the first clock signal (CLKi) from a reception signal (Drm) received through a receiving node; and a second data conversion circuit (15) that converts the second serial data (Ds) into second parallel data according to the second clock signal (CLKs). As a result, the chip area can be reduced.

Abstract: A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a selection circuit, where the input tier includes multiple combinatorial gate multiplexers. The method further includes selecting an output value at an output tier of the selection circuit, where the output tier includes at least one combinatorial gate multiplexer.

Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.

Abstract: Electronic equipment includes a battery, an interface portion to which a recording medium can be attached, a kind detection portion for detecting the kind of a recording medium, an access processing portion for executing a predetermined access process to a recording medium, a current consumption detection portion for detecting a value of current consumed by execution of the predetermined access process to the recording medium, an additional storage portion for storing a current consumption value corresponding to the detected kind into a storage portion, a power supply circuit for taking out and outputting electric power from the battery, and a power supply control portion for controlling the power supply circuit. The power supply control portion varies control on the power supply circuit in accordance with the current consumption value stored corresponding to the detected kind.

Abstract: A portable frequency synthesizer is provided with fine tuning over a broad bandwidth using a Fractional N type Delta Sum Phase Locked Loop circuit that enables elimination of boundary value spurs. In the system, frequencies where spurs occur are calculated to define a region of fractional N values that cannot be used with a first time base. To avoid the boundary spurs, a second time base reference is selected that can generate boundary spurs that do not overlap with the first time base. Circuitry is provided to select the appropriate time base and the fractional N values to generate desired output frequencies throughout the synthesizer range while avoiding the boundary spurs.

Abstract: A driver circuit, that provides slew rate control of its output voltage, including a current generator, an output transistor, and optionally, a capacitor. The current generator has an input port, an output port and reference port. The output port couples to the gate of the output transistor. The capacitor couples between the gate and drain of the output transistor. The current generator controls a current IS flowing through the output port based on an input voltage at the input port. The current generator limits the absolute value of the current IS to be less than or equal to a maximum determined by a reference current Iref provided at the reference port. Modifications may be made to the driver circuit to limit the output current (e.g., as a function of the output voltage) and to make the slew rate limit independent of the gate-drain capacitance of the output transistor.

Abstract: An electronic apparatus includes an electronic circuit including a driving transistor, an additional capacitive element and a first switch for controlling a connection between a circuit point and a control terminal and a driving circuit which controls the first switch to an off state and changes the potential of the control terminal such that the driving transistor transitions to an on state in a first period, controls the first switch to the on state so as to set the potential of the control terminal to an initial compensation value, in a second period, and controls the first switch to the on state and changes the driving potential from the first potential to the second potential such that the driving transistor transitions to the on state, in a third period.

Abstract: A ramp waveform generating apparatus generates a reference waveform by using an input signal and generates a driving control signal for turning on and off a switch having a first terminal connected to a load and a second terminal connected to a power supply by comparing the voltage of the reference waveform with the voltage of the load. While the switch is repetitively turned on and off in accordance with the driving control signal, a ramp waveform may be generated.

Abstract: A clock supply apparatus for supplying clock signals to a plurality of circuit blocks includes a supply unit configured to supply, to reset the plurality of circuit blocks, a clock signal rising at timing different from one circuit block to another to each of the plurality of circuit blocks.

Abstract: A power-up signal generation apparatus includes: a pre-power-up signal generation unit configured to generate a pre-power-up signal depending on a level of a power supply voltage; and a control unit configured to output the pre-power-up signal as a power-up signal in response to an active signal.

Abstract: A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.

Abstract: A slave device communicating with a master device includes a transmission unit configured to transmit a signal to the master device through a communication channel, a calibration unit configured to measure a flight time of a calibration signal which is transmitted to the master device and fed back through a calibration channel coupled to the master device, and a transmission delay unit configured to delay the signal transmitted from an internal circuit of the slave device to the transmission unit by a delay value determined according to the measurement result of the calibration unit.

Abstract: A phase-locked loop (PLL) with novel phase detection mechanism is provided, including a phase frequency detector (PFD), a controller, a digital-to-analog (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO), wherein PFD has a reference signal input and an input from output signal of the VCO/ICO and is connected to the controller, the controller is then further connected to D2A module, D2A module converts the control signal from the controller into an analog voltage to control the frequency and phase of VCO/ICO. It is worth noting that the PFD of the present invention has a novel phase detection mechanism so that the phase detection does not rely on edge alignment. In addition, the novel phase detection mechanism also allows flexible reference signal input, as opposed to the aforementioned fixed external source, such as, a crystal.

Abstract: In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first 1/2 frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter.

Abstract: In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.

Abstract: A semiconductor device includes a delay locked loop including a replica delay unit which is configured to delay a signal reflecting a delay amount of an output path of a signal, and a delay time compensator configured to compensate for a difference of a delay time between the replica delay unit and the output path by comparing an output signal of the replica delay unit and an output signal of the output path.

Abstract: A clock generation circuit includes a plurality of variable delay units configured to control a delay of an input clock signal under the control of delay control signals assigned thereto among a plurality of delay control signals, and output a plurality of delayed clock signals; a phase comparison unit configured to compare a phase of a reference clock signal which has a predetermined phase difference from the input clock signal and a phase of a delayed clock signal which is outputted from any one variable delay unit among the plurality of variable delay units; and a delay control unit configured to generate the plurality of delay control signals based on a comparison result from the phase comparison unit.

Abstract: Various exemplary embodiments of a phase correction circuit are disclosed. In one exemplary embodiment, the phase correction circuit may include a delay unit configured to delay a clock signal by a predetermined delay time and generate a delay clock signal, a delay line configured to delay a data strobe signal by a variable delay time in response to a delay control signal and generate a corrected data strobe signal, a phase detector configured to detect a phase difference between the delay clock signal and the corrected data strobe signal and generate a phase detection signal, and a shift register configured to generate the delay control signal in response to the phase detection signal.

Abstract: A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A phase correction circuit includes a skew detection unit configured to generate first skew detection signals and second skew detection signals by comparing multi-phase signals with one another, a phase control signal generation unit configured to generate a plurality of phase control signals by combining the first skew detection signals with the second skew detection signals, and a phase adjustment unit configured to delay the multi-phase signals by delay time corresponding to the plurality of the phase control signals.

Abstract: Provided is a stream signal transmission device that can eliminate transmission delay fluctuation with a fast change such as network jitter with high accuracy and synchronize a plurality of streams. The stream signal transmission device includes at least one reception unit that receives a stream signal to which a time code is attached from a network, at least one extraction unit that extracts the time code from the stream signal received by the reception unit, and at least one delay control unit that determines an output time by adding a predetermined fixed delay to a time indicated by the time code extracted by the extraction unit, and outputs the stream signal received by the reception unit after holding the stream signal up to the output time.

Abstract: A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

Abstract: A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock.

Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

Abstract: A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

Abstract: A phase shifter is provided. The phase shifter includes a first phase shifter that is continuously adjustable within a range of 0 degrees to 90 degrees, two 4-way switches each configured to selectively switch on one of a capacitance, an inductance, an open circuit, and a short circuit under control of a control voltage, and a bridge. A first input end and a first output end of said bridge are respectively connected to a first 4-way switch of the two 4-way switches. A second input end of said bridge is connected to an output end of said first phase shifter or a second output end of said bridge is connected to an input end of said first phase shifter.

Abstract: An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.

Abstract: An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.

Abstract: An integrated circuit 2 includes processing circuitry that includes a plurality of critical path circuits 4, 6, 8, 10. These critical path circuits include variable delay circuits 16 which add an additional delay in to the path delay through the critical paths so as to adjust the path delay to match a target path delay. Variable delay circuit 18 includes a tank capacitor 22 which is charged or discharged to generate a control voltage. This control voltage serves to control a power supply voltage fed to an inverter chain 28. Variation in the power supply voltage of the inverter chain 28 adjust the propagation speed of a processing signal through the inverter chain 28 and accordingly adjusts the additional delay imposed by the variable delay circuit.

Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).

Abstract: A transmitter includes a capacitor from one end of which a charge voltage is derived; a first constant current source to generate a charge current for the capacitor; a second constant current source to generate a discharge current for the capacitor; a charge/discharge controller to perform charge/discharge control of the capacitor based on a logic level of a transmission input signal and a comparison result between the charge voltage and a reference voltage; an output stage to generate the transmission output signal, wherein a slew rate of which is set in response to the charge voltage, and wherein an amplitude of the transmission output signal is set in response to an output side power source voltage; a reference voltage generator to fluctuate the reference voltage depend on the output side power source voltage; and a constant current controller to fluctuate a current value of the charge current and the discharge current depend on the reference voltage.

Abstract: A configurable calculating circuit includes a multiplexer, a mixer and an accumulator. The multiplexer is for receiving input signals including at least a first and a second input signals, and selectively outputting at least one of the input signals. The mixer is for mixing a selected input signal outputted from the multiplexer with a local oscillation signal to generate a mixed signal. The accumulator is for accumulating the mixed signal to generate an accumulated signal. When the configurable calculating circuit is operated under a first mode, the multiplexer selects the first input signal, and the accumulator performs a first accumulating operation upon the mixed signal; and when the configurable calculating circuit is operated under a second mode, the multiplexer selects the second input signal, and the accumulator performs a second accumulating operation, different from the first accumulating operation, upon the mixed signal.

Abstract: A switch circuit, particularly suitable for dimmer switches, detects zero-crossing or similar points in the supply and uses those to make predictions of future zero-crossing occurrences. The predicted occurrences may be used to time the operation of the switch itself to chop the supply which results in less variation in the power supplied (flicker if the switch circuit is operating a lamp) since the positions of the measured zero-crossings can be subject to noise but flicker is reduced if the switch is operated at times with respect to the true supply waveform. The predicted times may be obtained from a local oscillator having a period set by, for example, low pass filtering the period of the measured zero-crossings. The phase of the oscillator may be adjusted such that an error between the predicted and measured zero-crossings is reduced.

Abstract: Embodiments of the invention controlling power distribution in an ablation control apparatus or the like. In one embodiment, a power switching apparatus comprises a first switch assembly having an input end to receive a power input signal, the first switch assembly having a plurality of output channels; a second switch assembly coupled to the output channels of the first switch assembly; a plurality of power receiving members coupled to the second switch assembly; and a controller controlling the first switch assembly to selectively transmit the power input signal to the output channels one at a time in a cyclical manner according to a first switching rate.

Abstract: An N-level rectifier, wherein N is a number of voltage levels of the rectifier, includes an input; a plurality of switching devices connected in parallel, wherein the plurality of switching devices are connected to the input, wherein a number of the plurality of switching devices is equal to N?2; and a plurality of capacitors connected in series, wherein the plurality of capacitors are connected to the plurality of switching devices, wherein a number of the plurality of capacitors is equal to N?1, and wherein the plurality of capacitors are connected to an output of the N-level rectifier; wherein N is greater than three.

Abstract: The invention relates to a switching device for switching a current between a first connection (1) and a second connection (2), comprising a series connection of at least two JFETs (J1-J6), of which a lowest JFET (J1) is connected to the first connection (1), or the lowest JFET (J1) is connected in a cascade circuit to the first connection (1) via a control switch (M), and at least one further JFET (J2-J5), which is connected in series to the lowest JFET (J1), wherein the JFET (J6) farthest away from the lowest JFET (J1) is referred to as the uppermost JFET (J6) and is connected with the drain connection to the second connection (2), and wherein a stabilization circuit (D11-D53) is connected between the gate connections of the JFETs (J1-J6) and the first connection (1) in order to stabilize the gate voltages of the JFETs (J1-J6).

Abstract: Interfaces for coupling an electronic device to a power source control element and devices therefrom are provided. An interface includes a single node that is configured to receive a state signal and a serial communication signal from the electronic device. The interface also includes a switch circuit that is configured for providing a control signal for the power source control element based on the state signal, the switch signal capable of being influenced by the receipt of the state signal and the serial communication signal at the single node. The interface further includes a switch buffer circuit coupling the single node to the switch circuit, the switch buffer circuit comprising an impedance network configured to prevent the serial communication signal from activating the switch circuit.

Abstract: An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.