Patents Issued in December 1, 2011
  • Publication number: 20110291741
    Abstract: A semiconductor chip includes a semiconductor body having an upper surface. At least one power semiconductor component is integrated in the semiconductor chip together with other circuitry. Two or more vertically spaced metallization layers are arranged on the surface of the semiconductor body. The top metallization layer includes terminals establishing an electrical connection to load terminals of the power semiconductor component. A current measurement resistor is formed by a portion of the top metallization layer for sensing a load current of the power semiconductor component. A temperature measurement resistor is formed by a portion of at least one of the vertically spaced metallization layers, electrically isolated from current measurement resistor but thermally coupled thereto such that the current measurement resistor and the temperature measurement resistor have the same temperature.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Inventors: Alexander Mayer, Guenter Herzele, Andreas Tschmelitsch, Matthias Kogler
  • Publication number: 20110291742
    Abstract: An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.
    Type: Application
    Filed: July 28, 2010
    Publication date: December 1, 2011
    Inventors: Chua-Chin WANG, Ron-Chi Kuo, Jen-Wei Liu, Ming-Dou Ker
  • Publication number: 20110291743
    Abstract: A signal sample trigger apparatus (206) comprises an input (302, 304), a processing resource (300, 500) coupled to the input (302, 304), and an output (306) coupled to the processing resource (300, 500). The processing resource (300, 500) is arranged to generate, when in use, a trigger signal (400, 600) in response to location increment information. The location increment information (402, 404, 602, 604) is received via the input (302, 304), and the trigger signal (400, 600) is provided via the output for triggering execution of a sample of an analogue signal.
    Type: Application
    Filed: January 25, 2010
    Publication date: December 1, 2011
    Applicant: Lein Applied Diagnostics Limited
    Inventor: Robin Taylor
  • Publication number: 20110291744
    Abstract: Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.
    Type: Application
    Filed: November 18, 2010
    Publication date: December 1, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Hong Gyeom KIM
  • Publication number: 20110291745
    Abstract: A low noise current source includes first and second voltage input terminals. The current source further includes an amplifying device having an input terminal and an output terminal, where the output terminal is coupled to the second voltage input terminal via a load. The current source also includes a bias circuit coupled between the first voltage input terminal, the second voltage input terminal, and the input terminal. The current source additionally includes a first bypass circuit coupled between the first voltage input terminal and the input terminal, where the first bypass circuit configured to provide a substantially high electrical resistance and substantially no electrical impedance between the first voltage input terminal and the input terminal.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Inventor: David Albean
  • Publication number: 20110291746
    Abstract: An integrated circuit comprising a plurality of functional blocks, each functional block being operative to cause one or more power consuming events, each power consuming event being associated with a respective weight. The integrated circuit also comprises at least one accumulation block for monitoring the functional blocks over a time window and generating a weighted count of the number of occurrences of each power consuming event within the time window; and a power calculation module for calculating a runtime power consumption estimate over the time window using the weighted count. The weighted count may comprise a sum of products of each one of the power consuming events by its respective weight. Calculating the runtime power consumption estimate may comprise averaging the weighted count over the time window to generate a dynamic power estimate, calculating a leakage power estimate over the time window, and summing the dynamic power estimate with the leakage power estimate.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ali Ibrahim, Ashwini Dwarakanath, Daniel Parrenas Shimizu
  • Publication number: 20110291747
    Abstract: A voltage generation circuit includes: a first and second rectification circuits; and one or more amplification units connected between the first and second rectification circuits and configured to amplify an output of the first rectification circuit and provide the amplified output to the second rectification circuit. The second rectification circuit generates a reference voltage.
    Type: Application
    Filed: December 16, 2010
    Publication date: December 1, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jae Boum PARK
  • Publication number: 20110291748
    Abstract: Power management systems and methods that facilitate efficient and effective power conservation are presented. In one embodiment a power management method comprises: performing an initiation metric determination process, and adjusting operations of a logic component based on said threshold value. In one exemplary implementation, the initiation metric determination process includes monitoring activity of a logic component, and establishing a power conservation initiation threshold value. The initiation metric determination process can include performing a system architecture characteristic analysis in which a system architecture power-consumption break-even time (BE) is determined for the system. The initiation metric determination process can also include performing a system utilization analysis process is performed in which idle period durations detected during said monitoring are sorted into a variety of different length intervals and analyzed accordingly.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: NVIDIA CORPORATION
    Inventors: Sau Yan Keith Li, Thomas Edward Dewey, Saket Arun Jamkar, Amit Parikh
  • Publication number: 20110291749
    Abstract: Apparatus and methods are disclosed, such as those involving protection of a semiconductor junction of a semiconductor device. One such apparatus includes a bipolar transistor including an emitter, a base, and a collector; a first junction protection device including a first end electrically coupled to the emitter of the bipolar transistor, and a second end electrically coupled to a node; and a second junction protection device including a first end electrically coupled to a voltage reference, and a second electrically coupled to the emitter of the bipolar transistor. Each of the first and second junction protection devices may have a substantially higher leakage current than the leakage current of the base-emitter junction of the bipolar transistor when reverse biased.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: ANALOG DEVICES INC.
    Inventor: Kenneth Lawas
  • Publication number: 20110291750
    Abstract: A charge domain filter (CDF) and a bandwidth compensation circuit of the CDF are provided. The CDF includes an amplifier, a plurality of switch-capacitor networks (SCNs), a connector, a current adder (CA) and a bandwidth compensation circuit. A first input terminal of the amplifier receives an input signal, and an output terminal thereof is connected to input terminals of the SCNs. The connector is connected between the output terminal of the SCNs and the CA for configuring coupling status of the output terminals of the SCNs and input terminals of the CA. The bandwidth compensation circuit senses a portion of or all of the output terminals of the SCNs and the CA, and outputs the sensing result to a second input terminal of the amplifier.
    Type: Application
    Filed: July 8, 2010
    Publication date: December 1, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Ming-Feng Huang
  • Publication number: 20110291751
    Abstract: A The present invention relates to a phase matching band-pass filter using exponential function approximation, comprising an inductor including a parasitic resistor, a first device wherein a first amplifier is connected in a feedback mode, a capacitor including a parasitic resistor, a plurality of filter devices including a second device that is connected with a second amplifier in a feedback mode, and a coupling capacitor that connects the plurality of filter devices; the impedance of the first device has an increasing exponential function relation with a frequency, impedance of the second device has a decreasing exponential function relation with the frequency, and the first device is connected with the second device in parallel. According to the phase matching band-pass filter using exponential function approximation of this invention, conventional inductors and capacitors can be used 0 without modification or use of negative resistance, resulting in a high-performance phase matching band-pass filter.
    Type: Application
    Filed: January 22, 2010
    Publication date: December 1, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Gue Park, Byung Tae Yoon, Jae Sub Lee, Mi Hyun Son, Jong Wook Zeong
  • Publication number: 20110291752
    Abstract: A circuit includes a high impedance direct current (DC) gate having a DC impedance higher than a maximum impedance DC above which dendrite growth occurs in the circuit, and a low impedance radio frequency (RF) gate having an RF impedance lower than a minimum impedance RF needed to ensure RF stability for the circuit for an application.
    Type: Application
    Filed: October 15, 2010
    Publication date: December 1, 2011
    Applicant: STMicroelectronics, Inc.
    Inventor: John C. Pritiskutch
  • Publication number: 20110291753
    Abstract: Various apparatuses and methods for amplifying an FM signal in a segmented linear power amplifier are disclosed herein. For example, some embodiments provide an apparatus including a signal input, a signal output, and an output driver connected between the signal input and the signal output. The output driver includes a number of driver segments connected in parallel, each having an input connected to the signal input and each having an output. The output driver also includes a number of series capacitors, each associated with one of the driver segments. The series capacitors are each connected between the output of its associated driver segment and the signal output. The output driver also includes a number of shunt capacitors, each associated with one of the driver segments having an associated series capacitor. The shunt capacitors are each connected between the output of their associated driver segment and a ground.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Inventors: Brian P. Ginsburg, Mehmet Ozgun
  • Publication number: 20110291754
    Abstract: Various apparatuses and methods for varying segment activation in a segmented power amplifier are disclosed herein. For example, some embodiments provide a power amplifier including an input, an output, a plurality of amplifier segments and a controller. The amplifier segments are connected in parallel between the input and the output and are adapted to be activated and inactivated. The power level at the output may be controlled by changing a number of the amplifier segments that are activated concurrently. The controller is connected to the amplifier segments and is adapted to vary which of the amplifier segments are activated to arrive at a selected number of activated amplifier segments.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Inventors: Vijay Kumar Reddy, Srikanth Krishnan, Brian P. Ginsburg, Srinath Mathur Ramaswamy, Chih-Ming Hung
  • Publication number: 20110291755
    Abstract: When switching the mode of a power amplifier between compressed mode and uncompressed mode, accurate transmission power control is realized. A transmission power control method includes setting a power setting value of mode to switch to, such that an inter-mode output power error is canceled (equal to step ST21), calculating an intra-mode output power error from the power setting value of the mode to switch to (equal to step ST23), calculating a gain linearity value based on the power setting value of the mode to switch to and an output power error of the intra-mode (equal to step ST24), and resetting the power setting value of the mode to switch to based on the gain linearity value (equal to steps ST25 and 26).
    Type: Application
    Filed: November 18, 2010
    Publication date: December 1, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Tomoya Urushihara, Kaoru Ishida, Akihiko Matsuoka
  • Publication number: 20110291756
    Abstract: Aspects of a method and system for polar modulation with discontinuous phase for RF transmitters with integrated amplitude shaping may include amplifying a signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain, an amplitude offset gain and a pulse-shaping gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the amplitude offset gain and the pulse-shaping gain, wherein the one or more of the plurality of amplifiers used to set said amplitude offset gain and said pulse-shaping gain are distinct from the one or more of said plurality of amplifiers used to set the coarse amplitude gain.
    Type: Application
    Filed: October 19, 2007
    Publication date: December 1, 2011
    Inventor: Ahmadreza Rofougaran
  • Publication number: 20110291757
    Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.
    Type: Application
    Filed: August 11, 2011
    Publication date: December 1, 2011
    Applicant: BROADCOM CORPRATION
    Inventors: Afshin Momtaz, Namik Kocaman, Bharath Raghavan
  • Publication number: 20110291758
    Abstract: In one embodiment of the invention, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential amplifier includes an adjustable current control circuit coupled to limit a tail current passing through the differential amplifier.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: XILINX, INC.
    Inventor: Cheng-Hsiang Hsieh
  • Publication number: 20110291759
    Abstract: A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals.
    Type: Application
    Filed: July 9, 2010
    Publication date: December 1, 2011
    Inventors: Taek-Sang Song, Dae-Han Kwon, Jun-Woo Lee
  • Publication number: 20110291760
    Abstract: A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages.
    Type: Application
    Filed: April 27, 2011
    Publication date: December 1, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuji Maruyama
  • Publication number: 20110291761
    Abstract: Embodiments of the present disclosure use one or more gain stages to generate an output voltage representing whether a resistive memory element of a data cell stores a high data value or a low data value. In a particular embodiment, an apparatus includes a sensing circuit. The sensing circuit includes a first amplifier stage that is configured to convert a first current through a first resistive memory element of a memory cell into a first single-ended output voltage. A second amplifier stage is configured to amplify the first single-ended output voltage of the first amplifier stage to produce a second single-ended output voltage.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Applicant: QUALCOMM Incorporated
    Inventor: Hari M. Rao
  • Publication number: 20110291762
    Abstract: A semiconductor memory device includes a cell array including a plurality of unit cells, a first amplification circuit amplifying an input signal received from at least one unit cell among the unit cells, a signal transmission unit to transmit the signal to the first amplification circuit in response to a selection signal, first amplification control circuit to output a first amplification control signal controlling an amplification operation of the first amplification circuit, a second amplification circuit to amplify an output signal of the first amplification circuit, a second amplification control circuit to output a second amplification control signal controlling an amplification operation of the second amplification circuit, and a voltage adjustment circuit to adjust an internal voltage of the first amplification circuit in response to a voltage adjustment signal before the first and second amplification circuits perform the amplification operation.
    Type: Application
    Filed: July 12, 2010
    Publication date: December 1, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Keun Soo SONG
  • Publication number: 20110291763
    Abstract: A method for low noise signal amplification includes modifying a signal by way of a first amplification stage and conveying the modified signal to a second amplification stage. The method continues with comparing an output of the second amplification stage with a signal ground in a low-frequency feedback loop and changing a bias voltage for the first amplification stage as a result of the comparing step.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Inventor: David E. Smith
  • Publication number: 20110291764
    Abstract: A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through the input node is disclosed. The circuit has a frequency bias feedback network communicatively coupled between the output transistor and the input node for providing biasing to the Darlington transistor pair as well as for adjusting a phase and amplitude of an amplified version of the input signal that passes through the input transistor and into the frequency bias network. The circuit further includes a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of the amplified version of the input signal that passes through the input transistor.
    Type: Application
    Filed: May 3, 2011
    Publication date: December 1, 2011
    Applicant: RF MICRO DEVICES, INC.
    Inventor: Kevin Wesley Kobayashi
  • Publication number: 20110291765
    Abstract: Embodiments of circuits, apparatuses, and systems for an overdrive protection circuit arranged at an input to a primary power transistor to protect against overdrive conditions, where the overdrive protection circuit includes a sensing resistor. Other embodiments may be described and claimed.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 1, 2011
    Applicant: TRIQUINT SEMICONDUCTOR, INC.
    Inventors: Xiaopeng Sun, Mehra Mokalla, Wenlong Ma, Barry Jia-Fu Lin
  • Publication number: 20110291766
    Abstract: In a gain-switching-type transimpedance amplifier, in order to provide a technique capable of preventing unnecessary gain switching caused when noise is received, and preventing decrease in sensitivity caused when noise with a large input level is received, and then, a burst signal with a small input level is received, a transimpedance amplifier 5 includes: a pre-amplifier 200 to which the burst signal is inputted; an average detection start determination unit 300 for comparing an output of a pre-amplifier 200 with a first threshold voltage; an average detection circuit 400 for detecting and outputting an average value of the output of the pre-amplifier 200 during a certain period of time from a time point when the output of the pre-amplifier 200 exceeds the first threshold voltage; and a gain switching control unit 500 for determining whether to switch a gain of the pre-amplifier 200 based on an output of the average detection circuit 400.
    Type: Application
    Filed: January 13, 2010
    Publication date: December 1, 2011
    Applicant: HITACHI, LTD.
    Inventors: Daisuke Mashimo, Hiroki Ikeda, Yoshinobu Morita
  • Publication number: 20110291767
    Abstract: An oscillator circuit comprises a piezoelectric vibrator, an amplifier device including inverters provided in a plurality of stages, and an inverter control device. The inverters provided in the plurality of stages includes a performance-variable inverter configured which is operational in both of an initial phase of oscillation startup and a post-startup phase where the oscillation is stabilized and capable of a variable performance depending on whether the initial phase of oscillation startup or the post-startup phase where the oscillation is stabilized, and an ON/OFF inverter which is operational in the initial phase of oscillation startup and disconnected in the post-startup phase where the oscillation is stabilized.
    Type: Application
    Filed: July 22, 2010
    Publication date: December 1, 2011
    Inventors: Shinji Ishikawa, Ichiro Yamane
  • Publication number: 20110291768
    Abstract: A transforming circuit includes: a first winding having a first port and a second port operably coupled for a differential signal; and a plurality of second windings, each having a third port and a fourth port operably coupled for a single-ended signal when magnetically coupled to the first winding. When one of the second windings is magnetically coupled to the first winding, each remaining second winding(s) is not magnetically coupled to the first winding.
    Type: Application
    Filed: January 13, 2011
    Publication date: December 1, 2011
    Inventors: Shin-Fu Chen, Ling-Wei Ke, Ming-Fong Lei
  • Publication number: 20110291769
    Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.
    Type: Application
    Filed: August 9, 2011
    Publication date: December 1, 2011
    Inventors: Michael BURSTEIN, Boris GINZBURG, Andrew NIKISHIN
  • Publication number: 20110291770
    Abstract: Directional couplers are provided. In one embodiment, the directional coupler includes first and second transmission line segments positioned on a first plane and spaced apart by a first distance, third and fourth transmission line segments positioned on a second plane and spaced apart by a second distance, the second plane spaced apart from the first plane, a first conductive segment connecting the first and third transmission line segments, and a second conductive segment connecting the second and fourth transmission line segments, where the first and second transmission line segments are configured to couple energy therebetween, and where the third and fourth transmission line segments are configured to couple energy therebetween.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Inventors: Terry Cisco, Mary A. Teshiba
  • Publication number: 20110291771
    Abstract: Apparatus and methods are provided for a power matching apparatus for use with a processing chamber. In one aspect of the invention, a power matching apparatus is provided including a first RF power input coupled to a first adjustable capacitor, a second RF power input coupled to a second adjustable capacitor, a power junction coupled to the first adjustable capacitor and the second adjustable capacitor, a receiver circuit coupled to the power junction, a high voltage filter coupled to the power junction and the high voltage filter has a high voltage output, a voltage/current detector coupled to the power junction and a RF power output connected to the voltage/current detector.
    Type: Application
    Filed: August 9, 2011
    Publication date: December 1, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Steven C. Shannon, Jang Gyoo Yang, Matthew L. Miller, Kartik Ramaswamy, James P. Cruse
  • Publication number: 20110291772
    Abstract: A bond wire circuit includes at least three bond wires arranged to split an input signal into two output signals. In connection with various example embodiments, bond wires are arranged in a generally parallel manner to mitigate magnetic coupling and related issues for splitting an input signal and providing each of split signals to an amplifier. The bond wires are connected by capacitive circuits that facilitate the splitting, and in some applications, additional capacitive (to ground/reference) and load circuits to further facilitate the splitting of the input signals for specific amplifier circuit implementations, and applications to various loads. In some implementations, the input signals are split in equal or arbitrary portions with frequency independent phase differences in a wide frequency band, with isolation between ports of the circuit.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Inventor: Igor Blednov
  • Publication number: 20110291773
    Abstract: The invention relates to a dual-response stopband filter as well as to a filtering device comprising such a filter. The dual-response stopband filter comprises between the input terminal and the filter output a first direct channel and a second channel, known as a secondary channel, coupled with the first channel and forming a resonant element. The filter further comprises, integrated on the first direct channel, a selective low-pass filter to reject a first selected frequency band and, integrated on the second channel a variable capacitor to form the stopband filter of a second frequency band that can be determined. The switching device is associated with the first channel to switch the low-pass filter and the second channel to switch the stopband filter.
    Type: Application
    Filed: May 14, 2010
    Publication date: December 1, 2011
    Inventors: Dominique Lo Hine Tong, Jean-Yves Le Naour, Ali Louzir, Raafat Lababidi
  • Publication number: 20110291774
    Abstract: An equalizer includes an oversampling logic unit, a direct current setting unit, and an alternating current setting unit. The oversampling logic unit oversamples data from a channel to generate a plurality of direct current terms and a plurality of alternating current terms according to an oversampling clock, and outputting a plurality of direct current terms corresponding to an output clock and a plurality of alternating current terms corresponding to the output clock according to the output clock. The direct current setting unit adjusts a direct current setting of the equalizer according to a plurality of direct current terms inputted by the oversampling logic unit within a first predetermined time. And the alternating current setting unit adjusts an alternating current setting of the equalizer according to a plurality of alternating current terms inputted by the oversampling logic unit within the first predetermined time.
    Type: Application
    Filed: March 20, 2011
    Publication date: December 1, 2011
    Inventors: Kuo-Cyuan Kuo, Yu-Chiun Lin, Ming-Kia Chen
  • Publication number: 20110291775
    Abstract: A portable actuator and safety switch assembly wherein the portable actuator includes a housing and an actuator for selectively engaging with a control mechanism of said safety switch. The actuator is at least one of partially located within the housing, forms a part of the housing, or is attached to the housing. The assembly includes a controller that controls a configuration of the actuator assembly, such that the actuator assembly can selectively and controllably attain a first configuration wherein the actuator is able to interact with the control mechanism of the safety switch and a second configuration wherein the actuator is unable to manipulate the control mechanism of said safety switch.
    Type: Application
    Filed: April 11, 2011
    Publication date: December 1, 2011
    Inventors: Simon Hudson, Derek W. Jones
  • Publication number: 20110291776
    Abstract: A safety switch assembly having a number of fixed and movable contacts, a control mechanism that alters the conducting state of the contacts, and a magnetisable member that extends between alternate portions of the safety switch assembly. The safety switch assembly includes a magnetically operable electrical switch that is located in a body of the switch assembly and positioned proximate the magnetisable material such that changes in the magnetic condition of the magnetisable material alter the conducting state of the magnetically operable electrical switch.
    Type: Application
    Filed: May 23, 2011
    Publication date: December 1, 2011
    Inventor: Derek W. Jones
  • Publication number: 20110291777
    Abstract: A magnetically operated switch has a receiver which is mounted such that it is moveable between two switch positions, and which is used to actuate the magnetically operated switch, a housing relative to which the receiver is movably supported, a magnet, a magnetic sensor which interacts with the magnet, and evaluation electronics which are assigned to the magnetic sensor and can be used to generate a switch signal that is dependent on the switch positions of the receiver. To provide an improved magnetically operated switch, it has a magnetic shield which interacts with the magnet, the shield and the magnet are in different positions relative to one another depending on the switch positions of the receiver, and the evaluation electronics generate the switch signal depending on the relative positions.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Inventors: Winfried Stiltz, Christian Uhlig, Achim Weirowski-Herz, Roland Hengstler
  • Publication number: 20110291778
    Abstract: A quadrupole magnetic coded switch includes a switch housing, an actuator, one or more switch dipole magnets, and a plurality of magnetically operated switch circuits. The actuator housing is movable relative to the switch housing. The plurality of actuator dipole magnets are coupled to the actuator housing and are movable therewith. The one or more switch dipole magnets are coupled to the switch housing. The one or more switch dipole magnets and the plurality of actuator dipole magnets are arranged to generate a quadrupole magnetic field. Each magnetically operated switch circuit is disposed within the switch housing and is configured to transition between a plurality of switch positions in response to relative movement of the actuator housing and the switch housing.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventor: Gangi Reddy Rajula
  • Publication number: 20110291779
    Abstract: A superconducting coil is accommodated in a vacuum chamber. A radiation shield is arranged in the vacuum chamber with a prescribed space from the vacuum chamber to surround a periphery of the superconducting coil. A refrigerator cools the superconducting coil and the radiation shield by conduction. A provided member at least partly lies between the vacuum chamber and the radiation shield, through which heat is conducted from the vacuum chamber to the radiation shield. A cooling pipe has opposite end portions drawn out of the vacuum chamber and an intermediate portion in contact with the superconducting coil, the radiation shield, and the provided member. The provided member dissipates heat into a coolant flowing through the cooling pipe, to reduce the heat conducted to the radiation shield.
    Type: Application
    Filed: November 29, 2010
    Publication date: December 1, 2011
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tatsuya INOUE, Shoichi Yokoyama
  • Publication number: 20110291780
    Abstract: A magnetic encoder magnetizing method, in which magnetization of the plural neighboring tracks of the magnetic encoder can be accurately performed, is provided. While an annular magnetic body having a plurality of annular, unmagnetized magnetic encoder tracks integral therewith and juxtaposed relative to each other is rotated, the tracks of the magnetic encoder are individually magnetized by a magnetizing head, made up of a magnetizing yoke and an exciting coil, to thereby provide the magnetic encoder. In the practice of this magnetizing method, when one of the tracks of the magnetic encoder is magnetized, the other track is covered with a magnetic shielding mask.
    Type: Application
    Filed: February 9, 2010
    Publication date: December 1, 2011
    Applicant: NTN CORPORATION
    Inventors: Toru Takahashi, Shintarou Ueno, Pascal Desbiolles, Cyril Peterschmitt
  • Publication number: 20110291781
    Abstract: The magnetized structure that induces in a central area of interest a homogeneous magnetic field oriented along a longitudinal axis (z) of the structure comprises first and second magnetized rings (111, 121) disposed symmetrically relative to a plane (P) that is perpendicular to said longitudinal axis (z) and that contains said central area of interest, and one median annular magnetized structure (330) disposed between the first and second magnetized rings (111, 121) and also disposed symmetrically relative to the plane (P) of symmetry. The first magnetized ring (111) is magnetized radially relative to the longitudinal axis (z) with divergent magnetization, the second magnetized ring (121) is magnetized radially relative to the longitudinal axis (z) with convergent magnetization, and the median annular magnetized structure (330) is magnetized along the longitudinal axis (z).
    Type: Application
    Filed: August 27, 2010
    Publication date: December 1, 2011
    Inventors: Dimitrios Sakellariou, Cédric Hugon, Guy Aubert
  • Publication number: 20110291782
    Abstract: In a solenoidal electromagnet arrangement for a magnetic resonance imaging system, annular inner coils and annular end coils are provided, all concentrically aligned about an axis, the end coils being placed at axial extremities, axially outside of the inner coils. A pair of annular outer coils are provided concentrically aligned about the axis. An arrangement is provided retaining the pair of outer coils against an axial force urging the outer coils away from one another. The arrangement comprises strap elements which extend around a radially inner surface, a radially outer surface and an axially outer surface of each outer coil in certain circumferential locations. Each strap element on one of the outer coils is linked to a corresponding strap element on the other outer coil of the pair by a tensile member.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Inventor: Simon James Calvert
  • Publication number: 20110291783
    Abstract: Disclosed is a magnetic element that makes it possible to prevent a coil terminal from being positioned on a ring mount. The magnetic element comprises a first core member, coils, which are disposed in a second core member and a bobbin, and a first mount, on which the first core member is mounted, and possesses a second mount, which is disposed rising up from, and positioned between both edges of, the first mount, and on which the second core member is mounted, and is further equipped with a base, with multiple terminals disposed protruding from the sides thereof. Furthermore, a protrusion is disposed at the edge of the second mount, extending in the direction moving away from said second mount, and this protrusion is smaller than the thickness dimension of the base, and a terminal is positioned on the back surface of the protrusion on the opposite side from the side on which the second core member is mounted, and then bound to the terminals.
    Type: Application
    Filed: January 28, 2010
    Publication date: December 1, 2011
    Applicant: SUMIDA CORPORATION
    Inventors: Yuichi Yamada, Takayuki Yamaguchi
  • Publication number: 20110291784
    Abstract: An electronic component capable of adjusting the number of turns of a coil without preparing multiple kinds of inner conductors to be positioned at an end of the layer direction is composed of a multilayer body having multiple laminated magnetic layers. A spiral coil includes inner conductors and via-hole conductors connected to each other. Each of the inner conductors has a length of one turn. Both ends of each of the inner conductors are over points A and B. The inner conductor provided at the most negative side in the z-axis direction branches at one end so as to be over the points A and B.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoichi NAKATSUJI
  • Publication number: 20110291785
    Abstract: A variety of power inductor structures are obtained by arranging a magnetic material block between a plurality of wires and a plurality of bond fingers or bond finger pairs. The power inductor structure can provide high inductance and high currents and at the same time afford smaller sizes.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sungmook Lim, Yunjae Chong, Sungmo Kang
  • Publication number: 20110291786
    Abstract: A through via inductor or transformer in a high-resistance substrate in an electronic package. In one embodiment, the package comprises a target inductor which includes a through-via formed in the substrate through which a signal passes and a tuner inductor which includes a through-via formed in the substrate such that the through-via has an independent signal passing therethrough. The direction of the signal passing through the tuner inductor can be independently controlled to adjust the total inductance of the target inductor. In another embodiment, a transformer can comprise a primary loop and a secondary loop, each of which includes a plurality of through-vias that are coupled to a plurality of conductive traces. The primary loop forms a first continuous conductive path and the secondary loop forms a second continuous conductive path. A signal passing through the primary loop can induce a signal in the secondary loop such that the induced signal is dependent on the transformer ratio.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Applicant: QUALCOMM Incorporated
    Inventors: Xia Li, Jonghae Kim, Chi Shun Lo
  • Publication number: 20110291787
    Abstract: A planar inductor device includes a ferrite body and a conductive pathway. The ferrite body extends around an opening in the ferrite body. The conductive pathway includes an input section, a current-splitting section, a coil section, a current-combining section, and an output section connected with each other, the input section extending toward the opening in the ferrite body. The current-splitting section includes a plurality of conductive coils joined with the conductive pathway and electrically disposed parallel to each other. The coil section includes the conductive coils helically wrapped around the ferrite body. The current-combining section includes the conductive coils joined with each other. The output section includes the joined conductive coils extending out of the ferrite body.
    Type: Application
    Filed: April 14, 2011
    Publication date: December 1, 2011
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventors: Sidharth Dalmia, Shanit Vannala, Zhuowen Sun, Steven R. Kubes
  • Publication number: 20110291788
    Abstract: A planar inductor device includes a substrate, a ferrite body in the substrate, upper and lower conductors, and conductive vias. The substrate vertically extends from an upper surface to an opposite lower surface. The substrate laterally extends from a first edge to a second edge. The upper conductors are disposed above the ferrite body. The lower conductors are disposed below the ferrite body. The conductive vias extend through the substrate and are conductively coupled with the upper conductors and with the lower conductors. The vias, the upper conductors, and the lower conductors form one or more conductive coils that encircle the ferrite body in the substrate. At least one of the first edge or the second edge of the substrate passes through one or more of the vias such that the vias are exposed at the at least one of the first edge or the second edge.
    Type: Application
    Filed: April 14, 2011
    Publication date: December 1, 2011
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventors: Sidharth Dalmia, William Lee Harrison
  • Publication number: 20110291789
    Abstract: A multilayer inductor device includes a planar substrate, a ferrite body, and an outer and an inner conductive coil. The substrate includes plural dielectric layers with the ferrite body is disposed in the substrate. The outer and inner conductive coils are helically wrapped around the ferrite body. The outer conductive coil includes first upper conductors, first lower conductors, and first conductive vias vertically extending through the substrate and conductively coupled with the first upper and lower conductors. The inner conductive coil includes second upper conductors, second lower conductors, and second conductive vias vertically extending through the substrate and conductively coupled with the second upper and lower conductors. The inner conductive coil is disposed between the outer conductive coil and the ferrite body.
    Type: Application
    Filed: April 14, 2011
    Publication date: December 1, 2011
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventors: Sidharth Dalmia, Khanh Nguyen, Jaydip Das, Mark McGrath, William Lee Harrison
  • Publication number: 20110291790
    Abstract: A coil component is provided with a magnetic substrate made of magnetic ceramic material, a thin-film coil layer containing a coil conductor formed on one principal surface of the magnetic substrate, a plurality of bump electrodes formed on the principal surface of the thin-film coil layer, and an insulating resin layer formed on the principal surface of the thin-film coil layer excluding formation positions of the bump electrodes. Each bump electrode has an exposure surface on a bottom surface and on two side surfaces of a layered product composed of the magnetic substrate, the thin-film coil layer and the insulating resin layer. A corner of the each bump electrode has a notch portion. The insulating resin layer includes a center resin portion provided in a center of the principal surface of the thin-film coil layer and a plurality of corner resin portions provided in the notch portion of each bump electrode.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 1, 2011
    Inventors: Takeshi Okumura, Tomokazu Ito