Abstract: A method of coating a light emitting device is provided. The method includes preparing a plurality of light emitting devices. The plurality of light emitting devices are coated with a first photocurable liquid. First light is selectively exposed to the first photocurable liquid to form a first coating layer on at least a partial region of a surface of each of the plurality of light emitting devices. The plurality of light emitting devices on which the first coating layer is formed are coated with a second photocurable liquid. Second light is selectively exposed to the second photocurable liquid to form a second coating layer on at least a partial region of the surface of each of the plurality of light emitting devices or a surface of the first coating layer. The first coating layer corresponds to the cured first photocurable liquid, while the second coating layer corresponds to the cured second photocurable liquid.

Abstract: To provide a light-emitting display apparatus having a curved display face which can be manufactured with ease and high yield. The light-emitting display apparatus includes a curved and light-transmitting substrate 1 and a flat light-emitting display panel 2. The light-emitting display panel 2 is placed and fixed onto a curved face 1b of the substrate 1. A plurality of the light-emitting display panels 2 are arranged side by side on the curved face 1b. An outer peripheral portion of the light-emitting display panel 2 on the side of a display face is bonded to the curved face 1b through an adhering member 3. The adhering member 3 is a light-shielding member.

Abstract: A planar light source device is provided which satisfies the inequality ?1<?2, where ?1 is the angle formed between the direction in which an array of mortar-shaped light-emitting devices (50) emits light of maximum intensity and a vertical direction on a plane containing the vertical direction and the X direction or on a plane containing the vertical direction and the Y direction and ?2 is the angle formed between the direction in which the array of mortar-shaped light-emitting devices (50) emits light of maximum intensity and a diagonal direction (C) across the array on a plane containing the vertical direction and the diagonal direction (C), the first and second unevenness eliminating sheets (113a and 113b) each having surfaces one of which is more distant from the light sources than the other and is shaped such that shapes having upwardly convex cross-sections and extending along a longitudinal direction are arranged at pitches (P?), the pitches (Px and Py) being longer than the pitches (P?).

Abstract: The LED unit 100 comprises a plurality of the LED module 1 and the heat radiation plate. Each the LED module 1 comprises the LED chip and the package for incorporating the LED chip therein; the package has the electrical insulation property. Each the package comprises the sub-mount member which is located between the LED chip and the heat radiation plate and which has heat conductivity; these are integrally formed. The LED modules are arranged on the first surface of the heat radiation plate. This configuration makes it possible for the LED unit to efficiently disperse the heat in the LED chip 10 to the heat radiation plate.

Abstract: A method of manufacturing an Organic Light Emitting Diode (OLED). A substrate (101) is provided, and a plurality of pixel electrodes (102) is formed on the substrate resulting in at least one gap (105) between two adjacent pixel electrodes. A dielectric material (103) is deposited in the gap. The resulting structure is subjected to a process which ensures that at least a portion of the surface of the pixel electrodes is not covered by the dielectric material. At least the portion of the surface of the pixel electrodes is covered with a layer of an organic compound so as to form the OLED.

Abstract: Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.

Abstract: In general, embodiments of the present invention provide a variable height LED and method of manufacture. Specifically, under embodiments of the present invention, a buffer layer is applied (e.g., selectively) over a wafer, and a set of LED chips is provided over the buffer layer. One role of the buffer layer is to increase a height of at least a subset of the chips. As such, the buffer layer could be applied using any processing method now known or later developed. For example, the buffer layer could be selectively deposited, etched, etc. Regardless, in a typical embodiment, the buffer layer comprises a mesa structure having a thickness less than approximately 100 ?m. In addition, the mesa structure is typically constructed from three RGB wafers.

Abstract: An organic light-emitting display panel is provided that improves luminous efficiency and luminescent color by adjusting the difference in film thickness between layers of different luminescent colors, such as intermediate layers, when the intermediate layer and light-emitting layers are formed by a wet method. By varying the film thickness of an interlayer insulation film, which is a lower layer of an organic light-emitting element, the volume of a contact hole is varied by color, thereby adjusting the volume of a concavity in each anode plate. When ink that includes material for the intermediate layer, or like, is sprayed by an inkjet method, the film thickness of the intermediate layer, or like, changes in accordance with the amount of ink filing the concavity. Therefore, by adjusting the difference in volume between concavities of different colors, the difference in film thickness between the intermediate layers, or like, is finely adjusted.

Abstract: A light emission device includes multiple electrically activated solid state emitters (e.g., LEDs) having differing spectral output from one another; and/or phosphor material including one or more phosphors arranged to receive spectral output from at least one of the solid state emitters and to responsively emit a phosphor output, to provide spectral output. In one arrangement, multiple LEDs and multiple phosphors have different peak wavelengths and provide aggregated light output with less than four light emission peaks. In one arrangement, a plot of aggregated output emissions (light intensity versus wavelength) has a non-negative slope between more than two wavelength peaks. In one arrangement, a light emission device generates a user-perceptible transition in color of light at a predetermined time period as an indicative of a need to perform at least one selected task.

Abstract: According to one embodiment, a semiconductor light emitting device includes: semiconductor layers; a multilayered structural body; and a light emitting portion. The multilayered structural body is provided between the semiconductor layers, and includes a first layer and a second layer including In. The light emitting portion is in contact with the multilayered structural body between the multilayered structural body and p-type semiconductor layer, and includes barrier layers and a well layer including In with an In composition ratio among group III elements higher than an In composition ratio among group III elements in the second layer. An average lattice constant of the multilayered structural body is larger than that of the n-type semiconductor layer. Difference between the average lattice constant of the multilayered structural body and that of the light emitting portion is less than difference between that of the multilayered structural body and that of the n-type semiconductor layer.

Abstract: The present invention introduces the novel, improved design approach of the semiconductor devices that utilize the effect of carrier recombination, for example, to produce the electromagnetic radiation. The approach is based on the separate control over the injection of the electrons and holes into the active region of the device. As a result, better recombination efficiencies can be achieved, and the effect of the wavelength shift of the produced radiation can be eliminated. The devices according to the present invention outperform existing solid state light and electromagnetic radiation sources and can be used in any applications where solid state light sources are currently involved, as well as any applications future discovered.

Abstract: An optoelectronic component comprises an organic layer sequence (1), which emits an electromagnetic radiation (15) having a first wavelength spectrum during operation, and also a dielectric layer sequence (2) and a wavelength conversion region (3) in the beam path of the electromagnetic radiation (15) emitted by the organic layer sequence (1). The wavelength conversion region (3) is configured to convert at least partially electromagnetic radiation having the first wavelength spectrum into an electromagnetic radiation (16) having a second wavelength spectrum. The dielectric layer sequence (2) is arranged in the beam path of the electromagnetic radiation (15) emitted by the organic layer sequence between the organic layer sequence (1) and the wavelength conversion region (3) and is at least partially opaque to an electromagnetic radiation having a third wavelength spectrum, which corresponds to at least one part of the second wavelength spectrum.

Abstract: A Light-Emitting Diode (LED) includes a light-emitting structure having a passivation layer disposed on vertical sidewalls across a first doped layer, an active layer, and a second doped layer that completely covers at least the sidewalls of the active layer. The passivation layer is formed by plasma bombardment or ion implantation of the light-emitting structure. It protects the sidewalls during subsequent processing steps and prevents current leakage around the active layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a light emitting portion, a first transparent conductive layer, and a second transparent conductive layer. The light emitting portion is provided between the first and second semiconductor layers. The second semiconductor layer is disposed between the first transparent conductive layer and the light emitting portion. The first transparent conductive layer includes oxygen. The second transparent conductive layer is provided between the second semiconductor layer and the first transparent conductive layer. The second transparent conductive layer has a refractive index higher than a refractive index of the first transparent conductive layer, and includes oxygen at a concentration higher than a concentration of oxygen included in the first transparent conductive layer.

Abstract: A semiconductor light emitting device of one embodiment includes: a substrate; an n-type layer of an n-type nitride semiconductor on the substrate; an active layer of a nitride semiconductor on the n-type semiconductor layer; a p-type layer of a p-type nitride semiconductor on the active layer. The p-type layer has a ridge stripe shape. The device has an end-face layer of a nitride semiconductor formed on an end face of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer. The end face is perpendicular to an extension direction of the ridge stripe shape. The end-face layer has band gap wider than the active layer. The end-face layer has Mg concentration in the range of 5E16 atoms/cm3 to 5E17 atoms/cm3 at a region adjacent to the p-type layer.

Abstract: Embodiments of a light emitting diode (LED) package structure are provided. In one aspect, an LED package structure includes a base, at least one LED chip, a blocking plate, and a transparent cover plate. The LED chip is disposed on and electrically coupled to the base. The blocking plate is disposed on the base and surrounds the LED chip. The blocking plate has an opening for exposing the LED chip. The blocking plate comprises a light-absorbing material that is opaque. The transparent cover plate is disposed on the blocking plate and covers the opening of the blocking plate.

Abstract: The invention provides a white light emitting diode device, which includes: a conductive substrate; a multilayered light emitting semiconductor epitaxial structure formed on the conductive substrate; a contact provided on the multilayered light emitting semiconductor epitaxial structure; a transparent layer provided on the multilayered light emitting semiconductor epitaxial structure; a wavelength converting layer provided on the transparent layer; and an optical layer provided on the wavelength converting layer. The invention also provides a method of manufacturing the white light emitting diode device.

Abstract: There is provided a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked. The contact area between the first electrode layer and the first semiconductor layer is 3% to 13% of the total area of the semiconductor light emitting device, and thus high luminous efficiency is achieved.

Abstract: A light-emitting device includes a circuit board to which external electric power is supplied, a light emitting diode that is electrically connected onto the circuit board and emits light based on electric power from the circuit board, a housing provided on the circuit board so as to surround the light emitting diode and so that the upper end portion of the housing is positioned above the upper end portion of the light emitting diode, and a fluorescent laminate provided on the housing. The fluorescent laminate includes a first fluorescent layer that emits fluorescent light and a second fluorescent layer that emits fluorescent light having a wavelength that is longer than that of the first fluorescent layer. The second fluorescent layer is disposed on the housing and the first fluorescent layer is laminated on the second fluorescent layer.

Abstract: Light emitting structures are disclosed that can include a semiconductor light emitting diode (LED) that includes a p-n junction active layer. A first layer can include a binder material having a thickness that is less than about 1000 ?m, wherein the first layer is directly on the LED. A second layer can include phosphor particles, where the second layer can have a thickness that is less than about 1000 ?m and can be directly on the first layer so that the first layer is between the LED and the second layer.

Abstract: An organic light-emitting diode includes an organic light-emitting layer located between a transparent electrode and one other electrode on a substrate. In some embodiments at least one of the transparent electrode and the other electrode has two layers. The two layers include a structured layer, which is a charge carrier injection layer, and a conductive second layer into which the first layer is embedded. In some embodiments the organic light-emitting layer includes a structured charge carrier blocking layer.

Abstract: A method for producing a light-emitting device, includes: performing, on a first substrate made of III-V group compound semiconductor, crystal growth of a laminated body including an etching easy layer contiguous to the first substrate and a light-emitting layer made of nitride semiconductor; bonding a second substrate and the laminated body; and detaching the second substrate provided with the light-emitting layer from the first substrate by, one of removing the etching easy layer by using a solution etching method, and removing the first substrate and the etching easy layer by using mechanical polishing method.

Abstract: An ultraviolet light emitting diode package for emitting ultraviolet light is disclosed. The ultraviolet light emitting diode package comprises an LED chip emitting light with a peak wavelength of 350 nm or less, and a protective member provided so that surroundings of the LED chip is covered to protect the LED chip, the protective member having a non-yellowing property to energy from the LED chip.

Abstract: An electrical connection structure for use in an electronic component, a light emitting diode (LED) module, a fabric circuit and a signal textile with the same are provided. The electrical connection structure comprises a plurality of J-type leads which electrically connect to the electronic component and encircle two conductive lines. Thus, the electronic component can be firmly attached and electrically connected to the two conductive lines.

Abstract: The object of the invention is to improve the visual inspection yield of a semiconductor light emitting device. To achieve the object, a semiconductor light emitting device includes a semiconductor layer, a pad electrode on the layer, and a protection film covering at least the layer. The device includes at least one stopper arranged on a peripheral part of the pad electrode surface away from the film. The stopper has a semicircular arc shape opening toward the center of the pad electrode. In electrical/optical property inspection, if sliding on the pad electrode, a probe needle can be guided into the concave surface of the semicircular arc shape. The stopper can reliably hold the needle. It is avoidable that the needle contacts the film. It is preferable that each of positive/negative electrodes have the pad electrode, and a pair of stoppers be arranged in positions on the electrodes facing each other.

Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.

Abstract: A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.

Abstract: A first first-conductivity-type diffusion layer, a first second-conductivity-type diffusion layer, a second first-conductivity-type diffusion layer, and a second second-conductivity-type diffusion layer are arranged in this order. In a region where the second second-conductivity-type diffusion layer and the first-conductivity-type layer are in contact with each other, impurity concentrations thereof are higher in a part in contact with a side face of the second second-conductivity-type diffusion layer than in a part at a bottom surface of the second second-conductivity-type diffusion layer.

Abstract: A silicon wafer contains: a silicon substrate; a first epitaxial layer on the silicon wafer, wherein the absolute value of the difference between donor and acceptor concentrations is ?1×1018 atoms/cm3; a second epitaxial layer above the first epitaxial layer, whose conductivity type is the same as the first epitaxial layer, wherein the absolute value of the difference between donor and acceptor concentrations is ?5×1017 atoms/cm3; wherein, by doping a lattice constant adjusting material into the first epitaxial layer, the variation amount ((a1-aSi)/aSi) of the lattice constant of the first epitaxial layer (a1) relative to the lattice constant of the silicon single crystal (aSi) as well as the variation amount ((a2-aSi)/aSi) of the lattice constant of the second epitaxial layer (a2) relative to the lattice constant of the silicon single crystal (aSi) are controlled to less than the critical lattice mismatch.

Abstract: The present invention provides a method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. The present invention also provides a semiconductor device manufactured by this process.

Abstract: A MOS transistor structure with an in-situ doped source and/or drain and a method for forming the same are provided. The method comprises steps of: providing a substrate; forming a high Ge content layer on the substrate; forming a gate stack on the high Ge content layer and forming a side wall of one or more layers on both sides of the gate stack; etching the high Ge content layer to form a source region and/or a drain region; and forming a source and/or a drain in the source region and/or the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and/or the drain and to in-situ activate a doping element.

Abstract: A semiconductor device protects against concentration of electric current at a front end portion of one of the electrodes thereof The semiconductor device includes a substrate, a compound semiconductor layer formed on the substrate and having a channel layer based on a hetero junction, a first main electrode formed on the compound semiconductor layer, a second main electrode formed on the compound semiconductor surrounding the first main electrode and having a linear region and an arc-shaped region, a control electrode formed on the compound semiconductor layer and disposed opposite to the first main electrode and the second main electrode, an electric current being made to flow between the first main electrode and the second main electrode, and an electric current limiting section formed between the first main electrode and the arc-shaped region of the second main electrode.

Abstract: A Silicon-Germanium heterojunction bipolar transistor (SiGe HBT) formed on a silicon substrate, wherein, an active region is isolated by field oxide regions, a collector region is formed in the active region and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions. Each of the pseudo buried layers is a lateral distance away from the active region and contacts with a part of the collector region. Deep-hole contacts are formed in the field oxide regions located on top of the pseudo buried layers to pick up the collector region. The present invention can adjust the breakdown voltage of devices through adjusting the lateral distance. A method for manufacturing the SiGe HBT is also disclosed.

Abstract: Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface.

Abstract: A CMOS (Complementary Metal Oxide Semiconductor) pixel for sensing at least one selected from a biological, chemical, ionic, electrical, mechanical and magnetic stimulus. The CMOS pixel includes a substrate including a backside, a source coupled with the substrate to generate a background current, and a detection element electrically coupled to measure the background current. The stimulus, which is to be provided to the backside, affects a measurable change in the background current.

Abstract: An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract: An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.

Abstract: The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel.

Abstract: A semiconductor device includes a field effect transistor including: a semiconductor substrate including a channel forming region; a gate insulating film formed at the channel forming region on the semiconductor substrate; a gate electrode formed over the gate insulating film; a first stress application layer formed over the gate electrode and applying stress to the channel forming region; a source/drain region formed on a surface layer portion of the semiconductor substrate at both sides of the gate electrode and the first stress application layer; and a second stress application layer formed over the source/drain region in a region other than at least a region of the first stress application layer and applying stress different from the first stress application layer to the channel forming region.

Abstract: An image sensor includes: a substrate, at least a pixel, and at least a light shield is provided. Wherein the pixel includes a photodiode and at least a transistor, and the transistor is connected to a metal line via a contact. The light shield is positioned around at least one side of the pixel, wherein the light shield is made while forming the contact.

Abstract: A semiconductor device includes: a diffusion layer configuring a memory cell, and a diffusion layer configuring a dummy cell formed over the semiconductor substrate, interlayer insulating films formed over the semiconductor substrate, a cylinder layer insulating film including at least one concavity overlapping a diffusion layer and formed over an interlayer insulating film, a contact plug formed over one diffusion layer, a contact plug formed over another diffusion layer, a lower electrode formed over the side surfaces and bottom surface of the concavity and coupled to the diffusion layer by way of the contact plug, a dielectric material film formed over the lower electrode, over the cylinder layer insulating film and over the contact plug, and coupling by way of the contact plug to the diffusion layer, and an upper electrode formed over the inductive film material.

Abstract: According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

Abstract: A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.

Abstract: A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a semiconductor substrate, a memory cell transistor formed in a memory cell region, and a field-effect transistor formed in a peripheral circuit region. The memory cell transistor includes: a floating gate electrode; a first inter-electrode insulating film; and a control gate electrode. The field-effect transistor includes: a lower gate electrode; a second inter-electrode insulating film having an opening; and an upper gate electrode electrically connected to the lower gate electrode via the opening. The control gate electrode and the upper gate electrode are formed by a plurality of conductive films that are stacked. The control gate electrode and the upper gate electrode include a barrier film formed in one of interfaces between the stacked conductive films and configured to suppress diffusion of metal atoms. The control gate electrode and the upper gate electrode have a part that is silicided.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×1020 to 5×1021 [atom/cm3].

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a multilayer body, a semiconductor pillar, a memory layer, a first insulating film and a second insulating film. The multilayer body includes a plurality of interelectrode insulating films and a plurality of electrode films alternately stacked in a first direction. The semiconductor pillar penetrates through the multilayer body in the first direction. The memory layer is provided between each of the electrode films and the semiconductor pillar and extends in the first direction. The first insulating film is provided between the memory layer and the semiconductor pillar and extends in the first direction. The second insulating film is provided between each of the electrode films and the memory layer and extends in the first direction. The second insulating film is projected between the electrode films.