Abstract: A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. A first and a second Ohmic contact are applied to the first and the second doped regions of the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device to produce electromagnetic radiation upon the application of electrical power to the first and second Ohmic contacts.

Abstract: A method of manufacturing a back side illumination image sensor according to an embodiment includes: forming an ion implantation layer by implanting ions throughout the front side of a first substrate; defining a pixel region by forming a device isolation region on the front side of the first substrate; forming a photosensitive device and a readout circuit on the pixel region; forming an interlayer dielectric layer and a metal line on the front side of the first substrate; bonding a second substrate with the front side of the first substrate where the metal line is formed; removing a lower part of the first substrate under the ion implantation layer; applying wet etching to a back side of the first substrate after removing the lower part; and forming a microlens on the photosensitive device at the back side of the first substrate.

Abstract: A method of producing a solid-state image pickup element includes forming a hole portion, forming a first-conductive type high-concentration impurity region in a bottom wall of the hole portion, and forming a first-conductive type high-concentration impurity-doped element isolation region in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region. The method also includes forming a second-conductive type photoelectric conversion region beneath the first-conductive type high-concentration impurity region and adapted to undergo a change in charge amount upon receiving light, and forming a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A piezoelectric microphone, a speaker, a microphone-speaker integrated device and a manufacturing method thereof are provided. The microphone-speaker integrated device includes a silicon substrate and an insulating layer deposited on the silicon substrate; a piezoelectric plate formed on the insulating layer; and a mating electrode formed on the piezoelectric plate. The mating electrode is patterned with a polarity arrayed in series.

Abstract: A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching.

Abstract: A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

Abstract: In the present invention, a semiconductor substrate wherein a plurality of MEMS microphones is formed is disposed opposed to a discharge electrode in a state of being stuck on a sheet. Electretization of a dielectric film provided in the MEMS microphone is performed by irradiating the dielectric film between a fixed electrode and a vibration film provided in the MEMS microphone with ions resulting from a corona discharge of the discharge electrode in a state that a predetermined potential difference is applied to the fixed electrode and the vibration film and fixing charges based on the ions to the dielectric film. The electretization is successively performed to each MEMS microphone on the semiconductor substrate by relatively moving the semiconductor substrate and the discharge electrode. Therefore, electretization of the dielectric film in the MEMS microphone chip is realized using a low-cost and simple fabricating equipment and productivity can be enhanced.

Abstract: Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.

Abstract: The invention provides a method of manufacturing a monolithic thin-film photovoltaic cell or module with enhanced output voltage as high as 100 V or higher in a single microelectronic process without connecting in series a plurality of premanufactured solar cells. The method consists of forming a plurality of adjacent individual TSCs arranged on a common transparent substrate in the longitudinal direction of the substrate. Each TSC consists of a pair of PV cells having PIN and NIP structures, respectively, with substantially coplanar position of a P-doped layer of one of the cells with respect to an N-doped layer of another cell of the pair. A tunnel junction is formed between the cells of the pair by overlapping P-doped and N-doped layers in the area near the common transparent substrate.

Abstract: According to one embodiment, a method of manufacturing an organic EL device includes providing a structure including a substrate and an electrode positioned above the substrate, and forming an organic layer including a mixture of first and second organic materials above the electrode. The first organic material has a first sublimation point. The second organic material has a second sublimation point higher than the first sublimation point. The formation of the organic layer includes heating an evaporation material including a mixture of the first and second organic materials to an evaporation temperature so as to sublimate the first and second organic materials, and delivering the sublimed first and second organic materials toward the electrode to deposit a mixture including the first and second organic materials above the electrode. The evaporation temperature is, for example, a temperature higher than the second sublimation temperature by 50° C. or more.

Abstract: Disclosed herein are a method for fabricating an organic thin film transistor, including treating the surfaces of a gate insulating layer and source/drain electrodes with a self-assembled monolayer (SAM)-forming compound through a one-pot reaction, and an organic thin film transistor fabricated by the method. According to example embodiments, the surface-treatment of the gate insulating layer and the source/drain electrodes may be performed in a single vessel through a single process.

Abstract: A method for producing an electrically-conductive inorganic coating includes depositing, on a substrate, a coating-precursor containing a plurality of inorganic particles and at least one kind of organic component by a liquid-phase method by using a material-liquid containing the inorganic particles and an organic solvent. The inorganic particles are coated with a dispersant binding to the surfaces of the inorganic particles by chemical bonds that can be broken by oxidation. Further, the method includes oxidizing the coating-precursor at a temperature exceeding 100° C., and that is less than or equal to the pyrolysis initiation temperature of an organic component that has the highest pyrolysis initiation temperature among the at least one kind of organic component and less than or equal to the heat-resistance temperature of the substrate, thereby breaking the chemical bonds to eliminate the dispersant from the surfaces, and decomposing the at least one kind of organic component.

Abstract: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions of the top surface of the lead frame. The integrated circuit die is wire bonded to the lead fingers with a plurality of wire stitches subsequent to substantially removing the gold. The die is encapsulated in a mold compound to form a packaged integrated circuit.

Abstract: A temporary substrate having an array of first solder pads is bonded to the front side of a first substrate by reflowing an array of first solder balls. The first substrate is thinned by removing the back side, and an array of second solder pads is formed on the back side surface of the first substrate. The assembly of the first substrate and the temporary substrate is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip and a handle portion. A second semiconductor chip is bonded to an assembly through an array of the second solder balls. The handle portion is removed from each assembly by reflowing the array of the first solder balls, while the array of the second solder balls does not reflow. The assembly is subsequently mounted on a packaging substrate employing the array of the first solder balls.

Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: A lead frame facilitates the handling, positioning, attachment, and/or continued integrity of multiple dies, without the use of multiple separate parts, such as jumpers. The lead frame includes a number of structures, each of which is attached to at least one lead. At least one receiving surface, arranged to receive a die, is associated with each structure. When dies are disposed on the receiving surfaces, anodes are similarly-oriented. A number of fingers are attached to the lead frame, and one or more electrode contact surfaces are attached to each finger. Each electrode contact surface can be positioned (for example, bent) with respect to one receiving surface, to facilitate electrical connection between the anode of a die and a lead. The lead frame may be used in connection with surface- and through-hole-mountable electronic devices, such as bridge rectifier modules.

Abstract: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip.

Abstract: A method of treating a component can include providing a component including a plurality of metallic posts extending generally parallel to one another. The providing step can be performed so that the posts have solder on the tips of the posts but not covering other portions of the posts. The method can include reflowing the solder provided on the posts so that the solder coats the posts. The providing step may be performed so that, prior to the reflowing step, the solder covers only the tips of the posts. The providing step can include depositing portions of the solder on a surface of a metallic sheet and etching the sheet from the surface. The plurality of posts may comprise elongated posts.

Abstract: A method of fabricating a semiconductor device package is provided. The method includes providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having a dielectric film outer surface and a first metal layer outer surface; forming a plurality of vias extending through the laminate according to a predetermined pattern; attaching one or more semiconductor device to the dielectric film outer surface such that the semiconductor device contacts one or more vias after attachment; disposing an electrically conductive layer on the first metal layer outer surface and on an inner surface of the plurality of vias to form an interconnect layer comprising the first metal layer and the electrically conductive layer; and patterning the interconnect according to a predetermined circuit configuration to form a patterned interconnect layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device.

Abstract: A lead frame includes a base material having a front surface for mounting of a semiconductor chip and a back surface for connection with an external board, and an Ni layer having a thick section and thin section. The thick section is formed on the back surface of the base material, whereas the thin section is formed on all or a part of the front surface of the base material. It is preferable that the thick section has a thickness ranging from 2.5 to 5 ?m, and the thin section is 0.5-2 ?m thinner than the thick section. The lead frame can be manufactured with improved productivity by forming an Ni layer on both front and back surfaces of the base material, and then etching only the Ni layer formed on the front surface of the base material.

Abstract: An object is to provide an electronic device of a multilayer structure with high density and high reliability that can be reduced in size while incorporating an electronic component therein, and further provide a production method for easily producing such an electronic device. An electronic device of the present invention includes wiring layers and electrically insulating layers stacked on a core board and establishes predetermined electrical conduction between the wiring layers through upper-lower side conducting vias provided in the electrically insulating layers.

Abstract: A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage.

Abstract: Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.

Abstract: An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.

Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.

Abstract: A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.

Abstract: To suppress generation of dangling bonds, the present invention relates to a method for manufacturing a semiconductor device including the steps of: forming a semiconductor film; forming a gate insulating film and a gate electrode over the semiconductor film; forming an impurity region in the semiconductor film by addition of an impurity element having one conductivity type thereto; forming an insulating film containing fluorine with the semiconductor film, the gate insulating film, and the gate electrode covered therewith; heating the semiconductor film and the insulating film containing fluorine; and forming a wiring, which is electrically connected to the impurity region, over the insulating film containing fluorine. The insulating film containing fluorine is any one of a silicon oxide film containing fluorine, a silicon oxide film containing fluorine and nitrogen, or a silicon nitride film containing fluorine.

Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.

Abstract: A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure.

Abstract: The present invention discloses a method of manufacturing MOS device having a lightly doped drain (LDD) structure. The method includes: providing a first conductive type substrate; forming an isolation region in the substrate to define a device area; forming a gate structure in the device area, the gate structure having a dielectric layer, a stack layer, and a spacer layer on the sidewalls of the stack layer; implanting second conductive type impurities into the substrate with a tilt angle to form an LDD structure, wherein at least some of the impurities are implanted into the substrate through the spacer to form part of the LDD structure below the spacer layer; and implanting second conductive type impurities into the substrate to form source and drain.

Abstract: In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.

Abstract: An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).

Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.

Abstract: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device.

Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.

Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).

Abstract: A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region.

Abstract: A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal structure. The BN layer forming the support patterns has compressive stress as opposed to tensile stress and can therefore withstand cracking in the support patterns.

Abstract: A method of making a metal capacitor includes the following steps. A dielectric layer having a metal interconnection and a capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the metal interconnection and the dielectric layer can be prevented.

Abstract: In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

Abstract: A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.

Abstract: Methods of fabricating memory are disclosed. For example, a method includes fabricating rows of memory cells on pillars separated by isolation regions therebetween. Each pillar has a pair of memory cells, each on an opposite side thereof. The method also includes fabricating control gates substantially between the rows of memory cells, each control gate to control half the cells of each of its adjacent rows of memory cells, and fabricating word lines for the array, the word lines extending substantially parallel to the control gates for the cells.

Abstract: A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a floating gate that erase data using a channel erase procedure. An erase capacitor is coupled to the floating gate to provide a low voltage bias that decreases the voltage that is required to perform a Fowler-Nordheim erase process in the memory cell. The erase capacitor of the present invention is formed without adding a step in the manufacturing process of the memory cell. Memory cells of the present invention are low cost, high endurance, low voltage memory cells.

Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Abstract: A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

Abstract: An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.

Abstract: A method of forming a nonvolatile memory device which includes forming a first gate electrode on a gate insulating film formed on a semiconductor substrate. The first gate electrode having a lower portion formed on the gate insulating film and an upper portion having a gate length less than that of the lower portion formed on the lower portion. A spacer is formed contacting surfaces of the upper and lower portions, wherein a length of the spacer and the upper portion equals the length of the lower portion. An electric charge trapping film covers a portion of the semiconductor substrate, a surface of the lower portion, and a surface of the spacer. A second gate electrode is then formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode by the electric charge trapping film.