Abstract: Provided are a condenser lens-coupled photoconductive antenna device for terahertz wave generation and detection and a fabricating method thereof. A condenser lens-coupled photoconductive antenna device for terahertz wave generation and detection includes a condenser lens, a photoconductive thin film deposited on the condenser lens, and a metal electrode formed on the photoconductive thin film for a photoconductive antenna. In the antenna device, the condenser lens and the photoconductive thin film are coupled to each other.

Abstract: The present application is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present application is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate wafers. More specifically the photodiode array of the present application is fabricated such that the PN junctions are located on both the front side and back side surfaces of the array, and wherein the front side PN-junction is in electrical communication with the back side PN-junction. Still more specifically, the present application is a photodiode array aving PN junctions that are electrically connected from the front to back surfaces and which can be operated in a fully depleted mode at low reverse bias.

Abstract: There has been very little (if any) attention to address contamination diffusion within an integrated circuit (IC) because there are very few applications where a protective overcoat will be penetrated as part of the manufacturing process. Here, a sealing ring is provided that address this problem. Preferably, the sealing ring uses the combination of electrically conductive barrier rings and the tortuous migration path to allow an electronic device (i.e., thermopile), where a protective overcoat is penetrated during manufacture, to communicate with external devices while being isolated to prevent contamination.

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.

Abstract: CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure.

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.

Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.

Abstract: Methods of forming a PrCaMnO (PCMO) material by atomic layer deposition. The methods include separately exposing a surface of a substrate to a manganese-containing precursor, an oxygen-containing precursor, a praseodymium-containing precursor and a calcium-containing precursor. The resulting PCMO material is crystalline. A semiconductor device structure including the PCMO material, and related methods, are also disclosed.

Abstract: A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film.

Abstract: A method for fabricating a high quality freestanding nonpolar and semipolar nitride substrate with increased surface area, comprising stacking multiple films by growing the films one on top of each other with different and non-orthogonal growth directions.

Abstract: A semiconductor device manufacturing method includes loading a substrate, on which a high-k film is formed, into a processing chamber, performing a reforming process by heating the high-k film through irradiation of a microwave on the substrate, and unloading the substrate from the processing chamber.

Abstract: A chip level EMI shielding structure and manufacture method thereof are provided. The chip level EMI shielding structure includes a semiconductor substrate, at least one ground conductor line, a ground layer, and a connection structure. The ground conductor line is disposed on a first surface of the semiconductor substrate, and the ground layer is disposed on a second surface of the semiconductor substrate. The connection structure is formed on a lateral wall of the semiconductor substrate for connecting the ground conductor lines with the ground layer to form a shielding. With such arrangement, the chip level EMI shielding structure can reduce the chip size and the manufacturing cost.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device may include a first semiconductor chip including a semiconductor substrate, a first through via that penetrates the semiconductor substrate, a second semiconductor chip stacked on one plane of the first semiconductor chip, and a shielding layer covering at least one portion of the first and/or second semiconductor chip and electrically connected to the first through via.

Abstract: An IC package which can avoid electromagnetic waves leaked from a side surface of the IC package includes: an electric circuit board on which an IC chip is mounted; a first conductive board arranged at a position facing the electric circuit board while the IC chip on the electric circuit board is sandwiched therebetween; and a magnetic body which is arranged on a surface of the first conductive board on a side facing the IC chip and which is arranged at least partially on end portions of the first conductive board.

Abstract: The present invention reduces the occurrence of fracture in external terminal connecting sections and improves the reliability of secondary packaging of a semiconductor device. Specifically, the present invention provides a semiconductor device including a wiring board, a semiconductor chip mounted on one surface of the wiring board via a bonding member, and external electrodes formed on the other surface of the wiring board and electrically connected to the semiconductor chip. In the semiconductor device, a peripheral end of the bonding member is arranged in a position where the peripheral end does not overlap the external electrodes.

Abstract: A pallet (501) supporting a half-etched leadframe with cantilever-type leads (403) without metallic supports during the step of attaching components (510) to the leads in order to assemble an electronic system. After assembly, the pallet is removed before the molding step that encapsulates (601a) the components on the leadframe and mechanically supports (601b) the cantilever leads. The pallet is machined from metal or inert plastic material, tolerates elevated temperatures during soldering, and is reusable for the next assembly batch.

Abstract: Embodiments of the invention relate to a method for creating a flexible circuit, including defining a cavity in a top surface of a substrate before disposing a semiconductor chip within the cavity, such that a backside of the chip is disposed beneath the top surface of the substrate and above a bottom surface of the cavity. The method also includes forming a flexible connecting layer on the top surface of the substrate and extending over the chip. Other embodiments relate to a flexible circuit including a substrate defining a cavity in a top surface thereof. The cavity has encapsulant and a chip disposed therein, wherein a frontside of the chip is substantially coplanar with the top surface of the substrate. A flexible connecting layer is disposed on the top surface of the substrate and is partially supported by the substrate.

Abstract: An integrated circuit (IC) device arrangement includes a substrate, an IC die coupled to the substrate, an antenna coupled to the IC die, and a first wirelessly enabled functional block coupled to the IC die. The wirelessly enabled functional block is configured to wirelessly communicate with a second wirelessly enabled functional block coupled to the substrate. The antenna is configured to communicate with another antenna coupled to another device.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Abstract: An electronic component device includes a substrate, an electrode post made of a metal material, provide to stand on the substrate, and an electronic component whose connection electrode is connected to the electrode post, wherein the connection electrode of the electronic component and the electrode post are joined by an alloy layer including a metal which is different from the metal material of the electrode post.

Abstract: A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Abstract: Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side.

Abstract: A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

Abstract: The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of: forming and curing a first protective layer to cover a plurality of first bumps of a first wafer; cutting the first wafer to form a plurality of first dice; forming a third protective layer to cover a plurality of second bumps of a second wafer; picking up the first dice through the first protective layer, and bonding the first dice to the second wafer; removing part of the first protective layer; cutting the second wafer to form a plurality of second dice; and bonding the first dice and the second dice to a substrate. Whereby, the first protective layer can protect the first bumps, and the first protective layer can increase the total thickness and the flatness.

Abstract: A semiconductor device includes an insulating film base member and a wiring pattern that is formed on the insulating film base member. The wiring pattern has a surface, with at least a peripheral section of the surface being a peeled surface of the wiring pattern peeled from the insulating film base member. The semiconductor device further includes a plating layer that covers the surface of the wiring pattern, and an IC chip that has an active surface with a bump bonded to the wiring pattern. The peeled surface of the wiring pattern is peeled from the insulating film base member around a bonding position of the wiring pattern bonded with the bump.

Abstract: The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process.

Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Abstract: A semiconductor device according to this embodiment has an electrode (electrode pad) and an insulative film (protective resin film) formed on the electrode and having an opening for exposing the electrode. The semiconductor device further has an under bump metal (UBM layer) formed over the insulative film and connected with the electrode through the opening, and a solder ball formed over the under bump metal, and the contour line at the lower end of the solder ball is situated inside the contour line of the under bump metal, whereby generation of fracture in the insulative film caused by the stress upon mounting the semiconductor device is suppressed even when the solder ball is formed of a lead-free solder.

Abstract: In one embodiment, a semiconductor device includes a plurality of semiconductor chip stacks mounted on a substrate. Bonding terminals disposed on the substrate correspond to the chip stacks, such that at least one chip in each chip stack may be directly connected to a bonding terminal on the substrate and at least one chip in the chip stack is not directly connected to the bonding terminal. The semiconductor chip stacks may each act as one semiconductor device to the outside.

Abstract: A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Abstract: A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Abstract: A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface opposite to the first main surface. An electrically insulating material is deposited on the first main surface of the semiconductor chip using a plasma deposition method. A first electrically conductive material is deposited on the second main surface of the semiconductor chip using a plasma deposition method.

Abstract: A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

Abstract: The present invention relates to a semiconductor element having conductive vias and a semiconductor package having a semiconductor element with conductive vias and a method for making the same. The semiconductor element having conductive vias includes a silicon substrate and at least one conductive via. The thickness of the silicon substrate is substantially in a range from 75 to 150 ?m. The conductive via includes a first insulation layer and a conductive metal, and the thickness of the first insulation layer is substantially in a range from 5 to 19 ?m. Using the semiconductor element and the semiconductor package of the present invention, the electrical connection between the conductive via and the other element can be ensured, and the electrical connection between the silicon substrate and the other semiconductor element can be ensured, so as to raise the yield rate of a product.

Abstract: Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles.

Abstract: A semiconductor device includes: a semiconductor chip with a plurality of electrode pads disposed at a top surface thereof; a plurality of thin film terminals set apart from one another via respective separator portions, which are located below a bottom surface of the semiconductor chip; an insulating layer disposed between the semiconductor chip and the thin-film terminals; connecting members that connect the electrode pads at the semiconductor chip with the thin-film terminals respectively and a resin layer disposed so as to cover the semiconductor chip, the plurality of thin-film terminals exposed at the semiconductor chip, the separator portions and the connecting members.

Abstract: A method of forming patterns of a semiconductor device comprises forming a number of first insulating patterns that define sidewalls by patterning a first insulating layer formed over a semiconductor substrate, forming second insulating patterns, each second insulating pattern comprising a horizontal portion having two ends and being parallel to the semiconductor substrate and spaced protruding portions protruding from both ends of the horizontal portion parallel to the sidewalls of the first insulating patterns, forming third insulating patterns each filling a space between the protruding portions, removing the protruding portions to form trenches, and forming conductive patterns within the respective trenches.

Abstract: In various embodiments, an electronic module features a first cavity in a first side of a substrate, a fill hole extending from the first cavity, and a second cavity in a second side of the substrate. The second cavity is in fluidic communication with the fill hole, and a die is encapsulated within the second cavity.

Abstract: An aeration apparatus is immersed in diluted used seawater which is water to be treated and generates fine air bubbles in the diluted used seawater. The aeration apparatus includes: an air supply line L5 having branch pipes L5A to L5H for supplying air 122 through blowers 121A to 121D serving as discharge unit; aeration nozzles 123 including diffuser membranes 11 having slits, through which the air 122 is supplied to the aeration nozzles 123 via headers 15 of the branch pipes L5A to L5H; a water tank 140 and a supply pump P1 that are used as water introducing unit for supplying water 141 to the air supply line L5. When pressure loss of the aeration nozzles 123 increases, the aeration apparatus stops introduction of the air 122 and supplies the water 141 into the branch pipes L5A to L5H branched from the air supply line L5.

Abstract: A method for generating and dissolving nano-bubbles in a liquid comprises the steps of preparing a bamboo filter by partially or entirely removing an enamel layer of a bamboo and using a bamboo fibrous layer therein as a component of a filter; applying a gas to an inside of the bamboo filter with a pressure over atmospheric pressure in a state where the bamboo filter is submerged in water; and making the gas permeate from an inside of the bamboo fibrous layer to an outside thereof, thereby forming nano-bubbles and at the same time dissolving the gas in the liquid. The present invention advantageously allows the generation of nano-sized fine bubbles by a filter member made of naturally occurring material so that the nano-bubbles are dissolved in a liquid, without applying external mechanical force to the water.

Abstract: An aspect of the present invention relates to a method of manufacturing a formed article forming an upper surface of a forming material comprised of a thermosoftening substance into a desired shape by heating the forming material in a state where the forming material is positioned on a forming surface of a forming mold to a temperature permitting deformation of the forming material to bring a lower surface of the forming material into tight contact with the forming surface. The heating is conducted by positioning the forming mold, on which the forming material has been positioned, beneath heat source(s) radiating radiant heat in a state where a plate-shaped member the outermost surface of which is comprised of a metal material is positioned above the upper surface of the forming material.

Abstract: A porous material having controlled void dimensions and method of forming the same includes forming an aerogel precursor, the aerogel precursor including a matrix material and a liquid dispersion medium for dispersing the matrix material. A plurality of particles having preselected dimensions is dispersed in the aerogel precursor. The aerogel precursor with the particles dispersed therein is frozen so that the liquid dispersion is solidified. The aerogel precursor is freeze dried to sublime the dispersion medium and form the porous material.

Abstract: A manufacturing method for a tampon having an absorbent body that absorbs liquid includes obtaining the absorbent body by compressing and shaping an absorbent-body material, and applying a melted agent to an outer surface of the absorbent body, the outer surface having a temperature lower than or equal to a freezing point of a main ingredient of the agent.

Abstract: In a method of making multi-component plastic molded parts, using an apparatus which includes two outer platens with first half-molds, and a middle platen with second half-molds interacting with the first half-molds such as to define cavities in two parting planes for injection of a plastic melt and/or a PUR mixture, one of the first and second half-molds can move in increments relative to the other one of the first and second half-molds, thereby forming different cavities in the parting planes from cycle to cycle. In a first cycle preforms are produced in respective cavities and then held in one of the first and second half-molds as the other one of the first and second half-molds moves in increments. Further components can then be injected into cavities formed in the parting planes from cycle to cycle, while another process step can be executed from cycle to cycle in free half-molds.

Abstract: The present invention is a system including: an imprint unit transferring a transfer pattern to a coating film on a substrate using a template to form a predetermined pattern in the coating film; a treatment station connected to the imprint unit and performing a predetermined treatment on the template; a template carry-in/out station connected to the treatment station, capable of keeping templates, and carrying the template in/out from/to the treatment station; a carry line provided through the imprint unit and carrying the template between the imprint unit and the treatment station; and a substrate carry-in/out station connected to the imprint unit, capable of keeping substrates, and carrying the substrate in/out from/to the imprint unit.

Abstract: The invention relates to an optical thread position detection device (1) for detecting the rotational position of threads (2) of containers (3). The thread position detection device (1) comprises at least an optical detector (4a, 4b) and a positioning device (6) for the defined orientation of a longitudinal axis (L) of the containers (3) relative to the detector (4a,b), the positioning device (6) and a defined coupling area (8a,b,c) of the container (3) being connectable to one another. According to the invention the optical detector (4a,b), without coming into contact, registers items of information on at least one relative rotational position of at least one thread portion (2a), the processor device serving to generate data on the rotational position of the container, incorporating a defined reference variable and the items of information.

Abstract: An apparatus for forming molded edges on opposite sides of a load bearing surface including a stretching assembly integrated into a molding assembly. The stretching assembly may include localized fabric clamps that leave the center region of the fabric free (e.g. not clamped) through the process. The clamps may be arranged so that once extended to stretch the fabric, the fabric is held by the clamps in the appropriate position for molding. The fabric may be held so that opposed edges terminate in the mold cavities. The mold parts may cooperatively define two spaced apart mold cavities, and may include a mold pocket to provide space to store excess fabric. The fabric may be held against the surface of the mold cavity during the molding process, for example, using hold-down pins and special gate configurations. The molding apparatus may include an alternative stretching assembly configured to provide different amounts of stretch to different portions of the fabric blank.

Abstract: A method of manufacturing a sheet includes: rotating in a circumferential direction, a first roll having a protruding portion group, and a second roll opposing the first roll and having a region with the different flexibility property; and sandwiching the sheet with the protruding portion group and the outer circumferential face of the second roll. The protruding portion group has a plurality of rows of protruding portion rows with intervals therebetween in the circumferential direction. Each of the protruding portion rows includes a plurality of protruding portions aligned along a rotational axis direction of the first roll. A position of a downstream end in the circumferential direction of at least one protruding portion of the protruding portions positioned most downstream of the protruding portion group in the circumferential direction is arranged shifted from a position of a downstream end of another protruding portion configuring the protruding portion row.