Abstract: A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer.

Abstract: Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof.

Abstract: There is provided a method that allows semiconductor chips to be obtained from a semiconductor wafer at high yield, while sufficiently inhibiting generation of chip cracks and burrs. The method for manufacturing a semiconductor chip comprises a step of preparing a laminated body having a semiconductor wafer, an adhesive film for a semiconductor and dicing tape laminated in that order, the semiconductor wafer being partitioned into multiple semiconductor chips and notches being formed from the semiconductor wafer side so that at least a portion of the adhesive film for a semiconductor remains uncut in its thickness direction, and a step of stretching out the dicing tape in a direction so that the multiple semiconductor chips are separated apart, to separate the adhesive film for a semiconductor along the notches. The adhesive film for a semiconductor has a tensile breaking elongation of less than 5% and the tensile breaking elongation of less than 110% of the elongation at maximum load.

Abstract: Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.

Abstract: A doping method for a semiconductor device includes forming a trench in a semiconductor substrate, forming a doped layer doped with a dopant over the undoped layer, and forming a doped region into which the dopant is diffused, wherein the doped region is a portion of the semiconductor substrate in contact with the doped layer.

Abstract: In a replacement gate approach in sophisticated semiconductor devices, the place-holder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.

Abstract: The present invention provides a manufacturing method of a dielectric film which reduces a leak current value while suppressing the reduction of a relative permittivity, suppresses the reduction of a deposition rate caused by the reduction of a sputtering rate, and also provides excellent planar uniformity. A dielectric film manufacturing method according to an embodiment of the present invention is forms a dielectric film of a metal oxide mainly containing Al, Si, and O on a substrate, and comprises steps of forming the metal oxide having an amorphous structure in which a molar fraction between an Al element and a Si element, Si/(Si+Al), is 0<Si/(Si+Al)?0.1, and subjecting the metal oxide having the amorphous structure to annealing treatment at a temperature of 1000° C. or more to form the metal oxide including a crystalline phase.

Abstract: Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

Abstract: A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming an interlayer over the first Si layer; forming a second Si layer including Ge over the interlayer; wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.

Abstract: A bonding process includes the following process. A bump is formed on a first electric device. A patterned insulation layer is formed on a second electric device, wherein the patterned insulation layer has a thickness between 5 ?m and 400 ?m, and an opening is in the patterned insulation layer and exposes the second electric device. The bump is joined to the second electric device exposed by the opening in the patterned insulation layer.

Abstract: A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Abstract: A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.

Abstract: An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.

Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

Abstract: A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure.

Abstract: A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist film on the dielectric film, performing a lithography process using the measured thickness of the dielectric film to form a photoresist film pattern, and etching the dielectric film and the film to be etched using the photoresist film pattern.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Abstract: An image sensor package and a method for fabricating thereof are provided. A substrate having an insulator filled cavity is provided with an image sensor device electrical connected to a metal layer, thereon. A covering plate is then disposed on the substrate. The substrate is subsequently thinned to expose the insulator. Removing a portion of the insulator, a hole is formed and a conductive layer is filled therein to form a via hole. Next, a solder ball is located over a backside of the substrate which is electrically connected to the metal layer through the via hole. The image sensor package is thinned, thus, the dimensions thereof are reduced.

Abstract: A method of manufacturing a memory device is disclosed. The method includes providing a substrate, forming a number of memory sectors on the substrate, wherein each of the memory sectors is coupled to an adjacent one via a first diffused region in the substrate and is coupled to another adjacent one via at least one second diffused region in the substrate, forming a first dielectric layer on the memory sectors, forming a first conductive structure through the first dielectric layer to the first diffused region, and at least one second conductive structure through the first dielectric layer to the at least one second diffused region, forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure, and etching back the first conductive structure.

Abstract: Embodiments of the present invention provide a method of forming borderless contact for transistor. The method may include forming a gate of a transistor, on top of a substrate, and spacers adjacent to sidewalls of the gate; forming a sacrificial layer surrounding the gate; causing the sacrificial layer to expand in height to become higher than the gate, the expanded sacrificial layer covering at most a portion of a top surface of the spacers and thereby leaving an opening on top of the gate surrounded by the spacers; filling the opening with a dielectric cap layer; replacing the expanded sacrificial layer with a dielectric layer; and forming a conductive stud contacting source/drain of the transistor, the conductive stud being isolated from the gate by the dielectric cap layer.

Abstract: Methods of manufacturing a honeycomb extrusion die comprise the steps of coating at least a portion of a die body with a layer of conductive material and modifying the die body with an electrical discharge machining technique. The method then further includes the step of chemically removing the layer of conductive material, wherein the residual material from the electrical discharge machining technique is released from the die body.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.

Abstract: A chemical mechanical polishing composition, comprising, as initial components: water; 0.1 to 40 wt % abrasive having an average particle size of 5 to 150 nm; 0.001 to 1 wt % of an adamantyl substance according to formula (II); 0 to 1 wt % diquaternary substance according to formula (I); and, 0 to 1 wt % of a quaternary ammonium compound. Also, provided is a method for chemical mechanical polishing using the chemical mechanical polishing composition.

Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.

Abstract: A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device

Abstract: Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature.

Abstract: An apparatus for adaptive self-aligned dual patterning and method thereof. The method includes providing a substrate to a processing platform configured to perform an etch process and a deposition process and a metrology unit configured for in-vacuo critical dimension (CD) measurement. The in-vacuo CD measurement is utilized for feedforward adaptive control of the process sequence processing platform or for feedback and feedforward adaptive control of chamber process parameters. In one aspect, a first layer of a multi-layered masking stack is etched to form a template mask, an in-vacuo CD measurement of the template mask is made, and a spacer is formed, adjacent to the template mask, to a width that is dependent on the CD measurement of the template mask.

Abstract: A method for manufacturing a semiconductor device includes: a first etching step of etching a TEOS layer from a glass substrate to partially expose a SiN layer; a second etching step, conducted separately and independently from the first etching step, of wet-etching the exposed SiN layer to partially expose the glass substrate; and a bonding step of bonding a driver portion to the exposed glass substrate.

Abstract: A liquid crystal display device includes a plurality of gate lines and data lines crossing each other to define a plurality of pixel regions, a plurality of thin film transistors, each disposed in one of the pixel regions, and a plurality of pixel electrodes, each disposed in one of the pixel regions, wherein the thin film transistor includes at least one Ti layer.

Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Abstract: Provided are a semiconductor manufacturing apparatus and method, capable of reliably and rapidly transporting a heated semiconductor wafer. the apparatus is provided for transporting a semiconductor wafer, which has been processed by desired treatment (for example, film formation) and is held by a susceptor equipped with a heater, to the outside by a transport arm which holds the semiconductor wafer by suction, by moving the susceptor to a certain position above a top of a wafer waiting stage and introducing the semiconductor wafer held by the susceptor onto the top of the wafer waiting stage. Then, the susceptor present on the top of the wafer waiting stage is moved in a horizontal direction. After a certain cooling time, the transport arm holds the semiconductor wafer placed on the wafer waiting stage by suction and transports the semiconductor wafer to outside.

Abstract: A method of manufacturing a semiconductor device has supplying a first reactant gas into buffer chamber provided in a reaction chamber of the film deposition apparatus to form a first film over an inner wall surface of the buffer chamber, and supplying a second reactant gas into the reaction chamber to form a second film over a semiconductor substrate.

Abstract: A glass that is ion exchangeable to a depth of at least 20 ?m (microns) and has a internal region having a tension of less than or equal to 100 MPa. The glass is quenched or fast cooled from a first temperature above the anneal point of the glass to a second temperature that is below the strain point of the glass. In one embodiment, the glass is a silicate glass, such as an alkali silicate glass, an alkali aluminosilicate glass, an aluminosilicate glass, a borosilicate glass, an alkali aluminogermanate glass, an alkali germanate glass, an alkali gallogermanate glass, and combinations thereof.

Abstract: The present invention relates to a dielectric ceramic composition comprises a main component including a dielectric oxide having a composition shown by [(Ca1-xSrx)O]m[(Zr1-y-z-?TiyHf2Mn?)O2], note that, 0.991?m?1.010, 0?x?1, 0?y?0.1, 0<z?0.02, 0.002<??0.05), 0.1 to 0.5 parts by mol of Al2O3 and 0.5 to 5.0 parts by mol of SiO2 with respect to 100 parts by mol of the main component. A purpose of the present invention is to provide a dielectric ceramic composition available to prevent the occurrence of crack even when a dielectric layer is made thin, for example, 2 ?m or less, while maintaining various advantageous properties of a dielectric ceramic composition of [(CaSr)O]m[(TiZrHf)O2] type.

Abstract: The present invention relates to a method for producing an artificial lightweight aggregate containing bottom ash. The method includes the steps of: (a) mixing 100 parts by weight of clay and 10-100 parts by weight of bottom ash to obtain a mixture; (b) extrusion-molding the mixture by using an extruder and cutting the extrusion-molded mixture to form a molded article; (c) drying the molded article by using a rotary drier; and (d) sintering the dried article at 1050-1150° C. for 15-45 minutes to produce the artificial lightweight aggregate. The aggregate produced according to the invention is lightweight, cost-effective, and has uniform water absorption.

Abstract: A metal nanodot material is formed by ion-exchange with chabazite or a chabazite-like structure, followed by activation to form metallic nanodots. The nanodot may be formed from silver, nickel, copper, gold or a platinum group metal.

Abstract: A catalyst composition comprises the reaction product of an alkoxide or condensed alkoxide of a metal M, selected from titanium, zirconium, hafnium, aluminum, or a lanthanide, an alcohol containing at least two hydroxyl groups, a 2-hydroxy carboxylic acid and a base, wherein the ratio of equivalents of base to —COOH acid equivalents of said 2-hydroxy carboxylic acid is in the range 0.0033-0.2:1. The composition is useful as a catalyst for esterification reactions, especially for the production of polyesters such as polyethylene terephthalate, polytrimethylene terephthalate and polybutylene terephthalate.

Abstract: The present invention relates to a method for recovering N,N,N?-trimethylbisaminoethylether from a mixture with its amide and a method for separating N,N,N?-trimethylbisaminoethylether from mixtures comprising tertiary amines or tertiary aminoalkylether as well as a composition comprising a mixture of N,N,N?-trimethylbisaminoethylether and a transamidation agent.

Abstract: Methods for preparing catalysts for oxidation of unsaturated and/or saturated aldehydes to unsaturated acids is disclosed where the catalyst includes at least molybdenum (Mo), phosphorus (P), vanadium (V), bismuth (Bi), where the bismuth component was dissolved in an organic acid solution prior to adding the bismuth containing solution to a solution of the other components.

Abstract: A process for the production of low-temperature activated or partially activated partially decomposed organic matter for use as an ion-exchange medium comprising the steps of granulating partially decomposed moisture-bearing organic matter, drying the granules and activating the granules at a temperature of about 175-520° C., wherein the granule has a hardness and cation-exchange capacity suitable for a particular application desired.

Abstract: The invention relates to a method for producing activated carbon, in particular spherical activated carbon, wherein particles are carbonized from an organic precursor substance, wherein the activated carbon obtained from the particles is shock-chilled after carbonization, the temperature gradient being more than 100 K/min.

Abstract: A honeycomb structured body of the present invention is a honeycomb structured body in which plural pillar-shaped honeycomb units are bonded to one another through sealing material layers, each unit having in the longitudinal direction a large number of cells placed in parallel with a cell wall therebetween. Herein, a cross-sectional area of the honeycomb unit on a cross-section perpendicular to the length direction is at least about 5 cm2 and at most about 50 cm2, the honeycomb unit includes inorganic fibers and/or whiskers in addition to inorganic particles, and a Young's modulus of the honeycomb unit is at least about 50% and at most about 150% of a Young's modulus of the sealing material layer.

Abstract: The present invention is directed to increasing the efficacy of agricultural chemicals. This can be achieved by applying at least one agricultural chemical to a plant or plant seed under conditions effective for the agricultural chemical to perform its intended function and applying at least one hypersensitive response elicitor protein or polypeptide to the plant or plant seed under conditions effective to increase the efficacy of the agricultural chemical. Alternatively, the present invention relates to a method for increasing the efficacy of agricultural chemicals by applying an agricultural chemical to a transgenic plants or transgenic seeds transformed with nucleic acid molecule which encodes a hypersensitive response elicitor protein or polypeptide, wherein the agricultural chemical is applied under conditions effective for the agricultural chemical to perform its intended function but with increased efficacy.

Abstract: The present invention generally relates to aqueous seed treatment formulations comprising a pesticidal agent, a polyvinyl alcohol (PVA), a graft copolymer, and a plasticizer. In one embodiment of the invention, PVA-compatible polymer emulsions are employed. The present invention also relates to uses of the disclosed compositions for protecting seeds from pests.

Abstract: The invention pertains to a method for manufacture and use of a herbicidal formulation of chlorinated carboxylic acid herbicides. A number of different solvents have been found useful in this application. Furthermore, the use of surfactants that act as solvents for the acid herbicides has been discovered. These formulations have shown superior herbicidal activity when compared to standard salt and ester forms.

Abstract: A stabilized herbicidal composition, comprising a fenoxaprop ester herbicide, a salt of 2,4-D, a salt of MCPP-P and a salt of Dicamba, which may also optionally contain additional stabilizers such as triethylamine. Also disclosed is a stabilized herbicidal composition comprising a fenoxaprop ester herbicide in combination with a bromoxynil mixed ester herbicide. The stabilized herbicidal compositions of the present invention may also contain one or more surfactants and/or safeners.

Abstract: An oxide target for laser vapor deposition, which is used when an oxide film is formed in a laser vapor deposition system, including: a fixed plate, an Ag-soldering layer bonded onto the fixed plate, an oxide-Ag mixed layer bonded onto the Ag-soldering layer; and an oxide layer bonded onto the oxide-Ag mixed layer.