Patents Issued in July 31, 2012
  • Patent number: 8232786
    Abstract: A method of controlling a power converter having at least one switching device for supplying an output voltage and a load current to a load is disclosed. The method includes sensing the output voltage and sensing the load current. The method further includes controlling a duty cycle of the switching device according to the sensed output voltage and a voltage control loop when a rate of change of the load current does not exceed a threshold level. The method also includes adjusting the duty cycle of the switching device set by the voltage control loop when the rate of change of the load current exceeds the threshold level.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: July 31, 2012
    Assignee: Astec International Limited
    Inventors: Vijay G. Phadke, Arlaindo V. Asuncion, Evan M. Espina, Yancy F. Boncato
  • Patent number: 8232787
    Abstract: An apparatus for monitoring the pulse time of switches within a DC to DC power supply, comprising a timing circuit responsive to a switching confirmation signal to commence timing and to monitor for control signals being sent to the switch and to indicate whether elapsed period between the switching confirmation signal and the control signal is too long or too short.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: July 31, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Guillaume De Cremoux
  • Patent number: 8232788
    Abstract: A controller for a voltage regulator includes a hysteretic circuit that generates a hysteretic voltage output as a function of a regulated voltage and that generates a hysteretic current output as a function of an inductor current. A switch control circuit provides a quasi-continuous control output as a function of the hysteretic current output from a start time when the regulated voltage rises above a higher hysteretic voltage until a stop time when the regulated voltage falls below a lower hysteretic voltage.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: July 31, 2012
    Assignee: Seagate Technology LLC
    Inventors: Brian Dean Boling, Tuan Van Tran
  • Patent number: 8232789
    Abstract: A voltage regulator, comprises first circuitry for generating an output voltage responsive to an input voltage and a plurality of switching control signal. Switching control circuitry generates the switching control signals responsive to the output voltage and at least one of a buck ramp signal and a boost ramp signal. Voltage ramp generation circuitry generates each of the buck ramp signal and the boost ramp signal. The boost ramp signal comprises the buck ramp signal offset by the peak value of the buck ramp signal.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: July 31, 2012
    Assignee: Intersil Americas LLC
    Inventor: Zaki Moussaoui
  • Patent number: 8232790
    Abstract: A dual supply circuit uses a dual feedback control, single inductor, dual polarity boost architecture with a low side power FET for end of current recirculation sensing. A dual feedback system tracks the output voltage variations and a low side power FET end of current recirculation sensing utilizes the internal current limit sensing system. Logic defining the state of operations allows the regulator to operate in both single and dual mode to cater to wide application ranges. The positive boost regulator can be operated in a buck mode making the output voltage constant with high input supply.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: July 31, 2012
    Assignee: STMicroelectronics Asia Pacific Pte Ltd.
    Inventors: Kong Yin Leong, Soon Hwei Tan
  • Patent number: 8232791
    Abstract: A driver includes a boost converter, a pulse width modulator controlling the boost converter, and a timer controlling the pulse width modulator. The timer, such as a digital counter, causes the pulse width modulator to produce narrow pulses unless or until the end of a period is reached, at which point the pulse width modulator is not controlled by the timer.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: July 31, 2012
    Assignee: World Properties, Inc.
    Inventors: Harold Gee Yee, Douglas James Andersn
  • Patent number: 8232792
    Abstract: A system and method for controlling the output voltage of a power supply that includes a control section and an interconnect section having an output point. A voltage regulator provides a control section voltage, and a current measurement device measures a control section current and generates a current signal. A controller receives the current signal and a voltage command signal representing a desired output voltage at the output point of the interconnect section. The controller generates an adjusted voltage command signal based on the voltage command signal representing the desired output voltage, the current signal, a control section internal resistance and an interconnect section external resistance. The voltage regulator receives the adjusted voltage command signal and provides a control section voltage based thereon in order to supply an output voltage at the output point that is substantially equal to the desired output voltage.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: July 31, 2012
    Assignee: Lear Corporation
    Inventors: Richard Hampo, Benjamin D. Sweet
  • Patent number: 8232793
    Abstract: Embodiments of the subject invention relate to a method and apparatus for determining information regarding a load in a planar wireless power transfer system by extracting system operating parameters from one or more test points in the transmitter circuit. As shown in FIG. 1, a specific embodiment showing three test points in the transmitter circuit from which operating parameters can be extracted. The transmitter circuit is designed to produce a magnetic field, by driving the transmitter coil, which inductively couples to a receiver coil such that power is provided to a receiver. By extracting operating parameters from the transmitter circuit, the receiver does not need to incorporate sophisticated signal processing and can be manufactured with low cost.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 31, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Jenshan Lin, Zhen Ning Low
  • Patent number: 8232794
    Abstract: A rotation angle detector for detecting the rotation angle of a rotator to be measured which detects the flux density, generated depending on rotation of the rotator to be measured, of a ring-like magnet fixed to the rotator by means of a magnetic detection element. Since a soft magnetic member is interposed between the ring-like magnet and the rotator, rotation angle of the rotator can be measured accurately without being affected by the material or diameter of the rotator or the fixing state of the rotation angle detector to the rotator. Consequently, a rotation angle detector for detecting the rotation angle of a rotator to be measured accurately without being affected by the material or diameter of the rotator or the fixing state of the rotation angle detector to the rotator is presented.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: July 31, 2012
    Assignee: The Furukawa Electric Co., Ltd
    Inventors: Fumihiko Abe, Kengo Tanaka, Dongzhi Jin
  • Patent number: 8232795
    Abstract: A magnetic sensor includes a first detection unit and a second detection unit. The first detection unit calculates a first detection angle which is a detected value of a first angle that a direction of an external magnetic field in a first position forms with respect to a first direction. The second detection unit calculates a second detection angle which is a detected value of a second angle that the direction of the external magnetic field in a second position forms with respect to a second direction. The first detection angle includes a first angular error. The second detection angle includes a second angular error. The first angular error and the second angular error differ in phase by an odd number of times ½ of the error period.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: July 31, 2012
    Assignee: TDK Corporation
    Inventors: Shunji Saruki, Hiraku Hirabayashi
  • Patent number: 8232796
    Abstract: A conduit sensor device includes first and second pairs of permanent magnets. First and second rotor shunts include first and second rotatable magnets and interposed between the first and second pairs of permanent magnets, respectively. A shunt shaft includes a first helical worm gear and a second helical worm gear mounted thereon. The first rotor shunt includes a first rotatable magnet and a first rotor gear locked together. The first helical worm gear meshing with the first rotor gear driving the first rotor gear and the first rotatable magnet. The second rotor shunt includes a second rotatable magnet and a second rotor gear locked together. The second helical worm gear meshes with the second rotor gear driving the second rotor gear and the second rotatable magnet. The surface areas of the first and second pairs of permanent magnets equals the surface area of the first and second rotatable magnets.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: July 31, 2012
    Assignee: Invodane Engineering Ltd
    Inventors: Paul Laursen, Corry Comello, Roderick Lee
  • Patent number: 8232797
    Abstract: A device with separate emission/reception functions for making eddy current tests on an electrically conducting part comprising several emission rows (1-4) composed of emission windings (55), and several reception columns (a-h) each composed of reception windings (56) connected in series in at least one series, in which the emission windings associated with the reception windings in one series are powered by currents at different frequencies.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: July 31, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Jean-Marc Decitre
  • Patent number: 8232798
    Abstract: A magnetic tracking system is particularly adapted for a combination with an imaging system, for example with a rotational X ray device. The magnetic tracking system includes pairs of first and second field generators that are disposed on opposite sides of a measuring volume. The first field generators may particularly be attached to a radiation source and the second field generators to a detector of the X ray device. Moreover, the first and second field generators may be constituted by coils with opposite magnetic polarity. Due to the attachment of the field generators to the X ray device, motions of the X ray device do not disturb the magnetic field in a frame of reference fixed to the imaging system.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: July 31, 2012
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Sascha Krueger, Hans-Aloys Wischmann
  • Patent number: 8232799
    Abstract: This document describes a general system for noise reduction, as well as a specific system for Magnetic Resonance Imaging (MRI) and Nuclear Quadrupole Resonance (NQR). The general system, which is called Calculated Readout by Spectral Parallelism (CRISP), involves reconstruction and recombination of frequency-limited broadband data using separate narrowband data channels to create images or signal profiles. A multi-channel CRISP system can perform this separation using (1) frequency tuned hardware, (2) a frequency filter-bank (or equivalent), or (3) a combination of implementations (1) and (2). This system significantly reduces what we call cross-frequency noise, thereby increasing signal-to-noise-ratio (SNR). A multi-channel CRISP system applicable to MRI and NQR are described.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: July 31, 2012
    Assignee: Arjae Spectral Enterprises
    Inventors: Arsen R. Hajian, Jae K. Kim
  • Patent number: 8232800
    Abstract: Disclosed are a high-order generalized series parallel imaging method for acquiring high spatio-temporal resolution functional magnetic resonance images and a sampling method. The higher-order generalized series parallel imaging method for acquiring high spatio-temporal resolution functional magnetic resonance images includes: performing sampling of an input image in k-space; applying a high-order generalized series (HGS) reconstruction procedure to data acquired as the sampling result to acquire a first reconstructed image; and applying a parallel magnetic resonance reconstruction procedure to the first reconstructed image to acquire a second reconstructed image.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: July 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HyunWook Park, SungDae Yun
  • Patent number: 8232801
    Abstract: Structural health monitoring using nuclear quadrupole resonance is disclosed. For example, in one embodiment, a method of monitoring stress is provided. The method includes scanning a composite using an NQR spectrometer, the composite having a polymer matrix and a microcrystalline material disposed in the matrix. The microcrystalline material includes molecules having nuclei with respective nuclear quadrupole moments. The method also includes determining microscopic strain distribution indices of the composite from the NQR scans to quantify stress and identify precursors to failure in the composite.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 31, 2012
    Assignee: General Electric Company
    Inventors: Nilesh Tralshawala, Thomas Alan Early, William Thomas Dixon, Waseem Ibrahim Faidi, Thomas Miebach
  • Patent number: 8232802
    Abstract: A radio frequency coil assembly is provided that includes a first radio frequency coil for receiving a magnetic resonance signal from a tested body; a second radio frequency coil for receiving a magnetic resonance signal from the tested body; and a third radio frequency coil for receiving a magnetic resonance signal from the tested body and having a shape that is different from that of at least one of the first and second radio frequency coils so as to increase local sensitivity in an image-picked-up region.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 31, 2012
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventors: Kazuya Okamoto, Shinji Mitsui, Manabu Ishii
  • Patent number: 8232803
    Abstract: A tool 1 is used in electrical investigation of geological formations GF surrounding a borehole BH. The tool 1 is comprised in a string of tools TS. The tool 1 comprises a current injection section CIS and a current return section CRS. The string of tools TS comprises at least one other section OS1. The current injection section CIS is electrically decoupled from the current return section CRS. The current injection section CIS is electrically decoupled from the at least one other section OS1 when the current injection section CIS and the at least one other section OS1 are adjacent to each other. The current return section CRS is electrically decoupled from the at least one other section OS1 when the current return section CRS and the at least one other section OS1 are adjacent to each other.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: July 31, 2012
    Assignee: Schlumberger Technology Corporation
    Inventor: Richard Bloemenkamp
  • Patent number: 8232804
    Abstract: This invention relates to a time alert device (1) for use with an earth leakage protection device comprising a microprocessor system (10) provided with a software controlled alert trigger timer (22). On time out of the alert trigger timer, the microprocessor system (10) initiates an audible and/or visual annunciation to remind the user of the earth leakage protection device to perform integrity test on the earth leakage protection device. If the earth leakage protection device fails the integrity test, the user detects that the earth leakage protection device could be faulty and needs expert attention. If the earth leakage device passes the integrity test, the alert trigger timer is reset for another predetermined time interval to remind the user to perform another integrity test on the earth leakage protection device. The time alert device can be further provided with a message display panel.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: July 31, 2012
    Inventor: See Ni Fong
  • Patent number: 8232805
    Abstract: A method is described for manufacturing a battery sensor unit, in particular a battery sensor unit for a motor vehicle battery, comprising a cable holder for a cable end of a cable. The method includes sliding a sleeve composed of a resistor material onto the cable end, at least one first measuring tap being installed between the cable end and an inner circumference of the sleeve. The cable end provided with the sleeve and the measuring tap is inserted into the cable holder and is permanently connected thereto to form a measuring device. A battery sensor unit is described having a fastening device for fastening the battery sensor unit to a contact of a battery, in particular a motor vehicle battery, and having a measuring device for detecting the state of the battery.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: July 31, 2012
    Assignee: Robert Bosch GmbH
    Inventor: Sergej Kerbel
  • Patent number: 8232806
    Abstract: An insulation state detector detects an insulation state with respect to a ground potential portion of a DC power source on the basis of a charging voltage of a flying capacitor. The insulation state connector includes a detecting section that detects the insulation state of the DC power source by defining the charging voltage of the flying capacitor in the ground fault state as a charging voltage, in an unbalanced state where voltages across both ends of the positive-side Y capacitor and the negative-side Y capacitor are not equal to voltages obtained by dividing the voltage of the DC power source according to a voltage division ratio of the positive-side ground fault resistor and the negative-side ground fault resistor.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 31, 2012
    Assignee: Yazaki Corporation
    Inventor: Yoshihiro Kawamura
  • Patent number: 8232807
    Abstract: A device for measuring and isolating noise-creating imbalances in a paired telecommunications line has an internal circuit. The internal circuit includes a pulse generator. Pulses provided by the pulse generator are applied to an interface which includes balanced pathways to the conductors. The pulses are applied simplex (longitudinally) to the pair of conductors. Upon encountering a fault in the pair, a reflected metallic voltage signal is received by the interface. The reflected metallic voltage signal is sampled by an analog-to-digital converter. Data relating to the sampled signal is displayed for detection and location of faults on the pair.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: July 31, 2012
    Assignee: Textron Innovations Inc.
    Inventors: Thomas W. Durston, Robert G. Crick
  • Patent number: 8232808
    Abstract: There is provided a switch circuit for switching whether to output an input signal, including: a transmission path that transmits the input signal from an input end to an output end of the switch circuit; a first semiconductor switch that is provided on the transmission path and switches whether to transmit the input signal; a second semiconductor switch that is opened when the first semiconductor switch is short-circuited, and that is short-circuited when the first semiconductor switch is opened, thereby grounding, to a ground potential, a high-frequency signal leaked to the transmission path between the first semiconductor switch and the output end; and a voltage controller that causes a potential difference on both ends of the second semiconductor switch when the second semiconductor switch is opened.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 31, 2012
    Assignee: Advantest Corporation
    Inventors: Hiroki Kimura, Chisato Maeda
  • Patent number: 8232809
    Abstract: Solutions for determining a critical current density of a line are disclosed. In one embodiment a method of determining a critical current density in a line includes: applying a temperature condition to each of a plurality of samples including the line; calculating a cross-sectional area of the line for each of the plurality samples using data about an electrical resistance of the line over each of the temperature conditions; measuring an electrical current reading through the line for each of the plurality of samples; determining a current density through the line for each of the plurality of samples by dividing each electrical current reading by each corresponding cross-sectional area; determining an electromigration (EM) failure time for each of the plurality of samples; and determining the critical current density of the line using the current density and the plurality of EM failure times.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chad M. Burke, Cathryn J. Christiansen, Baozhen Li
  • Patent number: 8232810
    Abstract: An input device is provided with improved electrostatic discharge protection. Specifically, the input device includes a plurality of capacitive sensing electrodes configured for object detection. An electrostatic discharge (ESD) shunt is disposed near the capacitive sensing electrodes and configured to provide ESD protection to the capacitive sensing electrodes. The input device also includes an extended-proximity capacitive sensing electrode configured to for object detection of relatively distant objects. The ESD shunt has an associated first resistance, and the extended-proximity capacitive sensing electrode has an associated second resistance.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: July 31, 2012
    Assignee: Synaptics Incorporated
    Inventors: Joseph Kurth Reynolds, Tracy Scott Dattalo
  • Patent number: 8232811
    Abstract: There is disclosed an electrostatic discharge (ESD) device tester and a method of operating the tester. In an embodiment, the method comprises operating the tester by uniquely identifying an ESD device to be tested using identification means provided on the tester; taking at least one test measurement of the uniquely identified ESD device using testing means provided on the tester, the testing means being configurable in dependence upon data associated with the uniquely identified ESD device; and storing the at least one test measurement in a storage means provided in the tester. A running average of test measurements for the uniquely identified ESD device may be stored on the tester in order to compare a test measurement against the running average. A test is repeated if a test measurement falls outside of a predetermined range of the running average.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 31, 2012
    Assignee: Research In Motion Limited
    Inventor: Roger Enta
  • Patent number: 8232812
    Abstract: The present invention discloses a process for determining which material within a vicinity of an electrically conducting material is causing corrosion of the electrically conducting material. The process includes providing a piece of electrically conducting material, a piece of potentially corrosive material that is present in the vicinity of the electrically conducting material, an electrical resistance measuring device and a testing chamber. Thereafter, the piece of electrically conducting material and the piece of potentially corrosive material are placed within the testing chamber and the electrical resisting measuring device monitors the electrical resistance of the piece of electrically conducting material as a function of time.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: July 31, 2012
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Scott Michael Ankeney, Brian F. Smith
  • Patent number: 8232813
    Abstract: A circuit for operating an amperometric sensor having a reference electrode, a counter electrode and a work electrode. The circuit comprises an amplifier having a positive input and a negative input and an output. The positive input is coupled to a reference voltage source, and the negative input and the output are coupled together via a negative feedback loop. The circuit includes means for coupling the amperometric sensor into said negative feedback loop of the amplifier wherein, in a first configuration, the counter electrode is coupled to said output and the reference electrode is coupled to said negative input and, in a second configuration, the work electrode is coupled to said output and the reference electrode is coupled to said negative input.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: July 31, 2012
    Assignee: Toumaz Technology Limited
    Inventors: Alison Burdett, Paul Padden, David Townsend, Sharon Louise Thornton, legal representative, Christopher David Townsend, legal representative, Richard Andrew Martin, legal representative
  • Patent number: 8232814
    Abstract: A four-wire ohmmeter connector includes a pair of elongated members spaced apart from each other by an interconnecting web. A pair of elongated contacts are mounted on forwardly projecting portions of each of the elongated members. An insulative housing surrounds the elongated members, contacts and web. The contacts mounted on one of the elongated members are connected through separate wires to a positive probe, and the contacts mounted on the other of the elongated members are connected through separate wires to a negative probe. The elongated members are inserted into respective terminal apertures of a four-wire ohmmeter. A pair of semi-cylindrical conductive sleeves are aligned with each of the apertures, and they make contact with and compress the respective contacts that are inserted into the aperture.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: July 31, 2012
    Assignee: Fluke Corporation
    Inventor: Monte Washburn
  • Patent number: 8232815
    Abstract: A plunger for holding and moving electrical components in particular IC's to and from a contacting device connected to a test bed, comprises a head piece with a fluid distribution chamber through which temperature-controlled fluid flows. A suction head is arranged such that the temperature-controlled fluid flows around the suction head and is diverted along the suction head to the component.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: July 31, 2012
    Assignee: Multitest Elektronische Systeme GmbH
    Inventors: Max Schaule, Stefan Thiel, Franz Pichl, Günther Jeserer, Andreas Wiesböck, Alexander Bauer
  • Patent number: 8232816
    Abstract: A probe head for testing semiconductor wafers has a probe contactor substrate have a first side and a second side. A plurality of probe contactor tips are coupled to the first side and the plurality of tips lie in a first plane. A plurality of mounting structures are coupled to the second side with each of the mounting structures each having a top surface lying in a second plane, wherein the first plane is substantially parallel to the second plane.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 31, 2012
    Assignee: Advantest America, Inc.
    Inventors: Salleh Ismail, Raffi Garabedian, Steven Wang
  • Patent number: 8232817
    Abstract: The present disclosure provides methods and apparatus that enable characterization of an electrical property of a semiconductor specimen, e.g., dopant concentration of a near-surface region of the specimen. In exemplary method, a target depth for measurement is selected. This thickness may, for example, correspond to a nominal production thickness of a thin active device region of the specimen. A light is adjusted to an intensity selected to characterize a target region of the specimen having a thickness no greater than the target depth and a surface of the specimen is illuminated with the light. An AC voltage signal induced in the specimen by the light is measured and this AC voltage may be used to quantify an aspect of the electrical property, e.g., to determine dopant concentration, of the target region.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: July 31, 2012
    Assignee: Nanometrics Incorporated
    Inventor: Emil Kamieniecki
  • Patent number: 8232818
    Abstract: A probe head for a microelectronic contactor assembly includes a space transformer substrate and a probe contactor substrate. Surface mount technology (SMT) electronic components are positioned close to conductive elements on the probe contactor substrate by placing the SMT electronic components in cavities in the probe contactor substrate, which cavities may be through-hole or non-through-hole cavities. In some cases, the SMT electronic components may be placed on pedestal substrates. SMT electronic components may also be positioned between the probe contactor and space transformer substrates.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: July 31, 2012
    Assignee: Advantest America, Inc.
    Inventors: Yohannes Desta, Lakshmikanth Namburi, Matthew Losey
  • Patent number: 8232819
    Abstract: Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a voltage control. The output of the voltage control is fed back to the sensitivity control of the sensor—thus forming a feedback loop. The output of the voltage control may be the power supply of the soft error rate sensor. The output of the soft error rate sensor may also be used to enable and disable fault tolerant schemes or alert a user.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: July 31, 2012
    Assignee: LSI Corporation
    Inventors: Mark F. Turner, Jeffrey S. Brown
  • Patent number: 8232820
    Abstract: A method for using pins in different mode during different time is provided. The method is able to make at least one pin of a SOC be used in a first interface mode or a second interface mode during different time; wherein the SOC comprises a first interface circuit, a first pin, a second interface circuit, and a second pin; the first interface circuit comprises a first bidirectional PAD unit, a first signal interface unit of the first interface mode and a interface unit of the second interface mode; the second interface circuit comprises a second bidirectional PAD unit, a second signal interface unit of the first interface mode. The method comprises: selecting the output of the first signal interface unit or the output of the interface unit of the second interface mode to be connected with the first pin through the first bidirectional PAD unit during different time.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 31, 2012
    Assignee: Actions Semiconductor Co., Ltd.
    Inventor: Huigang Wang
  • Patent number: 8232821
    Abstract: Multiple flip-flops each latch input data at a time point of the corresponding clock signal. The i-th (i represents an integer) first logical gate generates an internal up signal which is asserted when the output of the (2×i?1)-th flip-flop does not match the output of the (2×i)-th flip-flop. The j-th (j represents an integer) second logical gate generates an internal down signal which is asserted when the output of the (2×j)-th flip-flop does not match the output of the (2×j+1)-th flip-flop. A third logical gate generates an up signal based upon the multiple internal up signals. A fourth logical gate generates a down signal based upon the multiple internal down signals.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Shinichi Saitoh
  • Patent number: 8232822
    Abstract: A charge pump including a first current source, a second current source, a first switch, a second switch, a third switch, a fourth switch, and a reset switch is provided. First terminals of the first and the third switch are coupled to the first current source. First terminals of the second and the fourth switch are coupled to the second current source. Second terminals of the first, the second, and the reset switch are coupled to an output terminal of the charge pump. A first terminal of the reset switch is coupled to the second terminals of the third and the fourth switch. Control terminals of the first, the second, the third, and the fourth switch respectively receive a first control signal, a second control signal, an inverted signal of the first control signal, and an inverted signal of the second control signal.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: July 31, 2012
    Assignee: Industrial Technology Research Institute
    Inventor: Meng-Ting Tsai
  • Patent number: 8232823
    Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: July 31, 2012
    Assignee: Altera Corporation
    Inventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
  • Patent number: 8232824
    Abstract: Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: July 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsing Wang, Chih-Chieh Chen, Chih Sheng Tsai, Shu Yi Ying
  • Patent number: 8232825
    Abstract: The invention describes self-timed RS-trigger with the enhanced noise immunity. Declared effect is achieved due to that circuit containing storage unit (1), indication unit (2), paraphase data input (3, 4), paraphase data output (5, 6), and indication output (7), is modified by adding two inverters (8, 9) and preindication unit (10). Inverters increase output capability of the trigger's paraphase data output and provide an electric isolation of the outputs of the storage unit from an external environment that leads to increasing immunity of the data stored in the trigger to influence of noises at signal wires. The preindication unit provides the trigger's indicatability.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 31, 2012
    Assignee: Institute of Informatics Problems of The Russian Academy of Sciences (IPI RAN)
    Inventors: Igor Anatolievich Sokolov, Yury Afanasievich Stephchenkov, Yury Georgievich Dyachenko
  • Patent number: 8232826
    Abstract: A circuit with N primary outputs and a delay chain with M selection multiplexers. M can be less than N, and M is based on the number of primary outputs that simultaneously require a delayed signal from the delay chain. The N primary outputs may include core outputs and/or registers. Each of the M selection multiplexers feed directly or indirectly a subset of the N primary outputs.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: July 31, 2012
    Assignee: Altera Corporation
    Inventors: Andy Nguyen, Ling Yu, Ryan Fung
  • Patent number: 8232827
    Abstract: A semiconductor switch includes: a first terminal; a second terminal; a switch section including a through FET connected between the first terminal and the second terminal and a shunt FET connected between the second terminal and a first ground terminal; a first control terminal configured to drive the through FET; a second control terminal configured to drive the shunt FET; and a driver provided on a substrate together with the switch section and configured to provide a differential output to the first control terminal and the second control terminal.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitomo Sagae, Toshiki Seshita
  • Patent number: 8232828
    Abstract: There is provided an analog circuit having improved response time. An analog circuit having improved response time may include: a low level limiter converting a signal having a lower level than a predetermined reference level into a signal having a predetermined non-low level higher than the predetermined reference level; and an analog circuit section amplifying the signal from the low level limiter into a signal having a predetermined level.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 31, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Shinichi Iizuka, Sang Hee Kim, Jun Kyung Na, Sang Hoon Ha
  • Patent number: 8232829
    Abstract: In accordance with the present invention, the active rectifier is a circuit which directly takes the place of a passive rectifier by using a switching module (or simply a device in cases where a single device is used) controlled by a sensing circuit. Where passive devices have a single knee value determined by the physical properties of the semi-conductive material being used, the active circuit can be designed to a range of knee voltages and other performance criterion. Additional flexibility is available to the designer through the active rectifiers ability to allow for manipulation of the curve of response from the circuit in the knee region. Flexibility both in production, in designs, and in characteristics make the active rectifier highly valuable for engineering firms designing larger electronic circuits.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: July 31, 2012
    Inventor: Andrew Frederick Robinson, III
  • Patent number: 8232830
    Abstract: A highly efficient rectifier can readily replace a two-terminal diode. Its conduction losses are reduced from that of the two-terminal diode. Connected between the source and drain of a MOSFET including a parasitic diode are a micro-power converter section for boosting a conduction voltage Vds between the source and drain to a predetermined voltage, and a self-drive control section that operates based on a voltage output from the micro-power converter section. When the source and drain are conductive with each other, the micro-power converter section generates, from the conduction voltage Vds, a power source voltage for the self-drive control section, and the self-drive control section (4) continues drive control of the MOSFET.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Miyuki Takeshita, Akihiko Iwata, Ikuro Suga, Shigeki Harada, Kenichi Kawabata, Takashi Kumagai, Kenji Fujiwara
  • Patent number: 8232831
    Abstract: Multiple input and/or gain stage Gilbert cell mixer designs are disclosed. The designs allow one input to be turned on at a time, and are suitable, for example, for use in receiver and transmitter applications. In addition, the designs allow for the inputs of the multi-input Gilbert cell mixer to be connected together, thereby allowing for switching of gain states within the Gilbert cell mixer. The mixer design may include, for example, a Gilbert cell mixer stage, and a plurality of input/gain stages. Each input/gain stage has its output connected to the input of the mixer stage, and is configured for receiving an input signal and applying a gain factor to that input signal to provide a signal for mixing with the LO. Each input/gain stage is configured with stage select circuitry for enabling or disabling that stage, so that only one input/gain stage is active at a time.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: July 31, 2012
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Jeffrey T. Feng, Richard T. Chan
  • Patent number: 8232832
    Abstract: A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: July 31, 2012
    Assignee: Yamaha Corporation
    Inventors: Nobuaki Tsuji, Toshio Maejima
  • Patent number: 8232833
    Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: July 31, 2012
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Nasrin Jaffari, Hung Quoc Nguyen, Anh Ly
  • Patent number: 8232834
    Abstract: Systems and methods for increasing amplifier supply power on demand for a plurality of xDSL signals is provided. In an embodiment, circuitry may be used to detect the signal or signals having the highest voltage. In different embodiments, the signal(s) with the highest absolute voltage or highest combined voltage between complementary signal pairs may be compared to a threshold voltage, such as an existing amplifier supply voltage. In different embodiments, when these highest voltage(s) exceed the threshold voltage, the corresponding amplifier supply voltages may be increased to meet the increased amplification demand. In some embodiments when these highest voltage(s) do not exceed the threshold voltage, the amplifier supply voltage may not be increased and the existing amplifier supply voltage may be used to amplify the xDSL signals.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: July 31, 2012
    Assignee: Analog Devices, Inc.
    Inventor: John Pierdomenico
  • Patent number: 8232835
    Abstract: An apparatus for generating a voltage required for a semiconductor device by using a voltage supplied from an external power supply is provided.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: July 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-rae Kim, Hee-seok Han, Yoon-kyung Choi