Abstract: A light source module is disclosed. The light source module comprises a light emitting diode (LED) and an LED receiver. The LED is provided with a locating element on a side surface thereof. The LED receiver has a receiving portion, and a snap-fitting structure is disposed on a side surface of the receiving portion to mate with the locating element so that the LED can be located in the receiving portion of the LED receiver. An LED receiver and a backlight device are also disclosed. The light source module and the LED receiver of the present invention allow for optimization of the assembling process of the LED.

Abstract: According to one embodiment, a display element includes a light guide and a light extraction unit. The light guide extends in one direction, and is optically transmissive. The light extraction unit includes a displacement layer, a reflective layer provided on the displacement layer, and a light extraction layer provided on the reflective layer to oppose the light guide. A plurality of prisms are formed in one major surface of the light extraction layer opposing the reflective layer. A trough line is formed between mutually-adjacent ridgelines. The element has at least one selected from a configuration in which an angle between one of the oblique surfaces and one other major surface of the light extraction layer opposing the light guide is different between corresponding oblique surfaces of two mutually-adjacent prisms and a configuration in which the ridgelines of the prisms are non-parallel to the trough line between the ridgelines.

Abstract: A lighting unit 5 includes a lighting functional portion 7 and a light guide member 8. The lighting functional portion 7 includes a light source 9 and a light-transmissive housing 11. The light source 9 is constituted by a plurality of types of LEDs with different emission colors. The light guide member 8 is molded using a synthetic resin material having light permeability. The light guide member 8 has a light incidence portion 13, a light-emitting portion 14 provided at a charging port 3 of a housing 2, and an intermediate portion 15 that connects the light incidence portion 13 and the light-emitting portion 14 together. If the light-emitting portion 14 emits light with the guided light, the light-emitting portion can be caused to look like shining the charging port 3 of the housing 2.

Abstract: An electronic device is disclosed, which includes a housing, a touch pad structure, and a light-guiding structure. The light-guiding structure includes a light-guiding plate and a plurality of light-emitting units. The light-guiding plate has a main body and a thru-opening formed on the main body. The main body has a pair of opposing first edge portions and a pair of opposing second edge portions. A light-guiding member is formed on the main body around the thru-opening. The light-emitting units are disposed on or beyond the light-guiding pate and around the light-guiding member and illuminate toward the first and second edge portions. The touch pad structure is received in the thru-opening and surrounded by the light-guiding member. The touch pad structure and the light-guiding member are exposed through a slot of the housing.

Abstract: The current invention for The Device has more than one surfaces' LED track means has build-in movable LED-unit(s) which can cipper-on or added-on, or insert-on to the track-means at anywhere along the track-means length or from ends. The current invention has multiple surface track-means or plurality of individual track-means(ies) to form a multiple surface in x-y-z axis to make all kind of illumination requirements. The movable LED-unit(s) has desire construction to get all kind of features and has movable protective-means to allow people to replace, add, reduce, move the said LED-units to save cost, energy.

Abstract: To convert an electrical signal from one form to another form a chopper element is placed in a circuit for receiving any arbitrary input signal. The chopper element generates a second signal. A transformer element receives the second signal at the primary winding and generates a third signal in the secondary winding. A rectification or reconstruction element is used to ensure that the third signal has the desired frequency, magnitude and polarity. A method for converting the signal is also disclosed.

Abstract: There is embodied a high-reliability high-voltage resistance compound semiconductor device capable of improving the speed of device operation, being high in avalanche resistance, being resistant to surges, eliminating the need to connect any external diodes when applied to, for example, an inverter circuit, and achieving stable operation even if holes are produced, in addition to alleviating the concentration of electric fields on a gate electrode and thereby realizing a further improvement in voltage resistance. A gate electrode is formed so as to fill an electrode recess formed in a structure of stacked compound semiconductors with an electrode material through a gate insulation film, and a field plate recess formed in the structure of stacked compound semiconductors is filled with a p-type semiconductor, thereby forming a field plate the p-type semiconductor layer of which has contact with the structure of stacked compound semiconductors.

Abstract: A controller for use in a power supply includes a clock coupled to output a clock signal. The clock signal determines a frequency. A modulator is coupled to receive the clock signal. The clock signal is divided into N cycles within the power supply. N is an integer greater than one. The modulator is coupled to receive N feedback signals from N output circuits during each respective one of the N cycles to control conduction times of a primary switch during each respective one of the N cycles to regulate N outputs of a power supply. Each of the N feedback signals is representative of a respective one of N output voltages of a respective to one of the N outputs of the power supply.

Abstract: A main circuit of a three-level active neutral point clamped voltage source converter having a pair of additional main switches provides two paths between an output node and a neutral point in which one of the paths involves only switches of an inner pair of switches that are operated at a high frequency. An auxiliary circuit operating at a high frequency for only a brief period during each high frequency switching cycle selects the path involving only the inner switches and provides operation with zero voltage switching and avoids reverse recovery of diodes connected antiparallel with the main and additional main switches. Accordingly, turn-on switching losses in the main switches is avoided and the voltage source converter can be operated at increased frequency to allow reduction in size of magnetic components and full potential power transfer to be achieved.

Abstract: An example power converter includes an energy transfer element, a switch, and a control circuit. The control circuit includes a drive signal generator and an unregulated dormant mode control circuit. The unregulated dormant mode control circuit renders dormant the drive signal generator thereby ceasing the regulation of the output by the drive signal generator when the energy requirement of the one or more loads falls below a threshold for more than a first period of time. The drive signal generator is unresponsive to changes in the energy requirements of the one or more loads when dormant. The unregulated dormant mode control circuit powers up the drive signal generator after a second period of time has elapsed, such that the drive signal generator is again responsive to changes in the energy requirement of the one or more loads after the second period of time has elapsed.

Abstract: Disclosed is a stabilized voltage power supply comprising an A/D converting circuit configured to convert an alternate current voltage received from an external power supply to an initial direct current voltage; a PWM signal output unit configured to generate and output a PWM signal; a control switch configured to alternatively carry out, based on control of the received PWM signal, switching between a turn-on state and a turn-off state so as to convert the initial direct current voltage to a pulse voltage whose duty ratio is the same with that of the PWM signal; a final converting circuit configured to convert the pulse voltage to a final direct current voltage, and output the final direct current voltage to an external load via an output terminal; and a feed unit configured to feed the final direct current voltage back to the PWM signal output unit.

Abstract: In one aspect, a power supply includes an energy transfer element, a switch, a feedback circuit, a comparator, a state machine, and a control circuit. The feedback circuit generates a feedback signal representative of an output level of the power supply. The comparator provides a feedback state signal having a first feedback state that represents the output level of the power supply being above a threshold level and a second feedback state that represents the output level being below the threshold level. The state machine selectively modulates a first signal in response to the feedback state signal, where the first signal is the feedback signal or the threshold value signal. The control circuit is coupled to control switching of the switch to regulate the output level of the power supply in response to the feedback state signal.

Abstract: This invention presents an electrical power conditioner in the form of an electrical drive system for a machine, motor or generator. The electrical drive system has both variable frequency and fixed frequency modes. The electrical drive system includes power conditioners of less than full capacity for the variable frequency mode and a direct connection switch of full capacity for the fixed frequency mode. The electrical drive system is capable of supplying or receiving power from a variable speed electrical machine. The electrical drive system is particularly useful for wind turbines.

Abstract: A power conversion system includes n (n being an integer of 2 or more) power conversion devices (P1 to P4) connected in parallel to a load (4); and a communication line (2) connected to the n power conversion devices (P1 to P4). Each of power conversion devices includes a communication circuit (10) which transmits a load current value detected by a current sensor (37) to each of other (n?1) power conversion devices through the communication line (2), and receives (n?1) load current values transmitted through the communication line (2) from other (n?1) power conversion devices; and an operation circuit (11) calculating a shared current and a cross current of the corresponding power conversion device based on the n load current values. Accordingly, a wiring line is prevented from becoming complicated even when the number of power conversion devices is increased.

Abstract: A power converter control system having a phase tracker that is designed and configured to estimate the phase of the voltage on the power network that will be on the network when network recovers from a fault on the network. Such a power converter control system allows a power-network-connected power source to ride-through a fault event and continue supplying power thereto at the designed phase and frequency. In one embodiment, the phase tracker provides this estimate by having a response time slow enough that the voltage drop or sag caused by the fault substantially does not affect the control system. In another embodiment, the phase detector is designed and configured to freeze the frequency of its output upon detection of a fault event on the power network.

Abstract: A multiphase power converter includes one or both of a phase control circuit and a valley switching locking circuit. The phase control circuit measures a phase difference between a first phase circuit and a second phase circuit and varies an on-time of a drive switch of the second phase circuit to produce and maintain a predetermined phase difference between the first phase circuit and the second phase circuit. When the multiphase power converter is operating in a discontinuous mode of operation, the valley switching locking circuit counts the number of zero crossings of an input current of the first phase circuit and blocks a second zero crossing detection signal from a waveform generator (i.e., PWM driver) associated with the second phase circuit until an input current of the second phase circuit has as many zero crossings as that of the first phase circuit input current.

Abstract: The invention relates to a power converter and a method for power conversion. A converter transformer with a primary winding and a secondary winding, an integrated current transformer and a synchronous rectifier are provided, wherein a controller is arranged in order to close respectively to open the synchronous rectifier depending on the measured winding current. The controller is arranged to close and/or to open the synchronous rectifier as a function of the winding current at a later and/or at an earlier time, whereby the time difference between the later and the earlier time is linearly dependent on the winding current difference, particularly in order to optimise a discharge process, and/or that an auxiliary supply circuit is arranged in order to provide auxiliary supply power, wherein the auxiliary supply circuit is arranged to derive auxiliary supply power from the integrated current transformer, in particular in overload situations.

Abstract: A distributed power supply system is configured to execute a process for determining whether or not to permit a diagnostic process in such a manner that it is determined whether or not a difference between a set upper limit value and an actual measurement current value is not less than a load current value, the set upper limit value being a predetermined upper limit value set with respect to a detected current of a current sensor, the measurement current value being detected by the current sensor in a state where the diagnostic process is not executed, and the load current value being a value of a current flowing from a commercial power utility to a power load during execution of the diagnostic process; and if it is determined that the difference is not less than the load current value, the controller permits the diagnostic process.

Abstract: A single-phase hybrid multilevel inverter is described that combines a 3-level leg and a 2-level leg to reduce the number of overall switching devices for a 5-level inverter. The 2-level inverter leg switches at a fundamental frequency and the 3-level flying capacitor leg uses PWM modulation to switch resulting in a low THD output voltage spectrum. The control method developed for the single-phase inverter is used to build a three-phase inverter comprised of three single-phase hybrid inverters in order to achieve a line-to-neutral voltage having five levels and a line-to-line voltage having nine levels.

Abstract: A compound semiconductor device includes: a substrate; a first compound semiconductor layer formed over the substrate; a second compound semiconductor layer formed over the first compound semiconductor layer; and an upper electrode formed over the first compound semiconductor layer, wherein two-dimensional hole gas is generated in a region of the first compound semiconductor layer, the region being located at an interface between the first compound semiconductor layer and the second compound semiconductor layer, so as to have a hole concentration that decreases with increasing distance from the upper electrode.

Abstract: The embodiments of the present circuit and method disclose a bridge rectifier and a driving circuit. The bridge rectifier having a first input, a second input, a first output, and a second output may comprise two high side diodes and two low side switches. The driving circuit may be coupled to the first input of the bridge rectifier and the second input of the bridge rectifier, and the driving circuit may be configured to provide a first driving signal and a second driving signal. The first driving signal may be coupled to a first low side switch and the second driving signal may be coupled to a second low side switch. The first driving signal may be limited to less than a first predetermined driving voltage and the second driving signal may be limited to less than a second predetermined driving voltage.

Abstract: A power conversion device (1) comprises an inductor (L) serried-connected to an alternating-current power source (20) and a load (30), a full-bridge MERS (100) parallel-connected to the load (30), a control circuit (110), a current direction switching part (200) serried-connected between the inductor (L) and load (30), and an ammeter (300). The control circuit (110) feeds back the current detected by the ammeter (300), repeatedly turns on/off either a pair of reverse conductive semiconductor switches (SW2, SW3) or a pair of reverse conductive semiconductor switches (SW1, SW4) constituting the full-bridge MERS (100), which corresponds to the positive/negative voltage output from the alternating-current source (20), and keeps the other pair being off.

Abstract: A power regeneration device includes an extraction unit and a high frequency-to-DC converter. The extraction unit is provided on a transmission path. The transmission path is provided for transmitting a high-frequency wave from a high-frequency wave source to a high-frequency load. The extraction unit extracts a reflected high-frequency wave generated by reflecting the high-frequency wave from the high-frequency load. The high frequency-to-DC converter converts the reflected high-frequency wave extracted by the extraction unit into DC power.

Abstract: A leg includes: two semiconductor device groups connected in series and a division current is generated in a current which flows in the semiconductor device group between elements in the semiconductor device groups, a current sensor which detects a current which flows in the semiconductor device group, a voltage command generation unit which calculates a voltage command value to be outputted, a voltage drop calculating unit which calculates a voltage drop of the semiconductor device group by using a current value which is detected by the current sensor and voltage drop characteristics including a division characteristic of the semiconductor device group, and a switching control unit which corrects a voltage command value which is generated by the voltage command generation unit by using the voltage drop which is calculated so as to control ON/OFF of the switching element.

Abstract: A current-source power converting apparatus in an embodiment includes a current-reference generating unit, a polarity determining unit, a PWM-pulse-signal generating unit, and a drive-signal generating unit. The current-reference generating unit outputs a phase current reference and a line-to-line current reference. The polarity determining unit determines a polarity of the phase current reference. The PWM-pulse-signal generating unit generates a PWM pulse signal by comparing the line-to-line current reference and a carrier signal. The drive-signal generating unit generates a drive signal that drives each of a plurality of switching elements, based on the PWM pulse signal and a polarity of the phase current reference.

Abstract: One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.

Abstract: Apparatus and systems may include an interface chip, a first memory die having at least one memory array disposed on the interface chip, and a second memory die having at least one memory array disposed on the first memory die. The first memory die can include a plurality of vias configure allow a first plurality of through wafer interconnects (TWIs) to couple the interface chip with the second memory die, and the interface chip can be configured to communicatively couple the first memory die and the second memory die. Other apparatus, systems, and methods are disclosed.

Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Abstract: Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.

Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

Abstract: The present disclosure includes resistive memory sensing methods and devices. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes.

Abstract: There are provided a memory element and a memory device with improved repetition characteristics during operations at a low voltage and current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer disposed on the first electrode side, and an ion source layer disposed on the second electrode side, and having a resistivity of 2.8 m?cm or higher but lower than 1 ?cm.

Abstract: A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.

Abstract: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.

Abstract: An object of the current invention is to provide DRAM that is not limited by capacitors.

Abstract: A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.

Abstract: Magnetic memory devices are provided, the devices include at least memory cell and a reference cell on a substrate. The memory cells include a first base magnetic layer, a free layer, and a first tunnel barrier layer between the first base magnetic layer and free layer. The reference memory cell includes a second base magnetic layer, a reference magnetic layer, and a second tunnel barrier layer between the second base magnetic layer and reference magnetic layer. The reference magnetic layer has a magnetic direction substantially perpendicular to that of the free layer.

Abstract: A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

Abstract: Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to a parallel state. Because the state of the MTJ corresponds to stored data, a read disturb event may cause data loss in MRAM devices. Read disturb events may be reduced by controlling the direction of current flow through the MTJ. For example, the current direction through a reference MTJ may be selected based on the state of the reference MTJ. In another example, the current direction through a data or reference MTJ may be alternated such that the MTJ is only subject to read disturb events during approximately half the read operations on the MTJ.

Abstract: A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.

Abstract: A non-volatile memory device includes a non-volatile memory cell array including a plurality of word lines, a voltage generator configured to generate a first high-voltage using a supply voltage and a second high-voltage using an external voltage which is higher than the supply voltage, and a word line selection circuit configured.

Abstract: A nonvolatile memory device includes a page region including a plurality of normal cells and a plurality of auxiliary cells, a detecting unit configured to output a pass signal when at least one cell is programmed with a voltage higher than a reference voltage among program target cells of the page region, a count storing unit configured to store a count in the plurality of auxiliary cells during a first program operation for the page region, wherein the count indicates a total number of program pulses applied to the at least one cell until the pass signal is outputted from the detecting unit, and a voltage setting unit configured to set a program start voltage for a second program operation of the page region based on the count stored in the plurality of auxiliary cells.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that of the at least two conductive layers in the first and second blocks are disposed on the driver, and select gate lines in the first and second blocks are connected to the driver through the at least two conductive layers on the driver.

Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

Abstract: NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a wired NOR match line array is utilized. In another embodiment a NAND match line array is shown. In yet other embodiments, hierarchal addressing, hash addressing, tree search and algorithmic/hardware engine based search is detailed utilizing both conventional NAND architecture non-volatile Flash memory arrays and dedicated NAND architecture CAM arrays utilizing wired NOR and wired NAND match lines.

Abstract: Voltage generation devices and methods are useful in determining a data state of a selected memory cell in a memory device. Voltages applied to an access line coupled to a selected memory cell can be determined at least partially in response to a sensed operating characteristic of the memory device, such as operating temperature, and to a particular data state to be determined in the selected memory cell.

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.

Abstract: The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.

Abstract: A non-volatile memory device and a program method thereof are disclosed. The non-volatile memory device includes a page buffer section connected to the bit lines further connected to memory cells and where the page buffer section is for controlling a potential of the bit lines in response to control signals, and a program controller configured to perform a comparison of a count of a number of program pulses provided to the memory cells with a target number by which a program pulse of the program pulses is to be provided and output the control signals in accordance with the comparison, wherein the target number is set in accordance with a threshold voltage value of the memory cells and a state to be programmed.