Abstract: A semiconductor device includes a memory cell. The memory cell includes: a magnetic recording layer formed of ferromagnetic material; first and second magnetization fixed layers coupled to the magnetic recording layer; first and second reference layers opposed to the magnetic recording layer; and first and second tunnel barrier films inserted between the magnetic recording layer and the first and second reference layers, respectively. The first magnetization fixed layer has a magnetization fixed in a first direction, and the second magnetization fixed layer has a magnetization fixed in a second direction opposite to the first direction. The first and second reference layers and the first and second tunnel barrier films are positioned between the first and second magnetization fixed layers.

Abstract: Some embodiments include memory cells which have channel-supporting material, dielectric material over the channel-supporting material, carrier-trapping material over the dielectric material and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. Some embodiments include methods of storing information. A memory cell to is provided which has a channel-supporting material, a dielectric material over the channel-supporting material, a carrier-trapping material over the dielectric material, and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. It is determined if carriers are trapped in the carrier-trapping material to thereby ascertain a memory state of the memory cell.

Abstract: Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.

Abstract: In method of programming a nonvolatile memory device, multi-bit data are loaded into a plurality of page buffers. Multi-level cells included in a multi-level cell block are programmed to a plurality of intermediate program states including a first intermediate program state and a second intermediate program state which is higher than the first intermediate program state based on the multi-bit data. Whether the multi-level cells are programmed to the plurality of intermediate program states is verified. Cell group information for the first intermediate program state is generated by checking whether a result of the verification for the second intermediate program state satisfies a predetermined criterion. The multi-level cells are programmed to a plurality of target program states corresponding to the multi-bit data based on the cell group information.

Abstract: A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h?n) data is stored in a memory MLC of a first region MLB, and i-bit (i<h) data is stored in a memory SLC of a second region SLB. If the number of rewritings in the memory cells of the second region SLB reaches a prescribed value, the i-bit data is stored in the memory of the first region MLB rather than the memory cells of the second region SLB.

Abstract: A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.

Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.

Abstract: Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program disturb.

Abstract: Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

Abstract: Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.

Abstract: A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa.

Abstract: A memory includes a memory cell including a first terminal, a second terminal and a channel extending between the first terminal and the second terminal. The memory further includes an energy storage element configured to support a programming of the memory cell, the energy storage element being coupled to the first terminal, an energy supply coupled to the energy storage element, and a controller. The controller is configured to activate the energy supply and to bring the channel of the memory cell into a non-conductive state for energizing the energy storage element, and to subsequently bring the channel of the memory cell into a conductive state for programming the memory cell based on the energy stored in the energy storage element.

Abstract: A 3D semiconductor memory device including a plurality of memory cell strings, includes a substrate and a channel that extends from the substrate. Memory cells may be disposed in layers in which the diameter of the channel varies. A programming verification operation may be carried out in a sequence whereby memory cells more likely to fail in programming are verified before attempting to verify memory cells that are less likely to fail programming. In an exemplary embodiment, the verification operation is performed on a memory cell disposed in a layer associated with a larger-diameter channel before performing the verification on a memory cell disposed in a layer associated with a smaller-diameter channel. In an exemplary embodiment, if a verification process detects a programming failure, the verification of subsequent memory cells is cancelled.

Abstract: A plurality of element isolation insulating films are formed in a semiconductor substrate in a memory cell array and have a first direction as a long direction. A plurality of element formation regions are formed isolated by the element isolation insulating films. A memory string is formed in each of the element formation regions. A plurality of element formation region groups are each configured by the element formation regions. In a memory cell array, in a second direction orthogonal to the first direction, a spacing between the element formation region groups is configured larger than a spacing between the element formation regions in each of the element formation region groups. A control circuit executes a write operation on the memory cell array on an element formation region group basis.

Abstract: A method for controlling operations of a delay locked loop (DLL) of a dynamic random access memory (DRAM) is provided herein. A phase detector of the DLL compares an external clock signal with a feedback clock signal to generate a first control signal. A delay line circuit of the DLL delays the external clock signal according to the first control signal. A detector of the DRAM detects variations of the first control signal to determine a length of an enable period of an enable signal. The delay line circuit and the output buffer are active only during the enable period when the DRAM is in a standby mode.

Abstract: A method includes receiving a memory code identifying a number of logic zeroes and logic ones to be stored in a semiconductor memory, determining a number of bit cells of a first type that are to be coupled to a first bit line of the semiconductor memory from the memory code, and selecting a first keeper circuit from a plurality of keeper circuits based on the number of bit cells of the first type that are to be coupled to the first bit line. An electronic representation of a layout of the semiconductor memory is stored in a non-volatile machine readable storage medium.

Abstract: A circuit comprises a first voltage source, a second voltage source, a first switch, firsts transistors, and a control circuitry. The first switch is configured to selectively couple the first voltage source or the second voltage source to a first signal line. The first transistors are in an IO circuitry and have first bulks configured to receive the first signal line. The control circuitry is configured to receive a clock and a command signal on a command signal line, and generate a first control signal on a first control signal line to control the first switch based on the clock and the command signal.

Abstract: A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.

Abstract: Disclosed is a memory module which includes a memory chip; an external input/output terminal having an electrical signal input/output terminal and an optical signal input/output terminal; an optical signal processor configured to convert a first optical signal input through the optical signal input/output terminal into a first internal electrical signal and to convert a second internal electrical signal into a second optical signal; and a controller configured to provide a first data signal to the memory chip in response to a first external electrical signal input through the electrical signal input/output terminal or the first internal electrical signal and to transfer the second internal electrical signal to the optical signal processor or to output a second external electrical signal to the electrical signal input/output terminal in response to a second data signal output from the memory chip.

Abstract: Disclosed herein is a semiconductor device having a self-refresh mode in which a refresh operation of the storage data is performed. The semiconductor device activates an input buffer circuit that receives an impedance control command to control an impedance of the data terminal even in the self-refresh mode so that the semiconductor device can change an impedance of the data terminal during the self-refresh mode.

Abstract: A memory device has: a plurality of memory cell blocks, the memory cell block including a plurality of memory cells, a redundancy memory cell, and a selector switching a defective memory cell among the plurality of memory cells to the redundancy memory cell; and a control circuit outputting control signals of the selectors of the plurality of memory cell blocks, based on defect information indicating whether or not each of the plurality of memory cell blocks has a defective memory cell and on specification information for specifying the defective memory cell in the memory cell block having the defective memory cell, wherein the control circuit has: a plurality of flip-flops provided in correspondence with respective bit lines of the control signals of the selectors of the plurality of memory cell blocks and for shifting the specification information serially.

Abstract: A screening method for testing solid-state memories for the effects of long-term shift and random telegraph noise (RTN). In the context of static random access memories (SRAMs), each memory cell in the array is functionally tested with a bias voltage (e.g., the cell power supply voltage) at a severe first guardband sufficient to account for worst case long-term shift and RTN effects. Cells failing the first guardband are then repeatedly tested with the bias voltage at a second guardband, less severe than the first guardband; if the tested cells pass this second guardband, the suspect cells are considered to not be vulnerable to RTN effects. Over-screening due to an unduly severe guardband is avoided, while still screening vulnerable memories from the population.

Abstract: Disclosed herein is a semiconductor device having first and second operation modes. In the first operation mode, the semiconductor device deactivates a DLL circuit during a self-refresh mode. In the second operation mode, the semiconductor device intermittently activates the DLL circuit to generate an internal clock signal.

Abstract: Disclosed herein is a semiconductor device having self-refresh modes in which a refresh operation of storage data is periodically performed asynchronously with an external clock signal. The semiconductor device performs the refresh operation on n memory cells in response to an auto-refresh command. The semiconductor device periodically performs the refresh operation on m memory cells included in the memory cell array during the self-refresh mode, where m is smaller than n.

Abstract: A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.

Abstract: A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes.

Abstract: Exemplary embodiments comprise memory for storing the look-up table values. One exemplary memory comprises a decoder, an encoder, and one or more patterns of crisscrossed interconnect lines that interconnect the encoder with the decoder. The patterns of crisscrossed interconnection lines may be implemented on one or more planar layers of conductor tracks vertically interleaved with isolating material.

Abstract: A method for calibrating an apparatus for measuring shape factor is provided, wherein the method comprises determining aspect ratios for each of a plurality of kaolin samples and measuring the shape factors of each of the plurality of kaolin samples using the apparatus, wherein each of the kaolin samples includes potassium oxide in an amount less than about 0.1% by weight of each of the kaolin samples. The method further includes calibrating the apparatus based on a correlation between the aspect ratios and the shape factors.

Abstract: Systems for controlling fluids in semiconductor processing systems are disclosed. The disclosed systems comprise a chemical blender, a reclaim tank, a dispense system, two chemical monitors, a controller, and a reclamation line in fluid communication with an outlet of the process station and coupled to the reclaim tank. The reclaim tank mixes solution from the chemical blender and the reclamation line. One of the two chemical monitors the mixed solution downstream from the dispense system. The controller is configured to flow the mixed solution to the process station upon determination by the first chemical monitor that at least one chemical compound in the mixed solution is at a predetermined concentration. The second chemical monitor monitors the reclaimed portion of the mixed solution to determine whether the at least one chemical compound is at a predetermined concentration before being reintroduced into the reclaim tank.

Abstract: Food processing apparati including magnetic drives are described herein. According to one exemplary embodiment, a food processing apparatus may include a motor having a motor shaft, a rotor rotatably mounted on the motor shaft, and a stator producing an electromagnetic field for interacting with the rotor. The rotor may magnetically drive a drive plate coupled to an impeller inside a food-contact chamber.

Abstract: A method for acquiring seismic data. The method may include towing an array of marine seismic streamers coupled to a vessel. The array includes a plurality of receivers and a plurality of steering devices. The method may further include steering the array of marine seismic streamers to be towed along two or more depths, and steering the array of marine seismic streamers to a slant from an inline direction while maintaining the array of marine seismic streamers at their respective two or more depths.

Abstract: Depth triggers for marine geophysical survey cable retriever systems. At least some of the illustrative embodiments include causing a submerged geophysical survey cable to surface. In some cases, the causing the cable to surface may include: fracturing a frangible link wherein the frangible link, before the fracturing, affixes position of a piston within a cylinder bore of a housing coupled to the geophysical survey cable, and the fracturing of the frangible link responsive to pressure exerted on a face of the piston as the geophysical survey cable reaches or exceeds a predetermined depth; moving the piston within the cylinder bore; and deploying a mechanism that makes the geophysical survey cable more positively buoyant.

Abstract: A system is proposed for conducting efficient marine seismic surveys in different climatic conditions for water depths of 0-500 meters, in near-shore zones and on the land for obtaining seamless profiles. The system includes at least one bottom module (BM) and onboard devices located on a vessel. The BM can be submerged from the vessel onto a bottom ground and lifted up on the board. The BM includes a case provided with roundings on its upper surface and its bottom area, to which case are mounted damping elements, a hydrophone and a geophone block for receiving seismic data, a vacuum port, a hermetic electrical socket, and equipment arranged inside the case, including—a clock generator,—a digital compass providing angle data,—an interface board essentially reading the seismic and angle data and transmitting thereof to the onboard devices, and—a recorder board communicating with the geophones, hydrophone, and interface board.

Abstract: Disclosed are apparatus and methods for seismic imaging which accounts for sea-surface variations. In accordance with one embodiment, a source wave-field is forward propagated to a subsurface level below a sea floor. In addition, a receiver wave-field is backward propagated to the subsurface level, wherein the backward propagation in time comprises synchronized backward running of the sea surface. Other embodiments, aspects, and features are also disclosed.

Abstract: Rough sea elevation is estimated from a high-frequency portion of recorded pressure data and recorded vertical velocity component data. Generalized deghosting and datuming operators are constructed, which take into account the estimated rough sea elevation and irregular recording depth conditions. A low-frequency portion of the recorded pressure data is decomposed into up-going and down-going wavefields on a horizontal reference plane, using the generalized datuming and deghosting operators. A low-frequency portion of the vertical velocity component data is reconstructed from the decomposed up-going and down-going wavefields on the horizontal reference plane, using the generalized datuming and deghosting operators.

Abstract: Measurement data acquired by at least one sensor in a cable structure towed through a body of water is received. A torsional vibration noise component in the measurement data is estimated. The torsional vibration noise component is used to estimate a rotation angle of the at least one survey sensor with respect to a reference coordinate system of the cable structure.

Abstract: There is provided herein a method of passive seismic acquisition that utilizes real time or near real time computation to reduce the volume of data that must be moved from the field to the processing center. Much of the computation that is traditionally applied to passive source data can be done in a streaming fashion. The raw data that passes through a field system can be processed in manageable pieces, after which the original data can be discarded and the intermediate results accumulated and periodically saved. These saved intermediate results are at least two, more likely three, orders of magnitude smaller than the raw data they are derived from. Such a volume of data is trivial to store, transport or transmit, allowing passive seismic acquisition to be practically used for continuous near-real-time seismic surveillance.

Abstract: Method for speeding up iterative inversion of seismic data (106) to obtain a subsurface model (102), using local cost function optimization. The frequency spectrum of the updated model at each iteration is controlled to match a known or estimated frequency spectrum for the subsurface region, preferably the average amplitude spectrum of the subsurface P-impedance. The controlling is done either by applying a spectral-shaping filter to the source wavelet (303) and to the data (302) or by applying the filter, which may vary with time, to the gradient of the cost function (403). The source wavelet's amplitude spectrum (before filtering) should satisfy D(f)=fIp(f)W(f), where f is frequency, D(f) is the average amplitude spectrum of the seismic data, and Ip(f) is the average amplitude spectrum for P-impedance in the subsurface region (306,402) or an approximation thereof.

Abstract: An obstacle detection system includes ultrasonic sensors and a controller. The ultrasonic sensors include first and second ultrasonic sensors. Each of them is located at either side of a vehicle bumper so that its own beam axis has an angle deflected in a horizontal direction from a surface-normal direction of the bumper and is directed towards an intermediate portion of the bumper.

Abstract: An ultrasonic membrane having ultrasonic transmission(s) over the surface area of the membrane with circuitry to control transmission(s), it can be made to any size but can also be connected to other membranes in each direction to cover large areas for example a super tanker hull.

Abstract: Disclosed is a high directive ultrasonic transducer that can concentrate a radiated ultrasonic wave in one direction by making an orientation angle of the radiated ultrasonic wave small in an ultrasonic transducer having a planar radiation plate structure, which has high radiation efficiency in an air medium. The high directive ultrasonic transducer according to the present disclosure includes a planar radiation plate configured to radiate an ultrasonic wave into a medium; a driving unit configured to vibrate the radiation plate in a higher order mode of a secondary order or more by applying predetermined force to a bottom surface of the radiation plate; and a matching layer formed in a height corresponding to 1/4 of an ultrasonic wavelength in the medium, in a part having a positive vibration velocity on a top surface of the radiation plate.

Abstract: A balance wheel for timepiece movement, which obeys the following condition: D5·f/I?20?2m3kg?1s?1 where D is the diameter of the balance wheel, f is the frequency and I is the moment of inertia.

Abstract: In a trick-action type clock, a part of an hour plate rotates along a plane parallel to a clock support plate. The trick-action type clock includes a first hour plate portion which is fixed to the clock support plate and has a circular shape, and a second hour plate portion which is rotated by a driving motor. The first hour plate portion includes an indicator needle shaft insertion portion which is provided at a position remote from a center of the first hour plate portion so as to insert an indicator needle shaft 101 therethrough. The second hour plate portion includes a circular notched hole which has a rotation center coincides with the center of the first hour plate portion with a circular shape and has the same shape as that of the first hour plate portion.

Abstract: In a case in which a microwave-assisted magnetic recording system is applied to a shingled write system for recording with high density, the width of a high-frequency generation element is narrower than a track width of main pole, and both steep parts of magnetic field gradients 24 and 25 are overlap each other by performing offset of a high-frequency magnetic field generating unit 17 of the magnetic head for shingled write from the central line of the main pole 8 in the both areas having high magnetic field gradient.

Abstract: A thermally-assisted recording (TAR) disk drive uses “shingled” recording and a rectangular waveguide as a “wide-area” heat source. The waveguide generates a generally elliptically-shaped optical spot that heats an area of the recording layer extending across multiple data tracks. The waveguide core has an aspect ratio (cross-track width to along-the track thickness) that achieves the desired size of the heated area while locating the peak optical intensity close to the trailing edge of the write pole tip where writing occurs. The large cross-track width of the waveguide core increases the volume of recording layer heated by the optical spot, which reduces the rate of cooling. This moves the peak temperature point of the heated area closer to the write pole tip and reduces the temperature drop between the peak temperature and the temperature at the trailing edge of the write pole tip where writing occurs.

Abstract: A slider may have a first surface on an air bearing surface (ABS) and a laser recess formed in a second surface of the slider, opposite the first surface. A laser can then be positioned in the laser recess with the laser extending from the slider to a top plane. A stud may be formed adjacent to and separated from the laser on the second surface of the slider with the stud extending from the second surface of the slider to the top plane.

Abstract: A thermally-assisted recording (TAR) disk drive that uses “shingled” recording and a rectangular waveguide as a “wide-area” heat source includes a controller that counts the number of writes to each annular band of data tracks. The wide-area heater generates a heat spot that extends across multiple tracks, so that each time an annular band is written, the data in tracks in adjacent bands are also heated. Because the bands are written independently, the number of passes of the heat spot and thereby the number of times the data tracks in a band are exposed to elevated temperatures without being re-written is related to the number of re-writes of the adjacent bands. The number of writes to each band is counted and when that count reaches a predetermined threshold value, one or more tracks in an adjacent band are re-written to avoid reaching an unacceptable level of magnetization decay in the tracks of the adjacent band.

Abstract: An optical disc drive and a method of reading an optical disc are disclosed. The drive includes an I/O port, an optical pickup module and a format conversion unit. The I/O port couples a host to receive a read command of a host terminal file system format. The optical pickup module accesses the optical disc which contains data of a first file system format. The format conversion unit coupled between the I/O port and the optical pickup module includes a mapping information generation module, a memory module and a read-command processing module. The mapping information generation module controls the optical pickup module to access data and thereby to generate mapping information. The memory module stores the mapping information. The read-command processing module controls the optical pickup module to access the optical disc according to the read command by referring to the mapping information.

Abstract: The amplitude deviation of a tracking error signal in an optical disk apparatus is reliably corrected by processing signals at low costs. A servo signal generator generates a tracking error signal and a lens error signal from a photodetected signal. A lens error deviation signal memory circuit stores the lens error signal generated at the servo signal generator, and reproduces the one-turn deviation of the lens error signal. A tracking error signal corrector learns an amplitude correcting value for the tracking error signal from the tracking error signal detected in reproducing the one-turn deviation of the lens error signal, and stores the amplitude correcting value in a correcting signal generator.

Abstract: A servo control device includes a plurality of reproduction channels, a plurality of analog/digital (A/D) converters, a servo error detecting circuit that generates a servo error signal, a servo signal processing device that executes predetermined processing for the servo error signal to generate a control signal, and a sampling frequency converter that converts the sampling frequency between the servo error detecting circuit and the servo signal processing device. A first clock is included as a sampling clock of the A/D converters and a processing clock of the servo error detecting circuit. A second clock is included as a processing clock of the servo signal processing device. The sampling frequency converter converts the sampling frequency by processing the servo error signal by the servo error detecting circuit in synchronization with the first clock and processing the signal processed in synchronization with the first clock in synchronization with the second clock.