Abstract: A magneto-impedance element includes a magnetic sensitive member having a form of a line, whose electromagnetic characteristics vary depending on an external magnetic field, a pulse current flowing from one to another end portion thereof in an axial direction. A conductive layer is arranged on an insulating layer provided on an outer surface of the magnetic sensitive member. A connection portion, electrically connecting the magnetic sensitive member and the conductive layer, is arranged on the other end portion in the axial direction of the magnetic sensitive member. A detection coil, outputting an induced voltage corresponding to an intensity of an external magnetic field acting on the magnetic sensitive member when the pulse current flows in the magnetic sensitive member, is wounded around the conductive layer. A direction of the pulse currents flowing in the magnetic sensitive member and in the conductive layer are opposite each other.

Abstract: An apparatus and system, capable of measuring the magnitude and direction of magnetic fields including an ultra-sensitive, wideband magneto optic (MO) sensor having magneto-optic crystals is disclosed herein. The sensor exploits the Faraday Effect and is based on a polarimetric technique. An ultra sensitivity optical-fiber magneto-optic field sensor measures a magnetic field with minimal perturbation to the field, and the sensor can be used for High-power microwave (HPM) test and evaluation; Diagnosis of radar and RF/microwave devices; Detection/measurement of weak magnetic fields (e.g., magnetic resonance imaging); Characterization of very intense magnetic fields (>100 Tesla, for example rail gun characterization); Detection of very low-frequency magnetic fields; Characterization of a magnetic field over an ultra broad frequency band (DC—2 GHz); Submarine detection; and Submarine underwater communication.

Abstract: Apparatus and methods enabling the improved noninvasive measurement of electric currents flowing in the body of a human being or animal or in a biological sample by means of a modular array of primary source mirrors and a magnetometer.

Abstract: A method of exciting nuclear spins in a body, the method comprising the steps of: (a) immerging said body (PB) in a static magnetic field (B0) for aligning nuclear spins along a magnetization axis (z), said static magnetic field being substantially uniform over at least a volume of interest (VOI) of said body; (b) exposing said body, or at least said volume of interest, to a time-varying magnetic field gradient having components (Gx, Gy, Gz) directed along at least three non-coplanar directions (x, y, z) and to a transverse radio-frequency field (B1), whereby said time-varying magnetic field gradient defines a three-dimensional trajectory in k-space constituted by segments linking discrete points (kT1?kT9), and said transverse radio-frequency field deposits radio-frequency energy along at least part of said trajectory for flipping said nuclear spins by a same predetermined flip angle, independently from their position within said volume of interest.

Abstract: In a method to acquire a magnetic resonance image data set of a target volume with a magnetic resonance device, wherein the target volume is composed of a number of sub-volumes defined in a two-dimensional plane orthogonal to the readout direction, for each sub-volume, in order to acquire a partial data set of a sub-volume, a targeted excitation of the sub-volume and a data acquisition from that sub-volume to measure the partial data set take place by radiation of a first radio-frequency pulse acting in a first direction of the plane and radiation of a second radio-frequency pulse acting in a second direction that is orthogonal to the first direction. The partial data sets are combined into the magnetic resonance data set.

Abstract: A feedforward control unit predicts the maximum value of the temperature of a gradient coil based on a power duty and a scan time of a pulse sequence, and a present temperature of the gradient coil. When the maximum value exceeds a predetermined upper limit, the feedforward control unit then instructs a temperature adjusting unit to start a water circulation in a chiller at the start of a prescan, and the temperature adjusting unit starts the water circulation based on the instruction.

Abstract: A controller of a magnetic resonance system outputs a low frequency base signal to a conversion device. While outputting the base signal to the conversion device, the controller outputs an oscillator control signal to an oscillator. The oscillator outputs a frequency signal corresponding to the oscillator control signal to the conversion device. The conversion device converts the frequency signal into a high frequency transmit pulse with the aid of the base signal and outputs the transmit pulse to a magnetic resonance transmit antenna. The magnetic resonance transmit antenna applies a high frequency field corresponding to a transmit pulse to an examination volume of the magnetic resonance system. The controller varies the oscillator control signal output to the oscillator while outputting the base signal to the modulator. The transmit pulse) has a larger bandwidth than the base signal.

Abstract: Magnetic resonance systems, devices, methods, and compositions are provided. A nuclear magnetic resonance imaging composition includes, but is not limited to, a plurality of ferromagnetic microstructures configured to generate a time-invariant magnetic field within at least a portion of one or more internal surface-defined voids. In an embodiment, at least one of the plurality of ferromagnetic microstructures includes one or more targeting moieties attached thereof.

Abstract: The invention relates to a method for manufacturing a coil for generating an intense magnetic field when an electric current passes through it, comprising the formation of turns in a cylindrical tube made of conducting or superconducting material, the formation of at least one indentation in an edge of at least one turn of said coil and the positioning of insulating material between the turn comprising the indentation and an adjacent turn, said recess being made in the edge to form with the insulating material a channel between the interior and the exterior of the tube when the coil is stressed.

Abstract: The present disclosure is directed to an antenna for transfer of information along a drill string. The antenna has an antenna coil having a long side and short side. The antenna coil is adapted to be affixed to the drill string such that the long side of the antenna coil is along the longitudinal axis of the drill string, and the short side is perpendicular to the longitudinal axis of the drill string.

Abstract: A deterioration degree calculating apparatus for a secondary battery of the invention includes: obtaining a voltage value at a stop time of charge and discharge of a target secondary battery; obtaining a voltage value at a first start time of charge and discharge after that; obtaining an SOC of the target secondary battery at the stop time or at the start time; obtaining a length of an unused period from the stop time to the start time (an elapsed time); obtaining a self-discharge slope of the target secondary battery by dividing an absolute value of a difference between the voltage value at the start time and the voltage value at the stop time by the elapsed time; obtaining a temperature during an unused period by use of a self-discharge map in which the SOC and the self-discharge slope is recorded for each temperature; calculating a progress degree of deterioration of the target secondary battery during the unused period based on the obtained temperature and elapsed time; and accumulating the calculated det

Abstract: Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.

Abstract: Provided is a switching apparatus comprising a contact point section that includes a first contact point; an actuator that includes a second contact point and moves the second contact point to contact or move away from the first contact point; and a control section that controls a first drive voltage. The actuator includes a first piezoelectric film that expands and contracts according to the first drive voltage and a support layer disposed on the first piezoelectric film. The control section causes the first piezoelectric film to contract by causing a change from a voltage that applies an electric field that is less than a first coercive electric field to a voltage that applies an electric field that exceeds the first coercive electric field, and causes the first piezoelectric film to expand by outputting a voltage that applies an electric field that is less than a second coercive electric field.

Abstract: A calibration device applied for a test apparatus with at least a first probe and a second probe, the calibration device comprising: a first testing region and a second testing region, the first testing region and the second testing region divides into n×n sensing units respectively, the first testing region for generating n×n average electricity corresponding to a contact degree of the first probe contacted with the calibration device, and the second testing region for generating another n×n average electricity corresponding to a contact degree of the second probe contacted with the calibration device, and the pitch is the distance between the center of the first testing region to the center of the second testing region that is the same as that of the center of the first probe to the center of the second probe.

Abstract: A method, implemented by a software-controlled computer device and/or by dedicated hardware, for probing an electrically conductive target material, e.g. molten metal or semiconductor material, in a metallurgical vessel. In the method, a measurement signal is acquired from a sensor, which is inserted into the target material, during a relative displacement between the electrically conductive target material and the sensor, the measurement signal being indicative of electrical conductivity in the vicinity of the sensor. The measurement signal is generated to represent momentary changes in an electromagnetic field around the sensor, which is created by operating at least one coil in the sensor. Based on the measurement signal, a signal profile is generated to be indicative of the electrical conductivity as a function of the relative movement. The method enables a probing of the internal distribution of the target material in the vessel at any level of detail.

Abstract: In one embodiment, a method includes communicating a first voltage to a drive line of a touch sensor; setting a sense line of the touch sensor to a predetermined voltage; and communicating a second voltage to the drive line. A resulting transition at the drive line from the first voltage to the second voltage causes an amount of charge accumulated on the sense line to be communicated to an integrator. The method also includes, at the integrator, integrating the amount of charge communicated from the sense line to convert the amount of charge to an output voltage. The method also includes restoring the sense line to the predetermined voltage.

Abstract: A method and apparatus determine a plurality of regions, each of the plurality of regions having a detected change in capacitance value that meets or exceeds a threshold value. In an embodiment, the method and apparatus fit a shape to the plurality of regions and determine another region, the other region being within the fitted shape and not having the detected change in capacitance value that meets or exceeds the threshold value. The method and apparatus may assign an assigned change in capacitance value to the other region.

Abstract: A measurement apparatus comprising a serial resistor in series with an element under measurement; a switching section that sequentially selects ends of a serial circuit including the element under measurement and the serial resistor, and ends of the serial resistor; an applying section that applies an application voltage or application current corresponding to a preset setting value, to each of the sequentially selected ends; a measuring section that, for each of the sequentially selected ends, measures current when the applying section applies the application voltage corresponding to the setting value and measures voltage when the applying section applies the application current corresponding to the setting value; and a resistance calculating section that calculates the resistance value of the element under measurement, based on either the setting values set sequentially in the applying section or measured values measured sequentially by the measuring section for each of the sequentially selected ends.

Abstract: In one possible implementation, a method is provided for determining contactor health including measuring a differential voltage between a first utility line voltage and a second utility line voltage on a primary side of a contactor and on a secondary side of the contactor. The measuring is performed with both an unloaded current and with a load current. The unloaded and loaded measurements are performed at the primary side and the secondary side, and are made with the contactor closed. It includes determining a difference between a secondary unloaded voltage and a secondary loaded voltage and subtracting a difference between a primary unloaded voltage and a primary loaded voltage to provide a contactor voltage drop. The contactor resistance is determined by dividing the contactor voltage drop by the loaded current.

Abstract: Provided is a motor control apparatus that can easily distinguish between a current sensor abnormality and a rotation-angle sensor abnormality, without making a current sensor a duplex system. An MGECU (140) estimates a W-phase current on the basis of a V-phase current detected by a current sensor (125), and estimates the V-phase current on the basis of a detected W-phase current. An actual torque of a motor generator MG2 is estimated on the basis of the detected V-phase current and the estimated W-phase current, and the actual torque of the motor generator MG2 is also estimated on the basis of the detected W-phase current and the estimated V-phase current. Then, an evaluation is made whether an abnormality is an abnormality of the current sensor (125) or an abnormality of a resolver (124), on the basis of the differences between the torque command value for the motor generator MG2 and both the estimated actual torques.

Abstract: A test circuit includes two probes, a comparison circuit, a switch circuit, and an indication circuit. The probes are connected to an electronic component to be tested, and a low level signal is output if the electronic component is short-circuited. The comparison circuit outputs a comparison signal based on the shorting signal from the probes. The switch circuit outputs a switch signal based on the comparison signal from the comparison circuit. The indication circuit indicates that the electronic component is short-circuited or not short-circuited based on the switch signal fro m the switch circuit.

Abstract: A probe assembly includes probe heads, a first connector, and groups of second connectors. Each probe head includes a first connection portion defining two first holes, and a data cable connected to an oscilligraph. The first connector includes a fixing portion and groups of rods fixed to the fixing portion. Each group of rods includes two rods. First ends of each group of rods are detachably inserted into the first holes to electrically connect the corresponding data cable. Each group of second connectors includes a second connection portion defines two second holes, and a connection cable. Second ends of the group of rods are detachably inserted into the second holes to connect the connection cable.

Abstract: Probes are arranged precisely and at a narrow pitch. Provided is a probe structure receiving and transmitting an electric signal from/to a device. The probe structure includes a contact point that transmits an electric signal, a probe on which the contact point is formed, a probe pad section that is electrically coupled to the contact point, and an insulating section that is provided on the probe and that insulates a bonding wire connected to the probe pad section from the probe. A probe apparatus, a manufacturing method of a probe structure, and a test apparatus are also provided.

Abstract: Apparatus and methods related to data transmission are disclosed. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes a pair of current sources and a pair of switches. Each of the switches conducts one of the current sources to the channel in response to input data. The receiver includes a first node configured to receive a signal over the channel. The receiver also includes a resistance generating a voltage drop between the first node and a second node. The receiver further includes a first transistor and a second transistor that are together configured to provide a voltage level to the second node based at least partly on the voltage drop. The resistance provides a negative feedback to center the mean signal level, thereby reducing intersymbol interference.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Abstract: An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier.

Abstract: A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an output of the second inverter and has an output coupled to a first node. A fifth inverter has an input coupled to the first node and an output coupled to a second node to which an output of the third inverter is coupled. Sixth and seventh inverters are configured to respectively output a differential signal based on the single-ended signal. The sixth inverter has an input coupled to the first node, and the seventh inverter has an input coupled to the second node.

Abstract: A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals.

Abstract: Circuit for detecting malfunction of a primary clock in SoCs comprises a primary clock circuit having a GRAY code counter for generating a GRAY code sequence based on a number of clock pulses generated Primary clock. A secondary clock circuit is configured to output a secondary clock pulse on each saturation of a secondary clock counter. A clock gated register circuit is clocked by the secondary clock pulse, and is configured to store a plurality of values of the GRAY code sequence, and update the plurality of values of the GRAY code sequence on each saturation of the secondary clock counter. An error detection circuit is configured to output a detection signal for detecting the malfunction of primary clock based on a comparison of the updated plurality of values of the GRAY code sequence with at least one predetermined threshold associated with the malfunction of primary clock.

Abstract: A system for simulating biofidelic signals includes a transducer and a neural transmitter port. The transducer is affected by a parameter and provides an alternating electrical signal based on an effect of the parameter. The neural transmitter port receives a processed electrical signal and outputs the processed electrical to a neural transmitter. The system further includes an input portion, a band-pass filter, and an integrate-and-fire mechanism. The input portion outputs a first signal based on the alternating electrical signal. The band-pass filter outputs a first filtered signal based on the first signal. The integrate-and-fire mechanism generates the processed electrical signal based on the first filtered signal.

Abstract: Disclosed is a discharge path circuit of input terminal for a driver IC (Integrated Chip), the circuit providing a discharge path to the input terminal of the driver IC including a power input port connected to a first input and an operation mode selection port connected to a second input, the discharge path circuit including an LC (Inductance Capacitance) filter interconnected between the first input and the power input port to filter noise on a power source, and a resistance element interconnected between the first input and a ground terminal, wherein the resistance element provides a discharge path for discharging power charged by the input terminal of the driver IC.

Abstract: The present invention relates to an output driving circuit and a transistor output circuit. In accordance with an embodiment of the present invention, an output driving circuit including: a first driving circuit unit driven according to on operation of a first switch to supply high voltage power source to a gate of an output transistor; a second driving circuit unit driven by a one-shot pulse generated according to on operation of a second switch, which operates complementarily with the first switch, to discharge a gate-source capacitance of the output transistor; and an output driving voltage clamping unit disposed between a high voltage power source terminal and the gate of the output transistor in parallel with the first driving circuit unit to maintain a gate potential of the output transistor discharged according to the on operation of the second switch is provided.

Abstract: Disclosed herein are an output driving circuit and a transistor output circuit. The output driving circuit includes: a reference voltage generating unit generating a reference voltage; a level shift unit including a transistor latch and turning off a first transistor of a driving circuit or driving the first transistor; a driving circuit unit including the first transistor that is driven to apply power to a gate of an output transistor and a second transistor that is driven complementarily to the first transistor to lower a gate voltage of the output transistor and drive the output transistor; and an withstand voltage protecting unit that is driven by receiving a reference voltage and includes a first withstand voltage protecting unit for protecting transistors of the transistor latch and the first transistor for stable operations thereof and a second withstand voltage protecting unit for protecting the output transistor for a stable operation thereof.

Abstract: A switching circuit for switching a time-varying input signal, the switching circuit comprising: at least one switch including a N-channel MOSFET and a P-channel MOSFET, each having a gate configured to receive a drive signal to change the ON/OFF state of the switch; and a drive circuit configured and arranged so as to selectively apply a pair of drive signals to change the ON/OFF state of the switch, the drive circuit being configured and arranged to generate the drive signals as a function of (a) a pair DC signal components sufficient to change the ON/OFF state of the switch and (b) a pair of time-varying signal components as at least a partial replica of the signal present on the source terminal of each MOSFET so that when applied with the DC signals to the gates of the re-channel MOSFET and p-channel MOSFET respectively, the drive signals will be at the appropriate level to maintain the ON/OFF state of the switch and keep the gate-source voltages of each MOSFET within the gate-source breakdown limit of th

Abstract: Determining time latency at a sensor node in a mesh network. A beacon time is received at the sensor node from an upstream node, the beacon time offset from global time by the latency. The latency, the global time, and a corresponding local time are determined at the sensor node.

Abstract: A digital glitch filter for filtering glitches in an input signal includes first and second flip-flops and a synchronizer. The synchronizer includes third and fourth flip-flops. A glitch prone input signal is provided to the first and second flip-flops. Additionally, an input clock signal is provided to the first and second flip-flops and the synchronizer. A glitch occurring in the input signal toggles the first and second flip-flops between transmitting and non-transmitting states and first and second intermediate signals are generated. The synchronizer synchronizes the first and second intermediate signals with the input clock signal to generate a filtered output signal.

Abstract: Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.

Abstract: Power switching is facilitated. In accordance with one or more embodiments, a power-switch apparatus includes a plurality of switches coupled between a voltage supply and a switched voltage output. A test control circuit operates the switches for testing a subset thereof, therein indicating a condition of the subset, which may be indicated independently from a condition of the power-switch apparatus as a whole. In some implementations, on-chip current loads are applied to emulate off-chip loads for testing the subset of switches, or individual switches.

Abstract: According to one embodiment, a semiconductor switch includes a voltage generator, a driver, a switch section, and a power supply controller. The voltage generator is configured to generate a first potential and a negative second potential. The first potential is higher than a power supply voltage supplied to a power supply terminal. The driver is connected to an output of the voltage generator and is configured to output the first potential in response to input of high level and to output the second potential in response to input of low level. The switch section is configured to switch connection between terminals in response to an output of the driver. The power supply controller is configured to control the output of the voltage generator.

Abstract: A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.

Abstract: An oscillation circuit includes an RS flip-flop for generating output signals based on a set signal and a reset signal, an electric-charge charge/discharge unit which has first and second capacitors and charges or discharges the first and second capacitors complementarily based on the output signals, a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage and outputs the set signal, a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage and outputs the reset signal, and a control unit for controlling a timing at which respective voltage levels of the first reference voltage and the first voltage match and a timing at which respective voltage levels of the first reference voltage and the second voltage match according to a frequency of the output signals.

Abstract: A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Abstract: A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.

Abstract: A source driver with an automatic de-skew capability is configured to receive a data signal and a clock signal from a timing controller, which are configured to drive a liquid crystal display panel. The source driver includes a signal delay unit, a setup time register, a hold time register, a first signal delay unit, a second delay unit and a logic circuit. In one embodiment of the present disclosure, the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal.

Abstract: A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.

Abstract: A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.

Abstract: A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

Abstract: An electronic system is configured for scan testing, with a clock distribution network going to a plurality of blocks of the system, and a test capture clock being generated locally at each block. Capture clock pulses may optionally be generated at different times for different blocks, and may optionally be suppressed for some blocks.

Abstract: A second driver is provided in addition to a first driver outputting an output signal in accordance with a voltage of an input signal. When the output signal changes from a first voltage level to a second voltage level in accordance with a voltage change of the input signal, a control part controls the second driver to assist the signal change during a period from a change start time until the output signal exceeds a third voltage level. The control part controls the second driver to suppress the signal change during a period from the time when the output signal exceeds the third voltage level until it reaches the second voltage level.