Patents Issued in March 14, 2013
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Publication number: 20130067112Abstract: A server device may store policy information that includes subscription information associated with one or more user devices, and an indication of how to route traffic upon detecting traffic associated with the one or more user devices associated with the stored subscription information. The server device may receive information associated with a particular traffic flow, where at least some of the received information is derived from the particular traffic flow. The server device may compare the received information to the stored policy information. The server device may detect, based on the comparing, that the particular traffic flow is associated with a particular one of the one or more user devices associated with the stored subscription information. The server device may route the particular traffic flow based on the stored policy information.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: VERIZON PATENT AND LICENSING INC.Inventors: Emerando DELOS REYES, Benjamin J. PARKER, Samir AIT-AMEUR, Lin SUN
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Publication number: 20130067113Abstract: The invention relates in particular to the optimization of routing in a cluster comprising a plurality of nodes and static communication links connecting nodes of the plurality of nodes, said routing being based on load levels associated with the communication links. In order to establish a connection between at least two nodes of the cluster that have been identified (505), at least one route is determined (510) that connects the identified nodes according to the communication links, said route being determined according to the nodes identified, communication links and at least one load level associated with each communication link. A determined route is selected. Subsequently, a value of weight associated with the selected route is estimated (520) and a load level associated with each communication link of the selected route is incremented (525).Type: ApplicationFiled: May 13, 2011Publication date: March 14, 2013Applicant: Bull SASInventors: Sebastien Dugue, Jean-Vincent Ficet, Yann Kalemkarian, Nicolas Morey-Chaisemartin
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Publication number: 20130067114Abstract: A recommendation apparatus for determining, for a user, a set of one or more recommended paths through an information space in response to receiving from the user a path request message. Advantageously, in some embodiments, the path recommender apparatus determines a recommended path by analyzing a set of paths, where each path in the set was traversed by a person who is in a “social graph” belonging to the user (e.g., each path in the set was traversed by one of the user's Facebook friends). In this way, paths can be recommended to the user based on paths that are popular with the user's friends.Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Applicant: Telefonaktiebolaget L M Ericsson (publ)Inventors: Johan HJELM, Mattias LIDSTROM, Mona MATTI
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Publication number: 20130067115Abstract: A centralized host server domain can be setup to process all the A (Address) wildcard DNS records of matching non-existent domain names. The left-most label of the non-existent domain will be identified as the “DOMAIN PREFIX” and it will be extracted from the non-existent domain name of the Universal Resource Locator (URL) HTTP Request that is sent by a client. The host server will use the extracted “DOMAIN PREFIX” and perform a search against a centralized database where Domains' output URLs are defined and mapped to “DOMAIN PREFIX” values. The search result, which can be a single URL or multiple URLs, of the same or different protocol, will be sent back to the client as the Response. Domain Prefixes values and their associated keywords that are stored in the centralized database and mapped to output URLs will be accessed and utilized by new and existing internet resources search engines.Type: ApplicationFiled: September 12, 2012Publication date: March 14, 2013Inventor: Isaac Omar Lapanc
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Publication number: 20130067116Abstract: Described is a technology by which machines such as gaming (including media) systems are configured to synchronize streaming video between peers over a network, including participants communicating via voice or video chat. The video synchronization may include “full” synchronization that operates to synchronize streaming video that is currently unsynchronized video, by causing participants to stop and buffer, and resume playing from a specified position in the stream. Video synchronization also may include “fast” synchronization that operates to re-synchronize video that has begun to drift out of synchronization, such as by briefly pausing any stream that has gotten ahead of others. Also described is replicating the activation of a video transport control (e.g., pause, fast forward, rewind, skip, and the like) that occurs on one machine to other machines, such that video players behave as if there is a common remote control among the peer systems.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: MICROSOFT CORPORATIONInventor: Brian H. Ostergren
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Publication number: 20130067117Abstract: An expansion input/output device includes a body having a receiving space, an input unit, a second transmission unit, and a third transmission unit. A handheld electronic device can be received in the receiving space and functions as a computation processing center. The expansion input/output device integrates an input function of the input unit to provide a user-friendly input interface, and sends an audio/video signal of the handheld electronic device from a first transmission unit of the handheld electronic device to an external display device through the second transmission unit and the third transmission unit to provide a large display view. The expansion input/output device expands the applicability and integration capacity of the handheld electronic device and enhances ease of use thereof.Type: ApplicationFiled: October 25, 2011Publication date: March 14, 2013Inventors: KUO-CHAN PENG, CHING-FENG HSIEH
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Publication number: 20130067118Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventor: Mosaid Technologies Incorporated
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Publication number: 20130067119Abstract: A method for setting boot up configuration in an embedded system includes pulling the DP data pin of a USB interface to the ground by the embedded system, pulling the DM data pin of the USB interface to the ground by the embedded system, and booting up the embedding system into a special mode when at least one of the DP data pin or the DM data pin is externally pulled up above a threshold value.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Inventor: Chi Kwok Wong
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Publication number: 20130067120Abstract: Bidirectional (bidi) extension techniques for USB and/or other similar busses/connections are described in which an interface is provided to enable bidirectional communication with connected devices. The interface may be implemented as an operating system component to handle bidi communication for devices from multiple different independent hardware vendors (IHVs). Device drivers for different devices can be configured to include extension files in accordance with an established schema for bidi communication. The extension files describe supported bidi attributes, capabilities of the device, and how to make calls into the device. The interface operates to detect the extension files and set-up a corresponding device for bidi communication. Applications then interact through the interface to access, retrieve, and set configuration and status data for connected devices.Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Herman Richard Forrest, III, Michael P. Fenelon, Guillermo Eduardo Guillen, Frank Gorgenyi, Justin Hutchings
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Publication number: 20130067121Abstract: An electronic meeting tool for communicating arbitrary media content from users at a meeting includes a node configuration operating a display node of a communications network that is coupled to a display. The node configuration receives user selected arbitrary media content and controls display of the user selected arbitrary media content on the display. At least one peripheral device communicates the user selected arbitrary media content via the communications network. The peripheral device is a connection unit including a connector that couples to a port of a processing device having a second display, a memory and an operating system; and a transmitter communicating with the communications network. A program is provided to run on the operating system of the processing device and obtains user selected arbitrary media content, while leaving a zero footprint on termination.Type: ApplicationFiled: October 11, 2011Publication date: March 14, 2013Inventors: Koen Simon Herman Beel, Yoav Nir, Filip Josephine Johan Louwet, Guy Coen
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Publication number: 20130067122Abstract: An invention is disclosed for offloading operations, such data transfers, of a guest partition to a host partition. A guest operating system is presented with virtualized resources rather than physical resources—e.g. a guest virtualized processor, guest virtualized memory space, and a guest virtualized direct memory access (DMA) controller. The guest partition can detect the guest operation system attempt to initiate a data transfer, and can instruct the host partition to perform the data transfer. The guest partition need not perform the data transfer using the guest virtual resources. The host partition can perform the data transfer to a remote computing as instructed by the guest partition without copying the data to the host virtualized memory space. The host partition can provide a message to the guest partition indicative of a status of the data transfer.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventor: Vladimir Pavlov
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Publication number: 20130067123Abstract: Methods and structure for improved shipping of I/O requests among multiple storage controllers of a clustered storage system. Minimal processing of a received I/O request is performed in a first controller to determine whether the I/O request is directed to a logical volume that is owned by the first controller or to a logical volume owned by another controller. For requests to logical volumes owned by another controller, the original I/O request is modified to indicate the target device address of the other controller. The first controller then ships the request to the other controller and configures DMA capabilities of the first controller to exchange data associated with the shipped request between the other controller and memory of the host system.Type: ApplicationFiled: March 28, 2012Publication date: March 14, 2013Applicant: LSI CORPORATIONInventors: James A. Rizzo, Vinu Velayudhan, Adam Weiner, Basavaraj G. Hallyal, Gerald E. Smith
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Publication number: 20130067124Abstract: A method for synchronizing a host media player and a removable audio player, when the removable audio player is attached to the host media player, including receiving a new media file via an external connector in the host media player, wherein the new media file may be a digital audio file or a digital media file of a media type that the removable audio player is unable to play but the host media player is able to play, storing the new media file in a storage unit within the host media player, and conditionally copying the new media file to a storage unit within the removable audio player when the removable audio player is attached to the host media player, if the new media file is an audio file.Type: ApplicationFiled: September 13, 2012Publication date: March 14, 2013Inventor: Itay Sherman
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Publication number: 20130067125Abstract: Methods and structure for improved processing of fast path I/O requests in a clustered storage system. In a storage controller of a clustered storage system, the controller comprises a fast path I/O request processing circuit tightly coupled with host system drivers for fast processing of requests directed to storage devices of a logical volume. The controller also comprises a logical volume I/O processing stack (typically implemented as programmed instructions) for processing I/O requests from a host system directed to a logical volume. Based on detecting a change of ownership of a device or volume and/or a change to logical to physical mapping of a logical volume, fast path I/O requests may be converted to logical volume requests based on mapping context information within the fast path I/O request and shipped within the clustered storage system for processing.Type: ApplicationFiled: March 28, 2012Publication date: March 14, 2013Applicants: LSI CORPORATION, LSI CORPORATIONInventors: James A. Rizzo, Vinu Velayudhan, Adam Weiner, Gerald E. Smith
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Publication number: 20130067126Abstract: Systems and methods are disclosed herein for implementing one or more individual pressure sensitive keys that each support multiple native scan codes, with each scan code corresponding to a unique pressure level output. The disclosed systems and methods may be implemented in one exemplary embodiment to allow users to leverage the capability of a variable pressure keyboard by providing an information handling system having individual variable pressure keys that are each capable of outputting a different macro or multi-key sequence per key pressure level sensed.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Inventors: Mark A. Casparian, Carlos Ross, Danae Sierra, Karun Reddy, Larry E. Knepper
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Publication number: 20130067127Abstract: In an apparatus according to one embodiment of the present disclosure, a communications link comprises a first device and a second device communicating with each other via the communications link at a plurality of different speeds. However, prior to communicating via the communications link for the first time at a second speed, the first device and second device complete a first training cycle at the second speed. Further, during this first training cycle for the second speed, the first training cycle for the second speed will pause before the first training cycle at the second speed completes, and the first device and second device communicate at a first speed for a period of time before returning to the paused first training cycle at the second speed. When the paused first training cycle for the second speed continues, the first training cycle for the second speed will continue where it had paused.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: NVIDIA CORPORATIONInventors: Michael Hopgood, Wei-Je Huang, Mark Taylor, Hitendra Dutt, David Wyatt, Vishal Mehta
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Publication number: 20130067128Abstract: Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Inventor: Terence C. Sosniak
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Publication number: 20130067129Abstract: In a slave node, a signal processor stores therein wakeup information uniquely defined for the slave node. The signal processor includes a writing unit configured to write the wakeup information into the transceiver at a given timing. A transceiver includes a memory. The wakeup information is written into the memory to be held therein. The transceiver includes a wakeup determiner. The wakeup determiner compares information received via the communication bus with the wakeup information held in the memory if the slave node is operating in the sleep mode, and determines whether the slave node should shift to the wakeup mode according to a result of the comparison.Type: ApplicationFiled: September 12, 2012Publication date: March 14, 2013Applicant: DENSO CORPORATIONInventors: Hideki Kashima, Tomohisa Kishigami
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Publication number: 20130067130Abstract: An exemplary object is to make it possible to prompt notify a master-end control unit of failure information of a controlled device in a bus control apparatus that employs a structure in which a master-end circuit part is connected to a slave-end circuit part through a serial bus. A master circuit equipped with a control unit generates an access message for access to a control target equipped with a slave circuit, and transmits the access message to the slave circuit connected to the master circuit through a bus. The slave circuit collects information on the control target, generates a response message to the access message, generates an information message based on the information on the control target, and transmits the response message and the information message to the master circuit. If generation of the response message conflicts with generation of the information message, the slave circuit generates the information message, with a higher priority given to the generation of the information message.Type: ApplicationFiled: May 16, 2011Publication date: March 14, 2013Applicant: NEC CORPORATIONInventor: Yuichi Tazaki
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Publication number: 20130067131Abstract: A method of processing J1850 requests using a scan tool having multiple processor systems is provided. The scan tool includes a first processor that processes data according to scan tool functions to assist with diagnosing and repairing a vehicle. A second processor receives data transmitted to the first processor and stores the data in a buffer. The second processor determines whether the data is complete to enable the first processor to make a determination regarding the data.Type: ApplicationFiled: August 21, 2012Publication date: March 14, 2013Applicant: Service Solutions U.S. LLCInventor: David Vossen
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Publication number: 20130067132Abstract: In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed.Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Inventors: Jayakrishna Guddeti, Binata Bhattacharyya
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Publication number: 20130067133Abstract: A method and apparatus for processing data in which a function is processed using a processor operable to perform a plurality of functions is disclosed. When an interrupt is received during processing of the function at a point during the processing at which a portion of the function has been processed then a control parameter is accessed. In response to the control parameter having a value indicting that the function has idempotence processing of the function is stopped without processing the function further, and information on progress of the function is discarded such that following completion of the interrupt the portion of the function that has already been processed is processed again.Type: ApplicationFiled: November 18, 2011Publication date: March 14, 2013Applicant: Arm LimitedInventors: David Hennah MANSELL, Timothy Holroyd Glauert
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Publication number: 20130067134Abstract: A system and method are directed towards a pseudo multi-master operation on a serial bus. The pseudo multi-master operation allows multiple devices without standard multi-master functionality to operate on the serial bus as masters. In a disclosed example, the serial bus is an Inter-Integrated Circuit (I2C) bus, which is isolated when an adapter card requires access to the I2C bus, such as to update vital product data (VPD) to a memory device, and to cache the updated VPD to a chassis management module.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher H. Austen, Douglas M. Boecker, Joseph E. Bolan, Patrick L. Caporale, Brent W. Jacobs, Todd J. Rosedahl, Christopher L. Wood
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Publication number: 20130067135Abstract: A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to these pages becomes local as soon as possible. Various heuristics are described to enable different implementations for different situations or scenarios.Type: ApplicationFiled: November 6, 2012Publication date: March 14, 2013Applicant: VMWARE, INC.Inventor: VMware, Inc.
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Publication number: 20130067136Abstract: A computing system includes a number of memory modules and temperature sensors. Each temperature sensor measures a temperature of a memory module. In such a computing system a garbage collector during garbage collection, determines whether a temperature measurement of a temperature sensor indicates that a memory module is overheated and, if a temperature measurement of a temperature sensor indicates a memory module is overheated, the garbage collector reallocates one or more active memory regions on the overheated memory module to a non-overheated memory module. Reallocating the active memory regions includes copying contents of the active memory regions from the overheated memory module to the non-overheated memory module.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cary L. Bates, Nicholas P. Johnson, Justin K. King
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Publication number: 20130067137Abstract: Systems and methods that may be implemented to utilize the same portion of solid state nonvolatile memory for both managing system running data during a system working state and to store previous working state data written from system volatile memory during a low power state when the system volatile memory is depowered. The previous working state information may include data and instructions that may be employed to restore the previous working state of the information handling system prior to entering the low power state and terminating power to the system volatile memory.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Inventor: Michael K. Molloy
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Publication number: 20130067138Abstract: A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.Type: ApplicationFiled: October 3, 2011Publication date: March 14, 2013Applicant: OCZ TECHNOLOGY GROUP INC.Inventors: Franz Michael Schuette, William Ward Clawson
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Publication number: 20130067139Abstract: A storage system comprises a plurality of flash packages comprising a plurality of flash chips, and a storage controller for receiving a first write request from a higher-level apparatus and sending a second write request of write data based on data conforming to this first write request to a write-destination flash package, and demonstrates a capacity virtualization function for causing a storage capacity to appear larger than an actual storage capacity for the higher-level apparatus, and for configuring a storage space using page units. The storage system generates a second VOL (logical volume) based on a first VOL, manages a plurality of VOLs comprising the first VOL and one or more second VOLs generated based on the first VOL as a VOL group, and allocates the same page to areas of the same address of the plurality of VOLs configuring the VOL group.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: HITACHI, LTD.Inventors: Akira Yamamoto, Masayuki Yamamoto
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Publication number: 20130067140Abstract: A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.Type: ApplicationFiled: October 13, 2011Publication date: March 14, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: OMPRAKASH BISEN, ABDULLA PICHEN
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Publication number: 20130067141Abstract: A data writing method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of lower physical pages and a plurality of upper physical pages respectively corresponding to the lower physical pages. The method includes determining whether a physical page is one of the upper physical pages before writing first data into the physical page; determining whether a backup area stores second data written into one of the lower physical pages corresponding to the physical page if the physical page is the upper physical page; reading the second data from the lower physical page corresponding to the physical page and backing up the second data into the backup area before writing the first data into the physical page when the backup area does not store the second data. Accordingly, the method may effectively prevent data loss due to a program failure.Type: ApplicationFiled: December 12, 2011Publication date: March 14, 2013Applicant: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Publication number: 20130067142Abstract: A method of judging problem storage regions adapted for a flash memory storage device includes steps of: sending a writing order to a flash memory chip for writing a written data to an appointed storage paging; when the flash memory chip beginning writing the written data to the appointed storage paging, getting the first time; when the flash memory chip finishing writing the written data to the appointed storage paging, getting the second time; calculating a writing time according to the first time and the second time; if the writing time not coincident with a standard value, then labeling the appointed storage paging as a problem storage region and copying the written data to a backup paging; updating a Mapping Table.Type: ApplicationFiled: March 21, 2012Publication date: March 14, 2013Applicant: A-DATA TECHNOLOGY (SUZHOU) CO.,LTD.Inventors: Young-Joon Choi, Kuo-Chung Liao, Yen-Hsin Liu, Chiang-Chang Hsien, Yun-Hui Wang, Chih-Ming Hsu
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Publication number: 20130067143Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a command storage module in which a command is stored, and a controller which receives the command from a host device, stores the command in the command storage module, executes the command stored in the command storage module, and after having completed the execution of the command, transmits, to the host device, a first signal reporting the completion of the execution of the command.Type: ApplicationFiled: March 22, 2012Publication date: March 14, 2013Inventors: Misao HASEGAWA, Atsushi Shiraishi
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Publication number: 20130067144Abstract: According to one embodiment, a controller for a storage apparatus is disclosed having interfaces connectable to a host system, a first storage apparatus and a second storage apparatus. A data in the first storage apparatus and a data in the second storage apparatus are duplicates. A status table stores the operating state regarding the first storage apparatus and the second storage apparatus, wherein the operating state indicates among writing, reading, or standing by. A monitor monitors the interfaces and set up the operating state into the status table. A buffer memory buffers the data for writing in the first storage apparatus and the second storage apparatus. A command response unit receives the data for writing and write-in request from a host system, and directs the writing of the data to the first storage apparatus and the second storage apparatus while making the buffer memory buffer the received data.Type: ApplicationFiled: August 6, 2012Publication date: March 14, 2013Inventors: Yoshiki Namba, Hiroyuki Nishikawa, Taichi Tashiro, Keiji Yamamoto, Kohta Nakamura
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Publication number: 20130067145Abstract: Provided is a memory device configured to store data having a first characteristic and a second characteristic in a memory region optimized to store data having the first characteristic and the second characteristic. The memory device includes a plurality of memory regions and a region determination unit configured to receive data, select a memory region appropriate for storing the received data, and store the data in the selected memory region. Correspondingly, performance degradation of the memory device may be prevented.Type: ApplicationFiled: August 23, 2012Publication date: March 14, 2013Inventors: Byoung-Sul Kim, Myong-Jae Kim, Woo-Il Kim
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Publication number: 20130067146Abstract: During normal power operation, an erased free block is prepared in nonvolatile memory so that at least one erased free block is continuously available as a standby block. If a power failure occurs, volatile data and its address conversion information are written into the standby block in the nonvolatile memory.Type: ApplicationFiled: August 31, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Tatsuya Zettsu
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Publication number: 20130067147Abstract: A storage device of the embodiment includes memory, a control section, a table holding section for managing a table for holding an identifier, a logical address, and a data length based on a read command, an issuing section for issuing the logical address and the data length for each identifier to the control section, a buffer for holding data received from the memory along with the identifier, and an identifier queue for receiving the identifier of a number proportional to a data length when the data of the logical address of the same identifier is received in the buffer. The storage device of the embodiment includes a transfer section for transferring the data corresponding to the identifier received in the buffer to outside when the identifier is held as incomplete readout in the table in order from the identifier at a head of the identifier queue.Type: ApplicationFiled: September 7, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Kazuhito OKITA
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Publication number: 20130067148Abstract: An information processing apparatus includes an assignment unit and a determination unit. The assignment unit evaluates physical properties of each of a plurality of semiconductor memories constituting one storage device as a whole and assigns a usage attribute corresponding to an evaluation result to at least a part of the plurality of semiconductor memories. The determination unit determines a semiconductor memory having an optimal usage attribute as a write destination of data with respect to a write command of the data.Type: ApplicationFiled: September 12, 2012Publication date: March 14, 2013Applicant: Sony CorporationInventors: Yoshinori Takagi, Ichiro Ogata, Hirofumi Hibi, Yoshihiro Tamura, Daisuke Izaki, Kyosuke Yoshida
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Publication number: 20130067149Abstract: A method for managing a storage device including determining whether the storage device includes a non-volatile cache, scanning for a clear cache instruction received from a computing machine, and clearing the non-volatile cache on the storage device in response to authenticating the clear cache instruction.Type: ApplicationFiled: April 12, 2010Publication date: March 14, 2013Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Leonard E. Russo, Walter A. Gaspard, Walter W. Bellamy
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Publication number: 20130067150Abstract: A data processor includes a flash memory, a random access memory (RAM), and a controller that creates free space information of the flash memory, creates record data according to each of a read latest data of the flash memory, and stores the free space information and the record data into the RAM.Type: ApplicationFiled: November 5, 2012Publication date: March 14, 2013Applicant: Renesas Electronics CorporationInventor: Renesas Electronics Corporation
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Publication number: 20130067151Abstract: A method includes writing a first portion of received user data to a first page of a block of a memory according to a writing schedule and writing a subsequent portion of the received user data to another page of the block according to the writing schedule. The method includes storing first metadata corresponding to writing the first portion in the memory. The method further includes associating the first metadata with the subsequent portion.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Applicant: SANDISK IL LTD.Inventor: SANDISK IL LTD.
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Publication number: 20130067152Abstract: The temporary area capacity required to be secured with respect to the whole permanent area is calculated in accordance with the capacity and access frequency of a host computer data permanent area of a disk device contained in the storage system and a disk device of an external storage device that is managed by a storage virtualization function of this storage system. The nonvolatile memory is defined as the temporary area and is used to temporarily store host computer data when a data I/O from the host computer is processed. The required capacity of the temporary area is re-calculated in accordance with an event such as a configuration change in the external storage system.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Applicant: HITACHI, LTD.Inventor: Yasutomo Yamamoto
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Publication number: 20130067153Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Applicant: SPANSION LLCInventor: Tzungren Tzeng
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Publication number: 20130067154Abstract: An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Applicant: NETAC TECHNOLOGY CO., LTD.Inventor: NETAC TECHNOLOGY CO., LTD.
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Publication number: 20130067155Abstract: A computing system includes computer memory of a number of different memory types. An application program compiled for execution on the computing system controls access to a field of a record in the computer memory of the computing system by defining a record that includes one or more fields, the one or more fields including a restricted field having a specification of restricted accessibility when the restricted field is allocated in a particular memory type; allocating an instance of the record in memory of the particular memory type; and denying each attempted access of the restricted field while the record is allocated in the particular memory type.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cary L. Bates, Nicholas P. Johnson, Justin K. King
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Publication number: 20130067156Abstract: In general, embodiments of the present invention provide a double data rate (DDR) controller having a shared address and separate data error direction for DDR3 direct memory access (DMA). In a typical embodiment, the architecture described herein comprises a fields programmable gate array (FPGA) having a single memory controller coupled to a data multiplexer (MUX). Groups/sets of memory having individual dual inline memory modules (DIMMs) are coupled to the memory controller and the data MUX. Data flows between the DIMMs and the data multiplexer, while address and control information flows between the DIMMs and the memory controller.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Inventor: Byungcheol Cho
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Publication number: 20130067157Abstract: Embodiments of the present invention provide a semiconductor storage device (SSD)-based storage system. Specifically, in a typical embodiment, the system comprises a SSD memory disk unit having (among other components) a plurality of host interface units coupled to a host interface controller. The plurality of host interface units communicate with a plurality of physical interface units of a device driver (e.g., on a one-to-one or one-to-multiple basis). The device driver also comprises a logical interface coupled to the plurality of physical interface units. Among other things, this allows the system to connect to multiple hosts. In addition, this design provides increased bandwidth.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Inventor: Byungcheol Cho
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Publication number: 20130067158Abstract: A mechanism is provided for tape writing of small transactions. A first file is written as a plurality of fixed-length data sets (DS), the DS number of the final DS in the plurality of DS is stored in memory as #N(DS#N) and the WP number as #M(WP#M), and the final first file and the second file in the DS following the final DS(DS#N, WP#M) containing the first file are packed and written in sequential DS units, and are stored as DS#N, DS#N+1, etc, and WP#M+1 in sequential order in DS containing the second file. The remaining first, second, or third file is packed and DS#N with WP#M is overwritten as DS#N with WP#M+2, and the remaining #N in the DS numbers of the second file and the third file in the subsequent DS are written as DS#N+1, N+2, etc. with WP#M+2, and the DS#N, #N+1, #N+2, etc. with WP+M+2 are stored.Type: ApplicationFiled: March 23, 2011Publication date: March 14, 2013Applicant: International Business Machines CorporationInventors: Takamasa Hirata, Setsuko Masuda, Yuhko Mori, Yutaka Oishi, Terue Watanabe
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Publication number: 20130067159Abstract: The storage devices of a storage device set (e.g., a RAID array) may generate a nonvolatile representation of the configuration of the storage device set, including logical disks, spaces, storage pools, and layout and provisioning plans, on the physical media of the storage devices. A computer accessing the storage device set may also generate a volatile memory representation of the storage device set to use while accessing the storage devices; however, the nonvolatile representation may not be performant due to its different usage and characteristics. Presented herein are techniques for accessing the storage device set according to a volatile memory representation comprising a hierarchy of logical disks, slabs, and extents, and an accessor comprising a provisioning component that handles slab accesses while applying provisioning plans, and that interfaces with a lower-level layout component that translates slab accesses into storage device accesses while applying layout plans to the storage device set.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventor: Karan Mehra
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Publication number: 20130067160Abstract: A method includes producing values with a producer thread, and providing a queue data structure including a first array of storage locations for storing the values. The first array has a first tail pointer and a first linking pointer. If a number of values stored in the first array is less than a capacity of the first array, an enqueue operation writes a new value at a storage location pointed to by the first tail pointer and advances the first tail pointer. If the number of values stored in the first array is equal to the capacity of the first array, a second array of storage locations is allocated in the queue. The second array has a second tail pointer. The first array is linked to the second array with the first linking pointer. An enqueue operation writes the new value at a storage location pointed to by the second tail pointer and advances the second tail pointer.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: MICROSOFT CORPORATIONInventors: Igor Ostrovsky, Stephen H. Toub
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Publication number: 20130067161Abstract: Methods and structure for task management in storage controllers of a clustered storage system. An initiator storage controller of the clustered storage system ships I/O requests for processing to a target storage controller of the system. Responsive to a need to abort a previously shipped I/O request, the initiator storage controller transmits a task management message to the target storage controller. The task management message identifies one or more previously shipped I/O requests to be aborted. The target storage controller processes the received task management message in due course of processing requests and completes processing for the aborted previously shipped request in an orderly manner. Resources associated with the aborted previously shipped requests are release within both controllers.Type: ApplicationFiled: March 28, 2012Publication date: March 14, 2013Applicants: LSI CORPORATION, LSI CORPORATION, LSI CORPORATION, LSI CORPORATION, LSI CORPORATIONInventors: Rakesh Chandra, James A. Rizzo, Vinu Velayudhan, Senthil M. Thangaraj, Sumant K. Patro