Patents Issued in March 14, 2013
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Publication number: 20130067162Abstract: Methods and structure for load balancing of background tasks between storage controllers are provided. An exemplary active storage controller comprises a front-end interface that receives host Input/Output (I/O) requests directed to a logical volume, a back-end interface that couples with one or more of storage devices provisioning the logical volume, and a control unit. The control unit processes the host I/O requests directed to the logical volume, identifies a background processing task distinct from the host I/O requests and related to the logical volume, and assigns the background processing task to a passive storage controller for processing.Type: ApplicationFiled: March 28, 2012Publication date: March 14, 2013Applicant: LSI CORPORATIONInventors: Raja Jayaraman, James A. Rizzo, Rakesh Chandra, Vinu Velayudhan, Phillip V. Nguyen
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Publication number: 20130067163Abstract: Methods and systems for transferring ownership of a logical volume in a storage system comprising multiple storage controllers is provided. According to the method, the storage controllers are coupled for communication with a logical volume, wherein at least one storage device coupled with the storage controllers implements the logical volume. The method comprises identifying, at a first storage controller, a second storage controller to receive the logical volume. The method also comprises initiating a transfer of ownership of the logical volume from the first storage controller to the second storage controller by transferring metadata stored in a memory of the first storage controller to the second storage controller, the metadata existing in a native format that describes the configuration of the logical volume on the at least one storage device.Type: ApplicationFiled: March 28, 2012Publication date: March 14, 2013Inventors: Vinu Velayudhan, James A. Rizzo, Basavaraj G. Hallyal, Guolin Huang, Sumant K. Patro
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Publication number: 20130067164Abstract: Methods and system are provided for exposing logical volumes to host systems and storage controllers in a consistent manner across a clustered storage system. One embodiment is a storage controller. The storage controller is operable to communicate with other storage controllers within the clustered storage system. The storage controller is further operable to generate a proposed Logical Unit Number (LUN) for a logical volume provisioned at the storage devices, and to communicate with each of the other storage controllers within the clustered storage system requesting that the other storage controllers determine if the proposed LUN is in use. If the proposed LUN is not in use, then storage controller assigns the proposed LUN to the logical volume. If the LUN is in use, then the storage controller generates a new proposed LUN and re-tries communication with the other storage controllers until a unique LUN is found.Type: ApplicationFiled: March 28, 2012Publication date: March 14, 2013Inventors: Vinu Velayudhan, James A. Rizzo, Adam Weiner, Rakesh Chandra, Guolin Huang
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Publication number: 20130067165Abstract: A disk array device includes hard disks from which RAID groups are configured. Therein, a volume setting unit sets one or more used areas. A data check control unit determines, on the basis of the state into which the used areas have been set, which areas in the RAID groups are subject to a diagnosis. A data check execution unit that executes a cyclical diagnosis on the areas determined, by the data check control unit, to be those subject to a diagnosis.Type: ApplicationFiled: July 25, 2012Publication date: March 14, 2013Applicant: Fujitsu LimitedInventors: Hidejirou DAIKOKUYA, Kazuhiko Ikeuchi, Chikashi Maeda, Takeshi Watanabe, Norihide Kubota, Atsushi Igashira, Kenji Kobayashi, Ryota Tsukahara
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Publication number: 20130067166Abstract: In a virtual computer system controlling a disk volume and a virtual server which is connected to the disk volume, to which the area of the disk volume is allocated as a virtual disk and which executes a process using the allocated virtual disk, the virtual computer system erases information stored in the virtual disk allocated to the virtual server to be deleted correspondingly with the deletion of the virtual server. An administrative server may be provided to select a server system which is low in load from among plural server systems controlling virtual servers as a server system for erasing information stored in the virtual disk allocated to the virtual server to be deleted.Type: ApplicationFiled: September 14, 2012Publication date: March 14, 2013Inventors: Eri KATAOKA, Yoshifumi Takamoto
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Publication number: 20130067167Abstract: Embodiments of archival storage system are disclosed. The archival storage system includes one or more removable disk drives that provide random access and are readily expandable. In embodiments, some or all of the data within the removable disk drive(s) is immutable. The archiving system creates a designation for the data representing the data as having Write Once Read Many (WORM) protection. Actions associated with the data may be received and determined to be read accesses. If the actions are something other than a read access, the archiving system, in embodiments, prevents the action on the data.Type: ApplicationFiled: September 12, 2012Publication date: March 14, 2013Applicant: Imation Corp.Inventors: Matthew D. Bondurant, Payman Dadashpour
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Publication number: 20130067168Abstract: Aspects of the subject matter described herein relate to caching data for a file system. In aspects, in response to requests from applications and storage and cache conditions, cache components may adjust throughput of writes from cache to the storage, adjust priority of I/O requests in a disk queue, adjust cache available for dirty data, and/or throttle writes from the applications.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Sarosh Cyrus Havewala, Apurva Ashwin Doshi, Neal R. Christiansen, Atul Pankaj Talesara
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Publication number: 20130067169Abstract: An apparatus for controlling operation of a cache includes a first command queue, a second command queue and an input controller configured to receive requests having a first command type and a second command type and to assign a first request having the first command type to the first command queue and a second command having the first command type to the second command queue in the event that the first command queue has not received an indication that a first dedicated buffer is available.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORP
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Publication number: 20130067170Abstract: A method and computer readable medium are disclosed for predictive caching of web pages for display through a screen of a mobile computing device. A load request is received at a mobile computing device, where the load request includes a current timestamp and an address. The address points to a remote server storing a current copy of the address content. The mobile computing device determines whether there is an existing copy of the address content is pre-cached on the mobile computing device. The mobile computing device determines whether a difference between the current timestamp and a pre-cache timestamp is greater than a heuristic timeliness value. If it is, the mobile computing device pre-caches the current copy of the address content from the remove server at the address on the mobile computing device. The mobile computing device then provides the current copy of the address content for display on its screen.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Inventor: Yin Zin Mark Lam
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Publication number: 20130067171Abstract: The invention discloses a data storage system and managing method thereof. The data storage system according to the invention includes N storage devices, a backup memory and a controller where N is a natural number. Each storage device has a respective write cache. Once the data storage system suffers from power failure, the backup memory still reserves data stored therein. The controller receives data transmitted from an application I/O request unit, executes a predetermined operation for the received data to generate data to be written, transmits the data to be written to the write caches of the storage devices, duplicates the data to be written into the backup memory, and labels the duplicated data in the backup memory as being valid in response to a writing confirm message sent from the storage devices.Type: ApplicationFiled: February 17, 2012Publication date: March 14, 2013Applicant: PROMISE TECHNOLOGY, INC.Inventors: Hung-Ming Chien, Che-Jen Wang, Yi-Hua Peng
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Publication number: 20130067172Abstract: Methods and structure for improved buffer management in a storage controller. A plurality of processes in the controller each transmits buffer management requests to buffer management control logic. A plurality of reserved portions and a remaining non-reserved portion are defined in a shared pool memory managed by the buffer management control logic. Each reserved portion is defined as a corresponding minimum amount of memory of the shared pool. Each reserved portion is associated with a private pool identifier. Each allocation request from a client process supplies a private pool identifier for the associated buffer to be allocated. The buffer is allocated from the reserved portion if there sufficient available space in the reserved portion identified by the supplied private pool identifier. Otherwise, the buffer is allocated if sufficient memory is available in the non-reserved portion. Otherwise the request is queued for later re-processing.Type: ApplicationFiled: March 28, 2012Publication date: March 14, 2013Applicant: LSI CORPORATIONInventors: James A. Rizzo, Vinu Velayudhan, Adam Weiner, Rakesh Chandra, Phillip V. Nguyen
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Publication number: 20130067173Abstract: A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to different physical memory banks, among the plurality of memory banks, and scheduling the selected subset of access requests, each over a separate access port.Type: ApplicationFiled: August 2, 2012Publication date: March 14, 2013Applicant: Cavium, Inc.Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Najeeb I. Ansari, Ahmed Shahid
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Publication number: 20130067174Abstract: The storage of data sets in a storage set (e.g., data sets written to hard disk drives comprising a RAID array) may diminish the performance of the storage set through non-sequential writes, particularly if the storage devices promptly write data sets that are followed by sequentially following data sets. Additionally, storage sets may exhibit inconsistencies due to non-atomic writes of data sets and verifiers (e.g., checksums) and an intervening failure, such as an occurrence of the RAID write hole. Instead, data sets and verifiers may first be written to a stored on the nonvolatile media of a storage device before being committed to the storage set. Such writes may be sequentially written to the journal, irrespective of the locations of the data sets in the storage set; and recovery of a failure may simply involve re-committing the consistent records in the journal to correct incomplete writes to the storage set.Type: ApplicationFiled: September 11, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Darren Moss, Karan Mehra, Rajeev Nagar, Surendra Verma, Shiv Rajpal
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Publication number: 20130067175Abstract: Method and system for partially cloning a data container with compression is provided. A storage operating system determines if a portion of a source data container that is to be cloned includes a plurality of compressed blocks that are compressed using a non-variable compression group size. The operating system clones the plurality compressed blocks with the non-variable compression group size and de-compresses a plurality of blocks of the data container that are not within the non-variable compression group size. The plurality of compressed blocks and the plurality of blocks that are not within the non-variable compression group size are then stored as a partially cloned copy of the source data container.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Inventors: Sandeep Yadav, Dnyaneshwar Pawar, Anand Natarajan
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Publication number: 20130067176Abstract: In an information processing device according to an embodiment, a generating unit generates a descriptor including information indicating an area in a storage unit and state information indicating a state of an entry in which the information indicating the area is stored, and an update unit updates the state information according to at least one of writing and reading of data to the area indicated in the entry selected according to the state information by the input/output unit. The generating unit generates the descriptor in advance before at least one of writing and reading of data to/from the storage unit is started.Type: ApplicationFiled: February 27, 2012Publication date: March 14, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Nobuhiko Sugasawa, Masataka Goto, Yuta Kobayashi, Shinichi Baba
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Publication number: 20130067177Abstract: An information processing method includes: grouping temporarily consecutive data into a plurality of groups based on a reference defined in advance and storing the grouped data; reading, in response to an access request from an external apparatus, target data to be a target of the request from a first group including the target data and outputting the read target data to the external apparatus; and reading, in response to the reading of the target data, at least part of data from a second group different from the first group as read-ahead target data.Type: ApplicationFiled: September 12, 2012Publication date: March 14, 2013Applicant: Sony CorporationInventors: Kyosuke Yoshida, Yoshihiro Tamura, Ichiro Ogata, Yoshinori Takagi, Hirofumi Hibi, Daisuke Izaki
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Publication number: 20130067178Abstract: A system and method for generating a triage dump of useful memory data from a computer that encounters an error while executing one or more software programs. The computer system may identify data values within the triage dump that are characteristic of personal data. To protect the privacy of the software user the personal data may be poisoned by overwriting the data values with overwrite values. The overwrite values used to poison the data values may be predetermined, based on the data values themselves, or chosen at random. The triage dump may be sent to an external server to associated with the developer of the one or more software programs for analysis. When overwrite values are dynamically selected, the specific overwrite values used may be sent to the server in connection with a triage dump.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Miklos Szegedi, Ryan S. Kivett, Gregory W. Nichols, Mikhail Basilyan, Jen-Lung Chiu, Genghis Karimov
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Publication number: 20130067179Abstract: A storage set (e.g., an array of hard disk drives) may experience a failure, such as a loss of power, a software crash, or a disconnection of a storage device, while writes to the storage set are in progress. Recover from the failure may involve scanning the storage set to detect and correct inconsistencies (e.g., comparing mirrors of a data set or testing checksums). However, lacking information about the locations of pending writes to the storage set during the failure, this “cleaning” process may involve scanning the entire storage set, resulting in protracted recovery processes. Presented herein are techniques for tracking writes to the storage set by apportioning the storage set into regions of a region size (e.g., one gigabyte), and storing on the nonvolatile storage medium descriptors of “dirty” regions comprising in-progress writes. The post-failure recovery process may then be limited to the regions identified as dirty.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Emanuel Paleologu, Karan Mehra, Darren Moss
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Publication number: 20130067180Abstract: The objects of an archive may be verified with a cryptographic signature stored in the archive. However, when an object is extracted, the authentication involves re-authenticating the entire archive, re-extracting the object, and comparing the extracted object with the current object, which is inefficient or unachievable if the archive is unavailable. Instead, the archive may include a block map signed with the signature and comprising hashcodes for respective blocks of the objects of the archive. When an object is extracted, the signature and block map may also be extracted and stored as objects outside of the archive. The extracted signature and block map may later be verified by authenticating the signature, verifying the block map with the signature, and matching the hashcodes of the block map with those of the blocks of the extracted objects, thus enabling a more efficient and portable verification of extracted object with extracted authentication credentials.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Simon Wai Leong Leet, Sarjana Bharat Sheth, Patrick T. O'Brien, JR., Jack R. Davis
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Publication number: 20130067181Abstract: An approach is provided for providing criticality based data backup. A data backup platform determines one or more state trajectories associated with one or more information management processes operating on at least one information space. The data backup platform further processes and/or facilitates a processing of the one or more state trajectories to determine criticality information associated with one or more data items of the at least one information space. The data backup platform also determines (a) one or more data backup processes, (b) one or more data restoration processes, (c) one or more parameters for the one or more data backup processes, the data restoration processes, or a combination thereof, or (d) a combination thereof based, at least in part, on the criticality information.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: Nokia CorporationInventors: Sergey Boldyrev, Pavandeep Kalra
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Publication number: 20130067182Abstract: A data processing method includes storing data as segments. Data requiring processing is identified. Related data segments are identified and copied to storage in an analysis module. The module reviews the data, identifies required analysis tasks and stores the identified tasks in task storage in the module. The module reviews the tasks to identify required data. The module identifies any required data not stored in the module, and required data is copied to the module. The analysis module executes required task. The module removes executed tasks and updates the data in module storage based on the analysis output. The module reviews data in module storage to identify what analysis must be carried out on the identified data. When an analysis tasks stops, the data store is updated based on the updated module data. The data store comprises storage media and the analysis modules are executed in random access memory.Type: ApplicationFiled: September 7, 2012Publication date: March 14, 2013Applicant: ONZO LimitedInventor: Adam Richard Westbrooke
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Publication number: 20130067183Abstract: The present invention transfers replication logical volumes between and among storage control units in a storage system comprising a plurality of storage control units. To transfer replication logical volumes from a storage control unit to a storage control unit, a virtualization device sets a path to the storage control unit. The storage control unit then prepares a differential bitmap in order to receive access requests. When the preparation is completed, the virtualization device makes access requests to the storage control unit. The storage control unit then hands over the access requests to the storage control unit. Subsequently, the storage control unit performs a process so that the access requests are reflected in a disk device and performs an emergency destage of storing data in a cache memory into disk device. When the emergency destage is ended, the storage control unit connects to an external storage control unit and hands over access requests to the external storage control unit.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Applicant: Hitachi, Ltd.Inventor: Hitachi, Ltd.
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Publication number: 20130067184Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.Type: ApplicationFiled: March 6, 2012Publication date: March 14, 2013Inventors: Scott H. Robinson, Gustavo P. Espinosa, Steven M. Bennett
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Publication number: 20130067185Abstract: Memory management by garbage collection involves a memory area that is allocated in a computer. Data is created in the memory area in accordance with a program executed by a processor of the computer, and it is checked whether or not data necessary to execute the program exists in the memory area to be released, in response to an explicit instruction to release the memory area. As a result of the check, if data necessary to execute the program does not exist in the memory area, the memory area is released. As a result of the check, if data necessary to execute the program exists in the memory area, the data is moved to a memory area different from the memory area to be released.Type: ApplicationFiled: November 2, 2012Publication date: March 14, 2013Inventors: Motoki OBATA, Hiroyasu NISHIYAMA, Kei NAKAJIMA, Koichi OKADA, Takuma NAGASE
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Publication number: 20130067186Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Steve Pronovost, Maxwell Abernethy, Rudolph Balaz, Ameet Chitre
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Publication number: 20130067187Abstract: A storage device set may allocate capacity for spaces (e.g., logical volumes) according to an allocation strategy, e.g., allocating capacity from the storage device having the greatest available capacity, or maximizing the distribution of allocated capacity across the storage devices. However, such allocation strategies may be inefficient (e.g., limiting the capability of the storage device set to satisfy subsequent requests with constraints such as a minimum distribution of capacity across several storage devices). The techniques presented herein achieve efficient allocation by first allocating capacity on storage devices having ample available capacity using a round-robin technique, and if such storage devices do not satisfy the capacity request, allocating capacity on storage devices having limited available capacity.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Darren Moss, Karan Mehra, Emanuel Paleologu
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Publication number: 20130067188Abstract: The representation of storage devices on computers (e.g., as logical volumes) may be complicated by the pooling of multiple storage devices in order to apply redundancy plans such as mirroring and checksumming. Presented herein is a storage device driver configured to operate as a storage device interface generating representations of the storage regions of the storage devices; to claim those regions as a storage controller; and to expose pooled storage regions as logical disks. Additionally, the storage device driver may support the inclusion of storage devices in a cluster, comprising nodes that may be appointed as managers of the storage pool configuration; as managers of the storage devices; as owners having exclusive read/write access to the storage pool or cluster resources; and as cluster resource writers having excusive write access to a cluster resource. The nodes of the cluster may interoperate to share the storage devices while avoiding write conflicts.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Karan Mehra, Rajeev Nagar, Shiv Rajpal, Darren Moss, Andrea D'Amato, Alan Warwick, Vyacheslav Kuznetsov
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Publication number: 20130067189Abstract: A method for initializing a memory subsystem (212) of a management controller (200) includes, with an additional memory initialization module (206) of the management controller (200), initializing the memory subsystem (212) of the management controller (200) in response to the memory subsystem (212) not being properly initialized. A management controller (200) includes a memory subsystem (212) including a memory controller (214) and a memory (216); firmware (208) able to initialize the memory subsystem (212); and a memory initialization module (206) to initialize the memory subsystem (212) if the memory subsystem (212) is not properly initialized.Type: ApplicationFiled: May 28, 2010Publication date: March 14, 2013Inventors: David F. Heinrich, Theodore F. Emerson, Hung Q. Le
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Publication number: 20130067190Abstract: A method for creating a buffer of a special class for accessing a specified memory space. The method includes the steps of: creating, by a processor of the computer system, a buffer of a special class, the buffer including a memory space that the processor is not permitted to access; and creating, by the processor, an accessible buffer of the class in access-permitted memory space by slicing off a portion of a created buffer of the class in response to a designation of the access-permitted memory space and size, where the processor includes: the special class for the buffer for accessing a memory space specified by an absolute address; and a function to create the class by slicing off the portion of the memory space specified by the class.Type: ApplicationFiled: September 7, 2012Publication date: March 14, 2013Applicant: International Business Machines CorporationInventors: Thomas R. Gissel, Hiroshi Horii
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Publication number: 20130067191Abstract: A set of storage devices may interoperate to share a pool of storage space, such as in a Redundant Array of Inexpensive Disks (RAID) scheme. However, the details of the representation of the pool and the allocation of capacity to the pool may enable advantages and/or impose limitations on the storage set. Presented herein are techniques for generating a representing a pooled partition on one or more storage devices featuring a pool configuration representing the pool as a set of spaces manifested by the pool; a set of storage devices sharing the pool; and a set of extents that map physical areas of the storage devices to logical areas of the spaces. The flexibility of these pooling techniques may enable such features as flexible capacity allocation, delayed binding, thin provisioning, and the participation of a storage device in two or more distinct pools shared with different sets of storage devices.Type: ApplicationFiled: September 11, 2011Publication date: March 14, 2013Applicant: Microsoft CorporationInventors: Karan Mehra, Emanuel Paleologu
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Publication number: 20130067192Abstract: Systems and methods for identifying objects generated during program execution are provided. In one embodiment, the method comprises examining one or more data structures that include information about allocation of memory space to one or more objects; determining address space allocated to at least one of said objects based on examining said data structure; populating a reverse object map based on the examining of the one or more data structures and the determining of the address space allocated to said objects, such that one or more addresses in memory are associated with an object instantiated during program execution; and determining identity of a target object accessed during program execution in association with a respective address, in response to evaluating the respective address against the reverse object map to find the target object.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: International Business Machines CorporationInventor: Yaakov Yaari
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Publication number: 20130067193Abstract: An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Michael Kagan, Ariel Shahar, Noam Bloch
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Publication number: 20130067194Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.Type: ApplicationFiled: November 8, 2012Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORP
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Publication number: 20130067195Abstract: A method for maintaining context-specific symbols in a multi-core or multi-threaded processing environment may include, but is not limited to: partitioning a virtual address space into at least one portion associated with the storage of one or more context-specific symbols accessible by at least a first processing core and a second processing core; defining at least one context-specific symbol; storing the at least one context specific symbol to the at least one portion of the virtual address space; and mapping the virtual address of the at least one context-specific symbol to both a physical address associated with the first processing core and a physical address associated with the second processing core.Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Applicant: LSI CORPORATIONInventors: Kapil Sundrani, Chethan Tatachar
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Publication number: 20130067196Abstract: A method of operating a computer processor includes storing at least one machine level vector instruction in a memory and replacing a plurality of machine level scalar instructions in a computer program with the at least one machine level vector instruction during execution of the computer program based on execution addresses associated with the plurality of machine level scalar instructions and/or instruction opcodes associated with the plurality of machine level scalar instructions.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: QUALCOMM IncorporatedInventors: Gerald Paul Michalak, Charles Dave Estes
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Publication number: 20130067197Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units CPUs and one node controller NC, where any two CPUs in each basic node are interconnected, each CPU in each basic node is connected to the NC in the basic node, the NC in each basic node has a routing function, any two NCs in the M basic nodes are interconnected, and a connection between the L composite nodes formed through a connection between NCs enable communication between any two NCs to require at most three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Applicant: Huawei Technologies Co., Ltd.Inventor: Huawei Technologies Co., Ltd.
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Publication number: 20130067198Abstract: A parallel computer is provided that includes a collection of compute nodes organized as a tree, including: initiating a collective gather operation by a logical root of the collection of compute nodes, including adding result data of the logical root to a gather buffer; for each compute node in the collection of compute nodes, determining whether result data of the compute node is already written in the gather buffer; and if the result data of the compute node is already written in the gather buffer, incrementing a counter assigned to that result data already written in the gather buffer; and if the result data of the compute node is not already written in the gather buffer, writing the result data of the compute node as new result data in the gather buffer, incrementing a counter assigned to that new result data, and writing in the gather buffer a node ID.Type: ApplicationFiled: November 1, 2012Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: International Business Machines Corporation
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Publication number: 20130067199Abstract: A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.Type: ApplicationFiled: March 6, 2012Publication date: March 14, 2013Applicant: VIA TECHNOLOGIES, INC.Inventors: G. Glenn Henry, Terry Parks, Rodney E. Hooker
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Publication number: 20130067200Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.Type: ApplicationFiled: September 14, 2012Publication date: March 14, 2013Inventors: Salvador PALANCA, Stephen A. FISCHER, Subramaniam MAIYURAN, Shekoufeh QAWAMI
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Publication number: 20130067201Abstract: The multiprocessor system includes one or a plurality of main processors and a plurality of sub-processors, and an execution control circuit which conducts execution control of each the sub-processors, wherein the execution control circuit includes an execution control processor for execution control processing of each the sub-processors, a control bus output unit for activation of a command to each the sub-processors, a status bus input unit for status notification from each the sub-processors, a determination circuit which determines whether or not the status notification has one-to-one dependency with a processing command to be issued next on an operation sequence and is to be processed at a high speed, a status accelerator which issues a corresponding processing activation command when the status notification is to be processed at a high speed, and a status FIFO control unit which processes the status notification by using the execution control processor.Type: ApplicationFiled: May 24, 2011Publication date: March 14, 2013Applicant: NEC CORPORATIONInventors: Toshiki Takeuchi, Hiroyuki Igura
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Publication number: 20130067202Abstract: A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction.Type: ApplicationFiled: March 6, 2012Publication date: March 14, 2013Applicant: VIA TECHNOLOGIES, INC.Inventors: G. Glenn Henry, Terry Parks, Rodney E. Hooker
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Publication number: 20130067203Abstract: A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.Type: ApplicationFiled: September 14, 2012Publication date: March 14, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moo-Kyoung Chung, Woong Seo, Ho-Young Kim, Soo-Jung Ryu, Dong-Hoon Yoo, Jin-Seok Lee, Yeon-Gon Cho, Chang-Moo Kim, Seung-Hun Jin
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Publication number: 20130067204Abstract: Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. Other embodiments are also described.Type: ApplicationFiled: November 6, 2012Publication date: March 14, 2013Inventors: Cristina S. Anderson, Simon Rubanovich, Benny Eitan
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Publication number: 20130067205Abstract: An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: QUALCOMM IncorporatedInventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Charles J. Tabony, Suresh K. Venkumahanti
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Publication number: 20130067206Abstract: Endpoint-based parallel data processing in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints, each endpoint including a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task, the compute nodes coupled for data communications through the PAMI, including establishing a data communications geometry, the geometry specifying, for tasks representing processes of execution of the parallel application, a set of endpoints that are used in collective operations of the PAMI including a plurality of endpoints for one of the tasks; receiving in endpoints of the geometry an instruction for a collective operation; and executing the instruction for a collective operation through the endpoints in dependence upon the geometry, including dividing data communications operations among the plurality of endpoints for one of the tasks.Type: ApplicationFiled: November 9, 2012Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: International Business Machines Corporation
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Publication number: 20130067207Abstract: Provided is a technique that is capable of efficiently compressing instructions by inserting instruction compression bits into valid instruction bundles and deleting no operation (NOP) instruction bundles. Accordingly, the number of instructions that can be parallel-processed in a processor may be increased.Type: ApplicationFiled: August 27, 2012Publication date: March 14, 2013Inventor: Tai-Song Jin
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Publication number: 20130067208Abstract: An improved system and method are disclosed for configuring a behavior of an application on a mobile device via configuration parameters maintained by an application control program provided on a network accessible platform that is separate from the mobile device. In one example, the method enables the application control program to configure and dynamically modify parameters for a particular application that may also be used as a stand-alone application on the mobile device.Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Applicant: BRINKMAN FINANCIAL COMPANY, L.P.Inventors: Mark BRINKMAN, Raymond J. MIMICK, Kary B. KELLOGG
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Publication number: 20130067209Abstract: Methods, systems, and computer program products are provided for automatically installing an operating system on a computing device that does not have an operating system pre-installed. Identifying information for the computing device is collected from a resource of the computing device. The identifying information is transmitted to a remote service. An indication is received of an operating system for the computing device selected by the remote service based on the identifying information. The selected operating system is downloaded for installation on the computing device.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: MICROSOFT CORPORATIONInventors: Michael Hall, Steven P. Maillet
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Publication number: 20130067210Abstract: Systems and methods for reducing problems and disadvantages associated with traditional approaches to encryption and decryption of data are provided. An information handling system may include a processor, a memory communicatively coupled to the processor, and a computer-readable medium communicatively coupled to the processor. The computer-readable medium may have instructions stored thereon, the instructions configured to, when executed by the processor: (i) periodically store, during an encryption or decryption operation performed on the computer-readable medium, one or more variables indicative of an encryption status of a volume of the computer-readable medium; (ii) determine, based on the one or more variables, whether the volume is in a partially encrypted or decrypted state; and (iii) in response to a determination that the volume is in a partially encrypted or decrypted state, boot from the volume and continue the encryption or decryption operation.Type: ApplicationFiled: October 30, 2012Publication date: March 14, 2013Inventors: Amy Christine Nelson, Kenneth W. Stufflebeam, JR.
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Publication number: 20130067211Abstract: In the field of computer enabled cryptography, such as a keyed block cipher having a plurality of sequenced rounds, the cipher is hardened against attack by a protection process. The protection process uses block lengths that are larger or smaller than and not an integer multiple of those of an associated standard cipher, and without using message padding. This is operative in conjunction with standard block ciphers such as the AES, DES or triple DES ciphers, and also with various block cipher cryptographic modes such as CBC or EBC.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Applicant: Apple Inc.Inventors: Augustin J. FARRUGIA, Benoit Chevallier-Mames, Melanie Riendeau, Mathieu Ciet, Thomas Icart