Abstract: In a method is provided for evaluating an analog signal, which carries data on a rotational motion, the analog signal is read in by an A-D converter for evaluation and zero crossings of the analog signal are determined.

Abstract: A humidity sensor according to the present examples include a sensor portion for detecting humidity in the ambient environment, and a power supply portion for applying an AC voltage to the sensor portion, wherein the sensor portion is structured so as to have an impedance that is higher than a sensor portion of a conventional humidity sensor. As a result, it is possible to reduce the amount of power consumed in the sensor portion when compared to that of a conventional humidity sensor. Doing so makes it possible to reduce the amount of electrical power consumed in the humidity sensor as a whole in the present invention, including the sensor portion, when compared to that of a conventional humidity sensor.

Abstract: A system that includes at least one capacitive sensor for least one angle of incidence component of radiation being measured striking the sensor. The measured capacitance of the sensor is affected by radiation striking the sensor. In some embodiments, the system includes multiple sensors where differences in the capacitive measurements of the sensors can be used to determine information about the radiation such as e.g. horizontal angle, directional angle, and dose.

Abstract: A capacitive sensor system and method resistant to electromagnetic interference is disclosed. The system includes a capacitive core, differential amplifier with inverting and non-inverting inputs, capacitive paths, and chopping system. Core can include inputs and outputs coupled to variable capacitors, and common nodes coupling variable capacitors. Capacitive paths couple core outputs to amplifier inputs. When chopping system is high, one polarity voltage is applied to core inputs, a first core output is coupled to the inverting input and a second core output is coupled to the non-inverting input. When the chopping system is low, opposite polarity voltage is applied to core inputs, and core output to amplifier input couplings are flipped. Capacitive paths can include bond wires. Chopping system can be varied between high and low at frequencies that smear noise away from a frequency band of interest, or that smear noise substantially evenly across a wide frequency range.

Abstract: A sensor interface circuit is provided for resolving sensor signals from a plurality of sensors into a digital sensor signal, the sensor interface circuit comprising: a relaxation oscillator for receiving and pre-processing the sensor signals to generate an analog sensor signal, the relaxation oscillator comprising one or more dynamic circuits; and a monitoring module for receiving the analog sensor signal and generating the digital sensor signal in response thereto. There is also provided a sensor system front-end and a relaxation oscillator.

Abstract: In one embodiment, a method includes restricting current flow between a node of a touch sensor and each of a drive system of the touch sensor, a sense system of the touch sensor, and a test system of the touch sensor. The method further includes capacitively coupling the drive system to the sense system through the test system. The method further includes using at least the drive system and the test system, inducing a charge on the sense system. The method further includes measuring the induced charge on the sense system. The method further includes making a pass or fail determination for at least a portion of the touch sensor based at least in part on the measured induced charge.

Abstract: A particle detector includes: a conductive nanolayer; insulating nanolayers attached to both sides of the conductive nanolayer; a nanopore formed to penetrate the conductive nanolayer and the insulating nanolayers so as to provide a migration path for a sample particle; a power supply unit configured to apply an electric field between both ends of the nanopore so as to apply a potential to the conductive nanolayer; and an electric signal measuring unit electrically connected to the conductive nanolayer and configured to measure the potential change in the conductive nanolayer induced by the sample particle as the sample particle migrates through the nanopore. The particle detector is capable of detecting a particle with high signal-to-noise ratio and resolution, scanning a sample without mechanical motion of the conductive nanolayer and analyzing DNA base sequences.

Abstract: An evaluation board for evaluating a power module including a power semiconductor device and a detecting unit for detecting characteristics of the power semiconductor device, comprises: a power source circuit supplying an electric power to the power module; a driving circuit driving the power semiconductor device; a display unit displaying a detected signal inputted from the detecting unit; and a substrate on which the power source circuit, the driving circuit, and the display unit are mounted.

Abstract: A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate chain, and a counter. The counter measures the difference in propagation delay between the test chain and the reference chain in calibrated oscillator cycles. Differences in test gate delay as a function of applied stress may be measured within the calibration accuracy of the oscillator frequency. The use of the reference gate chain allows a simpler unipolar counter.

Abstract: A probe apparatus includes a movable mounting table for holding a test object provided with a plurality of power devices including diodes; a probe card arranged above the mounting table with probes; a measuring unit for measuring electrical characteristics of the power devices by bringing the probes into electrical contact with the test object in a state that a conductive film electrode formed on at least a mounting surface of the mounting table is electrically connected to a conductive layer formed on a rear surface of the test object; and a conduction member for electrically interconnecting the conductive film electrode and the measuring unit when measuring the electrical characteristics. The conduction member is interposed between an outer peripheral portion of the probe card and an outer peripheral portion of the mounting table.

Abstract: A contactor assembly for automated testing a device under test (DUT) that includes a plurality of separate electrodes including a first electrode includes a tester load board and a contactor body coupled to the tester load board. A plurality of contactor pins carried by the contactor body includes a first contactor pin and a second contactor pin that are electrically coupled to the tester load board. The tester load board is configured to couple the plurality of contactor pins to automatic test equipment (ATE) for testing the DUT. The first contactor pin and second contactor pin are positioned to both contact the first electrode. A first path to the first contactor pin and a second path to the second contactor pin are electrically shorted together by the contactor assembly to be electrically in parallel to provide redundant paths to the first electrode during automated testing of the DUT.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A solar simulator in which locational unevenness of irradiance is reduced by using a small and simple optical system, having an array of light emitters 2 with a plurality of point light emitters planarly arranged in a given range 24, an effective irradiated region 4 spaced apart from a surface having the point light emitters 26 arranged thereon, and a reflection mirror 6 disposed to surround the given range 24 of the array. Preferably, a distance L between the point light emitter positioned at the outermost portion of given range 24 of the array of light emitters 2 and a light-reflecting surface of the reflection mirror is half of a pitch a of the array of the point light emitters and, more preferably, the distance L is larger than half of a width b of each point light emitter, and smaller than half of the pitch a.

Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Abstract: This invention is an electrostatic discharge (ESD) testing circuit that can deliver current pulses to a component under test (CUT) with controlled impedance. Generated current pulses simulating ESD events, such as those compliant to the European International Electrotechnical Commission IEC 61000-4-2 standard, can be delivered to the CUT with low distortion through a constant impedance electrical path, such as a combination of cables and controlled impedance conductors of printed wiring boards and wafer probes compatible with packaged IC devices, assemblies, and wafers, plus an impedance controlling series resistance. The current pulse can be delivered to the CUT with various forcing impedances. Measurements of the current passing through the CUT can be made.

Abstract: System and method for deglitching an input signal. An output signal may be delayed to generate a delayed signal, the delayed signal determining a guard time interval following a desired transition in the input signal, and a logic circuit is used to keep the output signal unchanged during the guard time interval, and to allow the output signal to equal the input signal outside the guard time interval, based on a value of the delayed signal.

Abstract: In one aspect, the invention relates to logic cells that utilize one or more of spin diodes. By placing one or two control wires on the side of the spin diodes to generate magnetic fields in the spin diodes due to input currents, the logic cell can be changed from one logic gate to another logic gate. The unique feature leads to field logic devices in which simple instructions can be used to construct a whole new set of logic gates.

Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.

Abstract: The present invention relates to a master-slave interleaved BCM PFC controller for controlling a PFC circuit with master and slave channels. In one embodiment, the PFC controller can include: a master channel controller that generates a master channel control signal and an inverted master channel control signal; a first phase shifter that provides a first phase shift for the master channel control signal, and generates a delayed opening signal therefrom; a second phase shifter that provides a second phase shift for the inverted master channel control signal, and generates a delayed shutdown signal therefrom; a slave channel controller that receives the delayed opening signal, the delayed shutdown signal, and a slave channel inductor current zero-crossing signal, and generates a slave channel control signal therefrom.

Abstract: A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.

Abstract: A battery temperature monitoring circuit, which has a cold comparator and a hot comparator, achieves high accuracy in a small cell size by utilizing a cold current optimized for the cold comparator and a cold reference voltage, and a hot current optimized for the hot comparator and a hot reference voltage, along with switching circuitry that provides the cold current to the cold comparator as the battery temperature approaches the cold trip temperature, and the hot current to the hot comparator as the battery temperature approaches the hot trip temperature.

Abstract: A signal generating apparatus includes: a direct digital synthesizer configured to generate an output signal of a frequency according to first control data based on a reference clock; and a controller configured to provide the direct digital synthesizer with the first control data at a timing synchronized with the reference clock, wherein the controller includes a table which stores second setting data for controlling the frequency of the output signal based on jitter information and provides the direct digital synthesizer with the second setting data in the table as the first control data at the timing.

Abstract: Versions of the present invention have many advantages, including operation under high temperatures, or high frequencies while providing the required current for switching a SiC VJFET, providing electrical isolation and minimizing dv/dt noise. One embodiment is a silicon carbide gate driver comprising a first group of silicon on insulator devices and passive components and a second group of silicon carbide devices. The first group may have equivalent temperatures of operation and equivalent frequencies of operation as the second group.

Abstract: An embodiment apparatus comprises a first two-piecewise linear approximation generator and a second two-piecewise linear approximation generator coupled to an output of the first two-piece wise linear approximation generator. The second two-piecewise linear approximation generator generates a dead time inversely proportional to the output of the first two-piece wise linear approximation generator. A gate drive generator is configured to generate a primary switch drive signal and an auxiliary switch drive signal complementary to the primary switch drive signal. In addition, the dead time between the primary switch drive signal and the auxiliary switch drive signal is adjustable when the power converter operates in a light load condition.

Abstract: A driver circuit for controlling a high-side power switch of a switching regulator includes: a logic circuit configured to generate a gate control signal for turning on the power switch; a diode having coupled to a first power supply voltage; a capacitor having a first electrode coupled to the cathode of the diode and a second electrode coupled to the switching output voltage; and a delay circuit configured to receive the gate control signal and to generate a delayed gate control signal. In operation, the capacitor is precharged to about the first power supply voltage. When the power switch is turned on, a first output drive transistor is turned on to distribute the charge stored on the capacitor to the gate terminal of the high-side power switch, and after the predetermined delay, a second output drive transistor is turned on to drive the output node to a high supply voltage.

Abstract: Disclosed herein is a solidstate switch driving circuit for a vehicle. The solidstate switch driving circuit includes an oscillation circuit, a constant voltage circuit, a first Field Effect Transistor (FET), a second FET, a third FET configured, a first time constant circuit, a first time constant circuit, a reverse voltage protection diode, a solidstate power switch, and a second time constant circuit. The first time constant circuit is connected to the drain of the second FET and the drain of the third FET. The reverse voltage protection diode has an N pole and a P pole. The solidstate power switch selectively turns on and off power applied to the load. The second time constant circuit has one side connected to the first time constant circuit and the reverse voltage protection diode, and another side connected to a gate of the solidstate power switch.

Abstract: A power module includes: a drive circuit for driving an IGBT of a semiconductor element; a protection circuit for performing operation for protection of the IGBT if the collector current of the IGBT has reached a trip level; and a control power source voltage detection circuit for detecting a control power source voltage to be supplied to the drive circuit. The protection circuit changes a sense resistor from a resistor to a series circuit with resistors and if the control power source voltage drops to a level lower than a predetermined value, thereby lowering the trip level.

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

Abstract: One embodiment of the present invention relates to a waveform generator that includes a first pair of capacitors, a second pair of capacitors, an op amp and control logic. The op amp has inputs and provides a differential triangular waveform at its outputs as an output signal. The control logic includes capacitor control logic, ramp control logic, reset control logic and charge control logic. The capacitor control logic connects a current pair of the first and second capacitors to the inputs of the op amp. The ramp control logic provides ramp currents to the current pair. The reset control logic resets capacitors of a next pair to selected voltage(s), such as zero. The charge control logic charges the next pair of capacitors, typically after the next pair of capacitors has been driven to the selected voltage(s).

Abstract: A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle.

Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.

Abstract: A calibration device and related method for a phase difference between data signal and clock signal are disclosed. An apparatus of the invention includes: an adjustable delay circuit for delaying at least one of a first input signal and a second input signal according to a delay control signal, and generating a first signal and a second signal; a phase detection circuit for detecting a phase difference between the first signal and the second signal to output a phase difference signal; a charge pump and a capacitor for outputting a control signal according to the phase difference signal; a comparison circuit for outputting a comparison result according to the control signal; and, a digital control circuit for outputting the delay control signal according to the comparison result.

Abstract: The circuit for the clocking of an FPGA comprises an FLL-circuit; a reference clock of a first frequency, or a reference clock input for the reception of a signal of a reference clock of a first frequency; and a digitally controlled oscillator, which outputs a clocking signal for the FPGA, wherein the FLL-circuit is designed in order to register a first number of clocking signals from the digitally controlled oscillator during a second number of periods of the reference clock, the first number is larger than the second number, and, in order to give out a feedback signal to control the ratio between the first number and the second number, as the feedback signal acts on the frequency of the digitally controlled oscillator.

Abstract: A digital input buffer and method. The input buffer includes a voltage regulator configured for operating in weak inversion and outputting a regulated potential, an inverter having as its power source the regulated potential and configured for receiving an input signal, a first latch having its input coupled to the inverter input, and a second latch having its input coupled to the inverter's output, having its output coupled to the first latch's enable input, and having its enable input coupled to the first latch's output. A first latch output signal from the first latch output and a second latch output signal from the second latch output enable switching the first latch output signal to the complement of the input signal and switching the second latch output signal to that of the input signal.

Abstract: A third periodic signal is synthesized using a first output signal having a phase corresponding to a first periodic signal and a second output signal having a phase corresponding to the second periodic signal. A value of the third periodic signal is detected at a timing of the phase of the delayed first periodic signal. The value of the third periodic signal detected with the delayed first periodic signal is compared with the value of the third periodic signal detected by the first periodic signal delayed by the different delay amount. The delay amount is obtained for the detected third periodic signal being a maximum or a minimum. In a state of the optimum delay amount, an amplitude of the third periodic signal is adjusted so that the detected value of the third periodic signal falls within a predetermined range.

Abstract: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.

Abstract: A buffer circuit includes a first node that receives a first voltage, a second node, an output node that receives the first voltage, a first transistor coupled between the first node and the second node, the first transistor having a backgate receiving the first voltage, and a second transistor coupled between the second node and the output node, the second transistor having a backgate receiving a second voltage being higher than the first voltage.

Abstract: Disclosed is a programmable complex mixer. In accordance with the embodiments of the present invention, it is possible to control an output by programming paths and signs of internal signals in a complex mixer to reduce a processing bandwidth, power consumption, and a chip area in a transceiver, thereby improving performance of a transceiver.

Abstract: A CMOS circuit and a semiconductor device having small leakage current and a low threshold voltage, and which is operated at high speed and with a small voltage amplitude, including an output stage circuit having MOSTs configured such that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, and upon deactivation, a voltage is applied to the gate of each of the MOSTs to cause a reverse bias to be applied between the gate and source of the MOST. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage.

Abstract: Provided is a reference voltage circuit for generating a low constant voltage (1.25 V or lower) having less temperature dependence. The reference voltage circuit includes: a bandgap voltage generation circuit including two PN junctions, for outputting a voltage (Vk) which is based on any one of the two PN junctions and a current (Ik) which is based on a voltage difference between the two PN junctions; and a voltage divider circuit for dividing the voltage (Vk). The voltage divider circuit corrects a divided voltage based on the current (Ik) input thereto, and outputs the corrected divided voltage as a reference voltage.

Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

Abstract: According to an embodiment, a semiconductor integrated circuit including first and second lower-layer power supply wires extending in a first direction and first and second upper-layer power supply wires extending in a second direction is provided. First and second connection wires between the upper-layer power supply wires and the lower-layer power supply wires are arranged in a same line along the second direction. First and second position converting wires extending from the connection wires are arranged between the first and second connection wires. First and second upper-side vias provided on the position converting wires are arranged in a same line along the first direction.

Abstract: According to one embodiment, an output signal circuit for use in a receiver is provided. The output signal circuit is provided with first and second transistors of an insulated gate field effect type, and a backgate bias generator. A source of the first transistor is capable of receiving an input signal. A source of the second transistor is capable of generating an output signal. A backgate bias generator produces a backgate bias voltage which is applied to backgate of the first and second transistors commonly.

Abstract: A protection relay device includes: an analog-to-digital converter that samples an analog signal inputted from an analog input unit and converts the analog signal into digital data; a variable filter that filters and outputs the digital data, the variable filter having a filter coefficient that is varied by external control; and an adaptive controller that variably controls the filter coefficient of the variable filter so that a difference between the digital data filtered by the variable filter and a target signal decreases.

Abstract: Disclosed herein is an integrated circuit including: a timing signal distribution circuit configured to distribute a timing signal that indicates predetermined timing; a synchronous operation circuit configured to operate in synchronization with the distributed timing signal; a logic circuit configured to perform predetermined logical operation based on an operation result of the synchronous operation circuit; and a power supply section configured to supply a voltage lower than a timing signal distribution circuit drive voltage to drive the timing signal distribution circuit as a logic circuit drive voltage to the logic circuit.

Abstract: A capacitive sensor system and method resistant to electromagnetic interference is disclosed. The system includes a capacitive core, differential amplifier with inverting and non-inverting inputs, capacitive paths, and chopping system. Core can include inputs and outputs coupled to variable capacitors, and common nodes coupling variable capacitors. Capacitive paths couple core outputs to amplifier inputs. When chopping system is high, one polarity voltage is applied to core inputs, a first core output is coupled to the inverting input and a second core output is coupled to the non-inverting input. When the chopping system is low, opposite polarity voltage is applied to core inputs, and core output to amplifier input couplings are flipped. Capacitive paths can include bond wires. Chopping system can be varied between high and low at frequencies that smear noise away from a frequency band of interest, or that smear noise substantially evenly across a wide frequency range.

Abstract: A transmitter that uses a digital pre-distortion (DPD) circuit to mitigate the effects of nonlinearity of a multistage or multi-branch power amplifier. The DPD circuit relies on two or more feedback signals received from an RF-output circuit of the transmitter to generate individually pre-distorted signals for the individual stages/branches of the power amplifier. The use of these individually pre-distorted signals advantageously enables the transmitter to achieve a more efficient suppression of inter-modulation-distortion products than that typically achieved with a comparable prior-art transmitter.

Abstract: A switching amplifying method or a switching amplifier for obtaining a linearly amplified replica of an input signal, is highly efficient, and does not have the disadvantage of “dead time” problem related to the class D amplifiers. Another aspect of the present invention provides a switching amplifier that is completely off when there is no input signal. Yet another aspect of the present invention further comprises an act of comparing an input signal with an output feedback signal for detection and correction of overall system signal processes therefore does not require a power supply regulator and is substantially immune to power supply and load perturbations.

Abstract: For high speed amplifiers, the parasitic capacitances from the differential input pair introduce a zero that can affect performance. Here, a neutralization network has been provided that compensates for this zero by shifting its position. This is generally accomplished by using a pair of capacitors that are cross-coupled across the differential input pair of the amplifier.

Abstract: The invention relates to a “push-pull” amplifier, comprising an input (12) and an output (14), which includes: a main amplification branch comprising two amplification transistors (18, 20) connected in opposite series between two supply voltages (V+, V?), the amplifier output (14) being connected between the two transistors (18, 20), and a control circuit (22, 24) for each amplification transistor (18, 20) connected to the input (12) to each receive as an input the signal to be amplified. The main amplification branch comprises, between each transistor (18, 20) and the output (14), a member having a nonlinear response (38, 40) and means (30, 32) for introducing at the input of the control circuit (22, 24) of each transistor (18, 20), a nonlinear compensating signal suitable for bringing about the circulation of a minimum current in the member having a nonlinear response (38, 40).