Abstract: A semiconductor device includes a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall, and a second transistor that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall. The first transistor includes a portion of a logic circuit. The second transistor includes a transistor included in a memory cell of a DRAM, or includes a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM. The first gate insulating film has a same thickness as that of the second gate insulating film. The first gate electrode has the same thickness as that of the second gate electrode. A layer structure of the first sidewall is a same as a layer structure of the second sidewall.

Abstract: A non-volatile memory device, a data read method thereof and a recording medium are provided. The method includes receiving a data read command for a first word line in a memory cell array, reading data from a second word line adjacent to the first word line, and reading data from the first word line using a different voltage according to a state of the data read from the second word line. The number of read voltages used to distinguish an erased state and a first programmed state is greater than the number of read voltages used to distinguish a second programmed state and a third programmed state.

Abstract: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.

Abstract: The disclosure relates to a method for testing an integrated circuit, comprising in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage, the first test voltage being set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down, the second test voltage being set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps.

Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

Abstract: A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.

Abstract: A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single data rate data. The first write switch circuit is used for outputting the odd term data of the adjusted double data rate data to an odd block of a memory and outputting the even term data of the adjusted double data rate data to an even block of the memory when the write data circuit receives the double data rate data, and outputting the adjusted single data rate data to the even block or the odd block of the memory when the write data circuit receives the single data rate data.

Abstract: A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.

Abstract: A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

Abstract: The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories.

Abstract: An interleaver or deinterleaver comprises a memory having M logical memory units arranged in groups of N memory units such that accesses to memory units within a group are faster after a first access to a memory in that group using first access. An address generator is arranged to write consecutive data items a number of memory units apart that is less than the size of groups N of memory units so that two or more data items are written within groups. The arrangement provides fast interleaving without increasing memory size.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.

Abstract: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal.

Abstract: A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip are stacked, the controller chip may still activate/enable a spare in the memory chip to repair a damaged or deteriorated memory cell in the memory chip through at least one vertical interconnect (for example, through-silicon via (TSV)), regardless of whether the damaged or deteriorated memory cell has been repaired or not before the controller chip and the memory chip are stacked.

Abstract: By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.

Abstract: A semiconductor memory device comprises a memory cell; a first bit line and a second bit line connected to the memory cell; and a sense amplifier operative to amplify the voltage between the first and second bit lines. The sense amplifier includes a first and a second drive transistor configuring a transistor pair for differential amplification, and a first and a second capacitor connected between the sources of the first and second drive transistors and a source control terminal, respectively. The sense amplifier precharges the first and second drive transistors on the drain side prior to sensing, thereby holding the threshold information on the first and second drive transistors in the first and second capacitors, and compensates for the source voltages on the first and second drive transistors by the threshold information held in the first and second capacitors at the time of sensing.

Abstract: An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells.

Abstract: A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing data output from the memory core and outputting serialized data to the controller via the data port. The controller generates the first selection signal based on at least one of the voltage signal and the serialized data.

Abstract: Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

Abstract: A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros.

Abstract: The present invention relates to a device for producing a hardenable mass, preferably bone substitute and/or bone reinforcing material or bone cement or similar material. A mixing container may include a mixing space in which at least one powder and at least one liquid component are mixed to provide the hardenable mass. A piston may be provided in the mixing space of the mixing container. A screw device may be connectable to the mixing container such that the screw device may be configured to impart by screw movements a discharge movement to the piston to discharge the hardenable mass from the mixing space.

Abstract: A system for blending and dispensing a frozen mixture includes a blending chamber to receive the ingredients to be blended and a blending mechanism that includes a rotating blade for blending and a motor to drive the blade. A piston is located within the blending chamber, and a dispensing mechanism dispenses a blended mixture from the blending chamber. A discharge mechanism discharges a cleaning fluid from the blending chamber. The piston is moved to a first position with respect to the blending mechanism during a blending cycle and moved to a second position during a dispensing cycle, the second position being closer to the blending mechanism than the first position. The piston is moved to a third position with respect to the blending mechanism during an introduction of a cleaning fluid into the blending chamber, the third position being farther away from the blending mechanism than the first position.

Abstract: An electromechanical transducer according to an embodiment of the present invention is capable of selectively performing a transmitting and receiving operation by using elements of different shapes. The electromechanical transducer has a plurality of cells, each of which has a vibrating film including two electrodes provided with a gap therebetween, two driving and detecting units, a potential difference setter, and a switch. Each of the driving and detecting units implements a transmitting and/or a receiving function. A first or second element includes first or second electrodes which are electrically connected and further connected to the common first or second driving and detecting unit, respectively. The potential difference setter sets a predetermined potential difference between the reference potentials of the first and second driving and detecting units, respectively, and the switch switches between the first and second driving and detecting units to perform the transmitting and receiving operation.

Abstract: The present invention provides an ultrasound system, which comprises: a signal acquiring unit to transmit an ultrasound signal to an object and acquire an echo signal reflected from the object; a signal processing unit to control TGC (Time Gain Compensation) and LGC (Lateral Gain Compensation) of the echo signal; a TGC/LGC setup unit adapted to set TGC and LGC values based on TGC and LGC curves inputted by a user; and an image producing unit adapted to produce an ultrasound image of the object based on the echo signal. The signal processing unit is further adapted to control the TGC and the LGC of the echo signal based on the TGC and LGC values set by the TGC/LGC setup unit.

Abstract: Apparatus for ultrasound image acquisition is integrated into the casing of an ultrasound probe that includes an array of electro-acoustic transducers, which transmit and receive ultrasound pulses. The array communicate with a processing unit, to which reception signals are fed, and are connected to a unit generating signals for exciting the transmission of ultrasound waves. In one aspect of the invention, at least the processing unit is fitted into the probe casing and is configured to convert the reception signals into an image, and to generate video signals for generating an image on a display unit. The transmission between the probe and a remote unit displaying and possibly storing the images as video signals may be operated wirelessly.

Abstract: A seismic streamer includes a sensor comprises an axially oriented body including a plurality of axially oriented channels arranged in opposing pairs; a plurality of hydrophones arranged in opposing pairs in the channels; a pair of orthogonally oriented acoustic particle motion sensors; and a tilt sensor adjacent or associated with the particle motion sensors. The streamer has a plurality of hydrophones, as previously described, aligned with a plurality of accelerometers which detect movement of the streamer in the horizontal and vertical directions, all coupled with a tilt sensor, so that the marine seismic system can detect whether a detected seismic signal is a reflection from a geologic structure beneath the streamer or a downward traveling reflection from the air/seawater interface.

Abstract: The subject disclosure relates to sonic logging while drilling. A transmitter and at least one receiver are mounted on a drill collar for performing sonic investigations of the formation traversing a borehole.

Abstract: Method for analyzing seismic data representing a subsurface region for presence of a hydrocarbon system or a particular play. Seismic attributes are computed, the attributes being selected to relate to the classical elements of a hydrocarbon system, namely reservoir, seal, trap, source, maturation, and migration. Preferably, the attributes are computed along structural fabrics (1) of the subsurface region, and are smoothed over at least tens or hundreds of data voxels. The resulting geologic attributes (2) are used to analyze the data for elements of the hydrocarbon system and/or recognition of specific plays, and for ranking and annotating partitioned regions (3) of the data volume based on size, quality, and confidence in the prospectivity prediction (5). A catalogue (8) of hydrocarbon trap configurations may be created and used to identify potential presence of hydrocarbon traps and/or aid in scoring (4) and ranking partitioned regions as hydrocarbon prospects.

Abstract: In an oscillator (100), a plurality of piezoelectric vibrators (111 to 113) supported by vibrator support mechanisms (120) individually output highly directional sound waves. The plurality of piezoelectric vibrators (111 to 113) is formed by dividing a laminated body of an elastic member and a piezoelectric substance by the vibrator support mechanisms (120). Since it is not necessary to arrange the plurality of piezoelectric vibrators in a matrix, the entirety of a device can be small-sized. A sound deflection unit that deflects a sound wave which is output by at least one of the piezoelectric vibrators may be further included.

Abstract: An apparatus comprises a test signal generator (401) which generates an ultrasonic test signal by modulating an audio band test signal on an ultrasonic signal. The ultrasonic test signal is radiated from a parametric loudspeaker (403) and is demodulated by non-linearities in the air. A reflected audio signal may arise from reflections of an object, such as a wall. An audio band sensor (405) generates an audio band captured signal which comprises the demodulated reflected audio band signal. A distance circuit (407) then generates a distance estimate for the distance from the parametric loudspeaker (403) to the object in response to a comparison of the audio band captured signal and the audio band test signal. Specifically two signals may be correlated to determine a delay corresponding to the full path length. Based on the distance estimates an audio environment may be estimated and a sound system may be adapted accordingly.

Abstract: A CMUT on CMOS imaging chip is disclosed. The imaging chip can use direct connection, CMOS architecture to minimize both internal and external connection complexity. Intelligent power management can enable the chip to be used for various imaging applications with strict power constraints, including forward-looking intra-vascular ultrasound imaging. The chip can use digital logic to control transmit and receive events to minimize power consumption and maximize image resolution. The chip can be integrated into a probe, or catheter, and requires minimal external connections. The chip can comprise integrated temperature control to prevent overheating.

Abstract: The various embodiments provide systems, devices, and methods which include an acoustic tag configured to transmit an acoustic signal through a contact medium that may be received by an acoustic modem, with the acoustic signal configured to transmit information. By modulating sound traveling through an acoustic connection between the fluid container and a pump, meter or valve, information such as an identifier of the fluid or container may be transmitted without risk of confusion with other fluid containers in the vicinity. In a medical embodiment, IV fluid and the IV drip tube provide a fluid and plastic acoustic connection to an IV pumping or metering device and an IV bag through which sound may be transmitted. The transmission of identification information through this physical connection may insure that the pumping or metering device only communicates with the IV bag coupled to the pump. Acoustic tags may be active or passive.

Abstract: An analog wearable electronic device that is operationally coupleable to a transmitting device. The transmitting device includes means for viewing a simulation of a display provided on the wearable electronic device, changing information displayable on the simulated display and transmitting the changed information and/or information from which the changed information is derivable to the wearable electronic device. The wearable electronic device includes a receiver for receiving from the transmitting device the changed information and/or the information from which the changed information is derivable. A controller assembly processes the changed information and/or derives the changed information, and an actuation mechanism moves a display indicator based at least in part on the changed information. The changed information is thereafter reflected on the display of the wearable electronic device by the display indicator.

Abstract: The invention relates to a balance spring (7, 37) including a first hairspring (11, 41), the inner coil of which comprises a collet (10, 40) arranged to be mounted on a staff (2, 32), and a second hairspring (13, 43) connected to the outer coil of the first hairspring (11, 41) by a raised terminal curve device (15, 45). According to the invention, the inner coil of the second hairspring (13, 43) includes a device (17, 47) for shifting the pinning point comprising a free end (6, 36) arranged to be pinned up to a stud (8, 38) in the plane of said second hairspring. The invention concerns the field of sprung balance resonators.

Abstract: Timepiece gear train device (1) of reduced height with a large power reserve, driving display means (4) including a cannon-pinion (5) and an hour wheel (6), which are driven about a main pivot axis (AP), secant to a barrel (3), by a motion work (7) and including a driving wheel (8), which pivots about a secondary pivot axis (AS) external to said barrel (3) and is friction coupled to said motion work (7) on a friction surface (9) coaxial to said secondary pivot axis (AS). Said driving wheel (8) includes a driving cannon pinion (83) pivoting about a wheel body (80) along said secondary pivot axis (AS) and coupled by a friction spring (84) to a shoulder (85) of said wheel body (80) forming said friction surface (9), said driving cannon-pinion (83) cooperating with a minute wheel (14) pivoting about a minute axis (AM).

Abstract: To provide a timepiece dial that presents a rich stereoscopic effect, and to provide a timepiece including the timepiece dial, a timepiece dial of the invention has a microlens layer in which a plurality of microlenses are arranged in an orderly fashion when viewed from above, and a decorative layer provided with a design, in which the microlens layer and the decorative layer are superimposed when viewed from above, and the decorative layer has a plurality of regions that are different in the design from each other. Preferably, the decorative layer is provided with a design having a plurality of lines and/or a repeating design having the same arrangement as the microlenses and a pitch that differs from that of the microlenses as the design.

Abstract: There is described a watch (10) comprising a case (12) enclosing a mechanism or clockwork (14), a clockwork holding support (18) and a strap. The strap consists of at least one flexible sheet (24) made of a metal material, having such a length as to be wound by bending and shaped around the wrist or a generic part of a user's body for steadily keeping the watch (10) in position. The flexible sheet (24) is inserted within a sheath (26) made of a non metal material intended for contacting the part of the user's body. Therefore, no clasp is required for the strap of the watch (10) since the flexible sheet (24) and the relative sheath (26) remain steadily rolled up around the part of the user's body, irrespective of the size of such part of the body (wrist, ankle, forearm, etc.), when the same watch (10) is worn.

Abstract: A watch with easily replaceable components, comprising a case, a bezel which is contoured so as to surround the glass of the case, and a strap. The bezel is fixed reversibly to the case with snap-acting quick engagement/release elements. The bezel has, on opposite perimetric portions, pairs of symmetrical grooves which are open on the inner part of the bezel and are closed on the outer part of the bezel and are each adapted to receive by insertion one end of a pin for the engagement of the strap, each pin remaining closed between the two grooves that accommodate its ends and the case.

Abstract: An apparatus includes a waveguide configured to deliver light to a transducer region. The apparatus also includes a plasmonic transducer that has two metal elements configured as side-by-side plates on a substrate-parallel plane with a gap therebetween. The gap is disposed along the substrate-parallel plane and has an input end disposed proximate the transducer region and an output end. The transducer is configured to provide a surface plasmon-enhanced near-field radiation pattern proximate the output end in response to the light received by the waveguide.

Abstract: Upon receiving a request to allocate a storage region, a storage device may initialize the contents of the storage device to default values (e.g., zero) in order to avoid problems arising from unknown data stored in the locations of the storage region (e.g., upon writing a data set to a location involved in a mirroring relationship, uninitialized data in the corresponding mirror location may result in a mismatch that jeopardizes the written data). However, initializing the storage device may be time-consuming and inefficient. Instead, a usage bitmap may be generated that, for respective location sets of the storage region, indicates whether values exist in the location. A read request may be fulfilled by examining the usage bitmap to determine whether values exist in the specified location, and if not, the default value may be returned without accessing the storage device. Other efficiencies may also be achieved using the usage bitmap.

Abstract: An information recording medium in which bottoms of a guide groove and a pit array formed on a disc substrate are allocated on a same flat plane and shaped in flat. Further, in a transition area from a pit array to a guide groove or from a guide groove to a pit array, the information recording medium is provided with an intermediate area composed of a pit array of which height changes from a height between a bottom and a side of a groove to another height between the bottom and a side of the pit array.

Abstract: An information recording medium in which bottoms of a guide groove and a pit array formed on a disc substrate are allocated on a same flat plane and shaped in flat. Further, in a transition area from a pit array to a guide groove or from a guide groove to a pit array, the information recording medium is provided with an intermediate area composed of a pit array of which height changes from a height between a bottom and a side of a groove to another height between the bottom and a side of the pit array.

Abstract: A copy-protected compact disc includes, within a single session, a table of contents (TOC) and a Video CD index (VI). Each track (T) is prefaced by unrecoverable data (UD) at a track start position (ATOC) indicated by the table of contents (TOC). However, the Video CD index (VI) indicates the actual position (AP) of the tracks. DVD players use the Video CD index (VI) to locate the tracks, while the CD-ROM drives use the table of contents (TOC) and read the unrecoverable data (UD), which prevents them from reading the subsequent track (T). The unrecoverable data (UD) may be prefaced by data pointers (DP) which cause the CD-ROM drive to load a player program in response to the error condition. The player program can be used to play the tracks (T), but restricts copying. Subchannel data (P; DX) causes audio CD players to ignore the Video CD index (VI) and the unrecoverable data (UD), and to play the tracks (T) at their actual start positions (AP).

Abstract: Method for reading data from an optical disc comprising a substrate layer, a read-only data layer, and a nonlinear layer with a super-resolution structure disposed on the data layer, the read-only data layer including diffractive pits and lands having a length larger than the diffraction limit of the pickup and super-resolution pits and lands having a length smaller than the diffraction limit of the pickup, the method comprising the steps of using a pickup including a laser for providing a HF signal for retrieving of the data of the data layer, providing a constant laser power for retrieving of the data, and pulsing the laser at the end of a diffractive pit or land. The Apparatus comprises a pickup with a laser and a comparator responsive to a threshold level and to the HF signal, for providing a trigger signal for pulsing of the lamer.

Abstract: A disclosed objective lens includes: a lens having an entrance surface and an emission surface; and an anti-reflection coat formed on the emission surface, wherein a transmittance T1—0 [%] of the anti-reflection coat when an incident angle of a first laser beam having a first wavelength ?1 (390 nm??1?430 nm) is 0°, and the transmittance T1—40 [%] of the anti-reflection coat when the incident angle of the first laser beam is 40° satisfy 0.95?T1—0/T1—40?1.05, and a transmittance T2—0 [%] of the anti-reflection coat when an incident angle of a second laser beam having a second wavelength ?2 (630 nm??2?680 nm) is 0° and a transmittance T2—40 [%] of the anti-reflection coat when the incident angle of the second laser beam is 40° satisfy 0.85?T2—0/T2—40?0.97.

Abstract: An optical disc apparatus includes a focus controller including a first digital filter, tracking controller including a second filter, focus actuator driver, tracking actuator driver, defect detector for detecting a defect on an optical disc, and a system controller for controlling the focus controller, the tracking controller and the defect detector. The system controller holds an input and output of at least one of either the focus controller or the tracking controller on the basis of the output of the defect detector, and sets an initial value in a delay memory of the digital filter of the controller held upon awake of the hold state.

Abstract: In an optical disk library device using a plurality of optical disk devices, before optical disk devices execute recording or reproduction of information to or from optical disks, self-monitoring information is acquired from an optical disk monitor, use preferential orders of the optical disk devices are evaluated on the basis of use frequency information or deterioration information included in the self-monitoring information and an optical disk device to be used for recording or reproduction of information is selected on the basis of the use preferential orders.

Abstract: A change in a property of a signal is detected, the signal having been sensed from a storage medium by a disk drive. A count is determined, the count corresponding to a first location on the storage medium at which the change in the property of the signal sensed from the storage medium is detected. The count is used to predict a second location on the storage medium corresponding to the change in the property of the signal sensed from the storage medium. Relative to the first location on the storage medium, the second location on the storage medium is closer to an actual location of a feature on the storage medium that causes the change in the property of the signal sensed from the storage medium.

Abstract: Provided is a mark forming apparatus including a head unit that forms a mark on a recording medium through laser beam irradiation based on a laser driving pulse, a control signal generation unit that generates a control signal at a start timing of the laser driving pulse supplied to the head unit, a multiplier that multiples a synchronization reference signal used to synchronize with the process of forming the mark on the recording medium in the head unit to generate a multiple signal, and a laser driving pulse generation unit that generates the laser driving pulse by setting the start timing of the laser driving pulse at resolution based on the multiple signal in accordance with the control signal.