SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall, and a second transistor that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall. The first transistor includes a portion of a logic circuit. The second transistor includes a transistor included in a memory cell of a DRAM, or includes a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM. The first gate insulating film has a same thickness as that of the second gate insulating film. The first gate electrode has the same thickness as that of the second gate electrode. A layer structure of the first sidewall is a same as a layer structure of the second sidewall.
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The present application is a Divisional Application of U.S. patent application Ser. No. 12/805,291, filed on Jul. 22, 2010, which is based on Japanese patent application NOs. 2009-190066 and 2010-131424, the entire contents of which are incorporated hereinto by reference.
BACKGROUND1. Technical Field
The present invention relates to a semiconductor device having a sidewall and a method of manufacturing the semiconductor device.
2. Related Art
In recent years, semiconductor devices have been manufactured in which a logic circuit and a memory device such as Dynamic Random Access Memory (DRAM) are integrated onto one substrate. In such semiconductor devices, a transistor included in the logic circuit and a transistor included in a peripheral circuit of the DRAM are generally manufactured by the same process. For this reason, the transistor included in the logic circuit and the transistor included in the peripheral circuit of the DRAM have, in general, mutually the same structure.
On the other hand, it is often the case that the latest transistors have a sidewall and an extension region of a source and drain region. The sidewall covers a sidewall of a gate electrode. The extension region is located under the sidewall, that is, between the source and drain region and the channel region (for example, Japanese Unexamined patent publication NOS. 2000-269351, 2004-349372, 2008-78359, and 2006-196493).
In particular, Japanese Unexamined patent publication NOS. 2004-349372 and 2008-78359 disclose that an N-type MOS transistor and a P-type MOS transistor are made different from each other in width of the sidewall.
In the transistor included in the logic circuit, it is preferable that the on-state current is high. On the other hand, in the transistor connected to a capacitive element, such as the transistor included in the peripheral circuit of the DRAM, it is preferable that the leak current is small. Recently, miniaturization of semiconductor devices has progressed, and the gate length has been shortened with this progress. When the gate length is shortened, the on-state current of the transistor is increased and thus a leak current is easily generated. As mentioned above, in the semiconductor device in which the logic circuit and the transistor connected to the capacitive element are integrated onto one substrate, the transistor included in the logic circuit and the transistor connected to the capacitive element are generally manufactured by the same process. For this reason, in the transistor connected to the capacitive element, the leak current is caused to increase.
SUMMARYIn one embodiment, there is provided a semiconductor device including: a first transistor, formed in a substrate, that includes a first gate insulating film, a source and drain region, a first gate electrode, and a first sidewall; and a second transistor, formed in the substrate, that includes a second gate insulating film, a second gate electrode, a source and drain region, and a second sidewall, wherein the first transistor is a portion of a logic circuit, the second transistor is a transistor included in a memory cell of a DRAM, or is a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM, the first gate insulating film has the same thickness as that of the second gate insulating film, the first gate electrode has the same thickness as that of the second gate electrode, and the width of the second sidewall is larger than the width of the first sidewall.
According to such a semiconductor device, the width of the second sidewall is larger than the width of the first sidewall. For this reason, it is possible that while the on-state current of the first transistor is raised by decreasing the substantial gate length of the first transistor, the leak current of the second transistor is lowered by increasing the substantial gate length of the second transistor.
In another embodiment, there is provided a method of manufacturing a semiconductor device, including: forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which are a portion of a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell of a DRAM or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM; and forming an extension region of the first transistor and an extension region of the second transistor, forming a first sidewall in a sidewall of the first gate electrode, forming a second sidewall having a larger width than that of the first sidewall in a sidewall of the second gate electrode, and forming a source and drain region in each of the first transistor and the second transistor.
According to the invention, it is possible that while the on-state current of the first transistor is raised, the leak current of the second transistor is lowered.
The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
Hereinafter, the embodiment of the invention will be described with reference to the accompanying drawings. In all the drawings, like elements are referenced by like reference numerals and descriptions thereof will not be repeated.
First EmbodimentThe first transistor 100 has two source and drain regions 140. The source and drain regions 140 are respectively provided with an extension region 130. The extension region 130 is the same conductive impurity region as the source and drain regions 140, and has a lower impurity concentration than that of the source and drain regions 140. The extension region 130 is located under the first sidewall 150.
The second transistor 200 has two source and drain regions 240. The source and drain regions 240 are respectively provided with an extension region 230. The extension region 230 is the same conductive impurity region as the source and drain region 240, and has a lower impurity concentration than that of the source and drain region 240. The extension region 230 is located under the second sidewall 250. As mentioned above, the width of the second sidewall 250 is wider than the width of the first sidewall 150. For this reason, the width of the extension region 230 is wider than the width of the extension region 130 of the first transistor 100. Meanwhile, the width of the first sidewall 150 is equal to or greater than 1 nm and equal to or less than 70 nm, and the width of the second sidewall 250 is equal to or greater than 1.4 nm and equal to or less than 100 nm.
In the embodiment, the first gate insulating film 110 has the same not only thickness but also width as the second gate insulating film 210. The first gate electrode 120 has the same not only thickness but also width as the second gate electrode 220. The widths of the first gate electrode 120 and the second gate electrode 220 are equal to or less than, for example, 130 nm.
The capacitive element 300 is, for example, a MIM (Metal-Insulator-Metal) type capacitive element having a cylinder shape, and is a portion of a memory cell of Dynamic Random Access Memory (DRAM). The first transistor 100 is a portion of a logic circuit, and the second transistor 200 is a transistor included in the memory cell of DRAM, or is a portion of a peripheral circuit that performs writing and erasing with respect to DRAM. One side of the source and drain regions 240 of the second transistor 200 is connected to the capacitive element 300, and the other side of the source and drain regions 240 is connected to a bit line 310.
An etching stopper film 30 and an insulating interlayer 40 are in this order formed on the first transistor 100 and the second transistor 200. The etching stopper film 30 is, for example, TEOS, SiO2, SiN, SiON, HDP, PSG, NSG, or BPSG, and functions as an etching stopper at the time of forming a contact hole in the insulating interlayer 40. The insulating interlayer 40 is a multilayer film in which a plurality of insulating films is laminated.
The first sidewall 150 is formed by a first insulating film 152 and a second insulating film 154, and the second sidewall 250 is formed by a first insulating film 252 and a second insulating film 254. The first insulating film 152 is located on the substrate 10 and on the sidewall of the first gate electrode 120, and is formed along the substrate 10 and the sidewall of the first gate electrode 120. The second insulating film 154 is formed on the first insulating film 152. Similarly, the first insulating film 252 is formed on the substrate 10 and on the sidewall of the second gate electrode 220, and the second insulating film 254 is formed on the first insulating film 252. The first insulating film 152 and the first insulating film 252 are the same film, and are formed of, for example, a silicon nitride film. The second insulating film 154 and the second insulating film 254 are the same film, and are formed of, for example, a silicon oxide film.
A concave portion 156 is provided in the end surface of the first insulating film 152 located on the substrate 10, and a concave portion 256 is provided in the end surface of the first insulating film 252 located on the substrate 10. The concave portion 156 is deeper than the concave portion 256. The etching stopper film 30 intrudes into both of the concave portions 156 and 256.
Meanwhile, contact plugs 42, 44, and 46 are buried in the insulating interlayer 40. In addition, an insulating film among interconnects 41 is formed on the insulating interlayer 40. Interconnects 50 and 52 are buried in the insulating film among interconnects 41. The contact plug 42 is connected to the interconnect 50 and one side of the source and drain regions 140 of the first transistor 100. The contact plug 44 is connected to the bit line 310 and one side of the source and drain regions 240 of the second transistor 200, and the contact plug 46 is connected to a lower electrode of the capacitive element 300 and the other side of the source and drain regions 240 of the second transistor 200.
Meanwhile, an device isolation insulating film 20 is formed in the substrate 10. The device isolation insulating film 20 is disposed to isolate each of the first transistor 100 and the second transistor 200 from others.
First, as shown in
Next, ion implantation is performed using the device isolation insulating film 20, the first gate electrode 120, and the second gate electrode 220 as a mask. Thereby, the extension region 130 of the first transistor 100 and the extension region 230 of the second transistor 200 are formed in a self-aligning manner.
Next, as shown in
The thickness of the first insulating film 500 is, for example, equal to or greater than 3 nm and equal to or less 10 nm, and the thickness of the second insulating film 502 is, for example, equal to or greater than 10 nm and equal to or less than 100 nm.
Next, as shown in
After that, as shown in
After that, as shown in
Next, etching is performed using the mask film 530 as a mask. Thereby, the first sidewall 150 is etched, and decreases in width. This etching process includes a wet etching process. For this reason, the concave portion 156 is deepened.
Next, as shown in
After that, the mask film 530 is removed. Thereafter, as shown in
Next, the action and advantages of the embodiment will be described. According to the embodiment, the width of the second sidewall 250 of the second transistor 200 is larger than the width of the first sidewall 150 of the first transistor 100. For this reason, the width of the extension region 230 of the second transistor 200 is larger than the width of the extension region 130 of the first transistor 100. Therefore, it is possible that while the on-state current of the first transistor 100 is raised by decreasing the substantial gate length of the first transistor 100, the leak current of the second transistor 200 is lowered by increasing the substantial gate length of the second transistor 200. For this reason, the holding time of information in the capacitive element 300 can be prolonged.
In addition, the etching stopper film 30 intrudes into the concave portion 156 of the first sidewall 150 and the concave portion 256 of the second sidewall 250, respectively. The concave portion 156 is deeper than the concave portion 256. For this reason, stress generated from the etching stopper film 30 is easily applied to a channel region of the first transistor 100. Therefore, the driving current of the first transistor 100 is increased.
Second EmbodimentFirst, as shown in
Next, as shown in
Next, first insulating film 500 and second insulating film 502 are etched using the mask film 530 as a mask. Thereby, the first sidewall 150 is formed.
Next, as shown in
After that, as shown in
Next, the first insulating film 500 and the second insulating film 502 are etched using the mask film 520 as a mask. Thereby, the second sidewall 250 is formed. At this time, the width of the second sidewall 250 is made larger than the width of the first sidewall 150 by adjusting etching conditions.
Next, as shown in
After that, the mask film 520 is removed. Next, the etching stopper film 30, the insulating interlayer 40, the capacitive element 300, the contact plugs 42, 44, and 46, the insulating film among interconnects 41, and the interconnects 50 and 52 are formed as shown in
It is also possible to obtain the same advantages as those of the first embodiment by the embodiment.
In addition, the logic circuit includes a densely-packed pattern and an isolated pattern, and the DRAM is formed only by a densely-packed pattern in many cases. In anisotropic etching for forming the sidewall, the etching rate in the isolated pattern of the logic circuit is slower than that of the densely-packed pattern. For this reason, it is often the case that the optimum time of etching in the logic circuit is longer than the optimum time of etching in the DRAM.
When the sidewall is formed by the same etching process in the logic circuit and the DRAM circuit, and the etching time is set to the optimum time of etching in the DRAM, the insulating film used as a sidewall in the logic circuit remains in a portion other than the sidewall. On the other hand, when the etching time is set to the optimum time of etching in the logic circuit, the etching amount of the substrate becomes larger in the DRAM and thus a defect occurs in the source and drain region. This defect causes the leak current from the capacitive element and thus the data retention characteristics of the DRAM are deteriorated.
On the other hand, since the first sidewall 150 and the second sidewall 250 are formed by a separate process in the embodiment, the etching conditions for forming each of them can be set to each of the optimum conditions. For this reason, it is possible to suppress the generation of the above-mentioned problems.
Third EmbodimentFirst, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, the third insulating film 504 and the second insulating film 502 are etched using the mask film 550 as a mask, and the first insulating film 500 is further etched. In etching at this time, anisotropic dry etching is used. Thereby, the second sidewall 250 is formed. In this process, the surface of a portion which is not covered with the mask film 550 in the device isolation insulating film 20 is etched. Thereby, a step difference 22 is formed in the device isolation insulating film 20.
After that, as shown in
Next, the third insulating film 504 is etched using the mask film 560 as a mask, and the first insulating film 500 is further etched. In etching at this time, anisotropic dry etching is used. Thereby, the first sidewall 150 is formed. At this time, the width of the first sidewall 150 is made narrower than the width of the second sidewall 250.
Further, in this process, the surface of a portion which is not covered with the mask film 560 in the device isolation insulating film 20 is etched. As described above, the edge of the mask film 560 is kept away at a certain distance from the step difference 22. For this reason, a groove 24 is formed in the surface of the device isolation insulating film 20.
After that, as shown in
Next, as shown in
Next, as shown in
According to the embodiment, it is also possible to obtain the same advantages as those of the first embodiment. In addition, the second insulating film 154 in which the surface layer of the first sidewall 150 is formed is formed by materials different from those of the etching stopper film 30, and this can raise etching selectivity with respect to the etching stopper film 30.
When the whole first sidewall 150 cannot raise etching selectivity with respect to the etching stopper film 30, it is considered that the first sidewall 150 is formed only by the first insulating film 152, for example, as shown in
On the other hand, in the embodiment, the second insulating film 154 in which the surface layer of the first sidewall 150 is formed has a high etching selectivity with respect to the etching stopper film 30 as described above. Therefore, even when the position of the contact hole for burying the contact plug 42 is shifted to thereby overlap with the first sidewall 150, the contact hole does not pass through the first sidewall 150 and thus the leak current of the first transistor 100 is not increased.
In addition, as shown in
On the other hand, in the embodiment, the edge of the mask film 560 is kept away at a certain distance, for example, 20 nm or more from the step difference 22. For this reason, as shown in the plan view of
In addition, since the first sidewall 150 and the second sidewall 250 are formed by a separate process, it is possible to set etching conditions for forming each of them to each of the optimum conditions. For this reason, the insulating film for forming the sidewall is suppressed from remaining on the first gate electrode 120, the second gate electrode 220, or the gate interconnect 400. Therefore, it is possible to form the silicide films 124, 224, and 402 on the entirety of the surfaces of the first gate electrode 120, the second gate electrode 220, and the gate interconnect 400.
Fourth EmbodimentFirst, as shown in
Next, as shown in
Next, as shown in
After that, as shown in
Next, as shown in
After that, as shown in
According to the embodiment, it is also possible to obtain the same advantages as those of the first embodiment.
As described above, although the embodiments of the invention have been set forth with reference to the drawings, they are merely illustrative of the invention, and various configurations other than the foregoing can be adopted.
It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
Claims
1. A semiconductor device, comprising:
- a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall; and
- a second transistor, formed in the substrate, that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall,
- wherein the first transistor comprises a portion of a logic circuit,
- wherein the second transistor comprises a transistor included in a memory cell of a Dynamic Random Access Memory (DRAM), or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM,
- wherein the first gate insulating film has a same thickness as that of the second gate insulating film,
- wherein the first gate electrode has a same thickness as that of the second gate electrode, and
- wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall such that a width of the second sidewall is larger than a width of the first sidewall.
2. The semiconductor device as set forth in claim 1, wherein the first sidewall and the second sidewall include:
- a first insulating film formed over the substrate and over a sidewall of the first gate electrode or the second gate electrode;
- a second insulating film formed over the first insulating film; and
- a concave portion provided in an end surface of the first insulating film which is located over the substrate, and
- wherein a concave portion of the first sidewall is deeper than a concave portion of the second sidewall,
- the semiconductor device further comprising: an etching stopper film, formed over the first transistor and the second transistor, of which a portion intrudes into the concave portion of each of the first sidewall and the second sidewall; and an insulating interlayer located over the etching stopper film.
3. The semiconductor device as set forth in claim 2, wherein the etching stopper film comprises one of TEOS, SiO2, SiN, SiON, HDP, PSG, NSG, and BPSG.
4. The semiconductor device as set forth in claim 1, further comprising:
- an etching stopper film formed over the first transistor and the second transistor;
- an insulating interlayer located over the etching stopper film; and
- a contact which is formed in the insulating interlayer and the etching stopper film, and connected to the source and the drain region of the first transistor,
- wherein at least a surface layer of the first sidewall comprises a material different from that of the etching stopper film.
5. The semiconductor device as set forth in claim 4, wherein the etching stopper film comprises a silicon nitride film, and
- wherein at least the surface layer of the first sidewall comprises a silicon oxide film.
6. The semiconductor device as set forth in claim 5, wherein the first sidewall includes a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in that order.
7. The semiconductor device as set forth in claim 1, further comprising:
- an device isolation film which is buried in the substrate, and is located between the logic circuit and the memory cell;
- a gate interconnect which is formed over the device isolation film, and is connected to the second gate electrode;
- a silicide film formed over the gate interconnect; and
- a groove, formed in the device isolation film, that extends in a direction intersecting the gate interconnect.
8. The semiconductor device as set forth in claim 1, wherein the width of the first sidewall is equal to or greater than 1 nm and equal to or less than 70 nm, and the width of the second sidewall is equal to or greater than 1.4 nm and equal to or less than 100 nm.
9. A semiconductor device, comprising:
- a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode and a first sidewall;
- a second transistor, formed in the substrate, that includes a second gate insulating film, a source and a drain region, a second gate electrode and a second sidewall,
- wherein the first gate insulating film has a same thickness as that of the second gate insulating film,
- wherein the first gate electrode has a same thickness as that of the second gate electrode, and
- wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall such that a width of the second sidewall is larger than a width of the first sidewall.
10. A semiconductor device according to claim 9, wherein the first transistor comprises a portion of a logic circuit, and
- wherein the second transistor comprises a transistor included in a memory cell, or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the memory cell.
11. A semiconductor device according to claim 10, wherein the memory cell comprises a memory cell of a Dynamic Random Access Memory (DRAM).
12. A semiconductor device according to claim 9, wherein the first sidewall and the second sidewall include:
- a first insulating film formed over the substrate and over a sidewall of the first gate electrode or the second gate electrode;
- a second insulating film formed over the first insulating film; and
- a concave portion provided in an end surface of the first insulating film which is located over the substrate, and
- wherein a concave portion of the first sidewall is deeper than a concave portion of the second sidewall,
- the semiconductor device further comprising: an etching stopper film, formed over the first transistor and the second transistor, of which a portion intrudes into the concave portion of each of the first sidewall and the second sidewall; and an insulating interlayer located over the etching stopper film.
13. A semiconductor device according to claim 12, wherein the etching stopper film comprises one of TEOS, SiO2, SiN, SiON, HDP, PSG, NSG, and BPSG.
14. A semiconductor device according to claim 9, further comprising:
- an etching stopper film formed over the first transistor and the second transistor;
- an insulating interlayer located over the etching stopper film; and
- a contact which is formed in the insulating interlayer and the etching stopper film, and connected to the source and the drain region of the first transistor,
- wherein at least a surface layer of the first sidewall comprises a material different from that of the etching stopper film.
15. A semiconductor device according to claim 14, wherein the etching stopper film comprises a silicon nitride film, and
- wherein at least the surface layer of the first sidewall comprises a silicon oxide film.
16. A semiconductor device according to claim 15, wherein the first sidewall includes a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in that order.
17. A semiconductor device according to claim 9, further comprising:
- an device isolation film which is buried in the substrate, and is located between the logic circuit and the memory cell;
- a gate interconnect which is formed over the device isolation film, and is connected to the second gate electrode;
- a silicide film formed over the gate interconnect; and
- a groove, formed in the device isolation film, that extends in a direction intersecting the gate interconnect.
18. A semiconductor device according to claim 9, wherein the width of the first sidewall is equal to or greater than 1 nm and equal to or less than 70 nm, and the width of the second sidewall is equal to or greater than 1.4 nm and equal to or less than 100 nm.
19. A method of manufacturing a semiconductor device, the method comprising:
- forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor, and a second gate insulating film and a second gate electrode of a second transistor;
- forming an extension region of the first transistor and an extension region of the second transistor;
- forming a first sidewall in a side wall of the first transistor;
- forming a second sidewall having a larger width than that of the first sidewall in a sidewall of the second transistor; and
- forming a source and a drain region in each of the first transistor and the second transistor,
- wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall in the semiconductor device.
20. A method of manufacturing a semiconductor device according to claim 19, wherein the first transistor comprises a portion of a logic circuit, and
- wherein the second transistor comprises a transistor included in a memory cell of a Dynamic Random Access Memory (DRAM), or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM.
Type: Application
Filed: Nov 5, 2012
Publication Date: Mar 14, 2013
Applicant: RENESAS ELECTRONICS CORPORATION (Kawasaki-shi)
Inventor: Renesas Electronics Corporation (Kawasaki-shi)
Application Number: 13/669,102
International Classification: G11C 11/409 (20060101); H01L 21/8242 (20060101);