Abstract: A tower computer system includes a tower chassis; a mounting assembly installed at a middle section of a widthwise surface of the tower chassis and coupled to internal sides of the front and rear racks to form a vertical connecting board for providing a longitudinally perpendicular fixing position to a predetermined board, and acting as a longitudinal corresponding line formed by connecting the front rack to the rear rack for the connecting board of the mounting assembly, such that the transverse widthwise surface of the tower chassis is separated into a first assembling chamber with an opening aligned towards the left side and a second assembling chamber with an opening aligned towards the right side; and a first electric connection port, disposed in a vertical direction on the rear rack and at a position proximate to the mounting assembly, and situated in an area inside the first assembling chamber.

Abstract: The present invention provides a removable portable computer device. In an embodiment, the portable computer device includes: a flat panel computer; a base; a back plate; a first connection structure through which the base is connected with the back plate; a second connection structure through which the back plate is connected with the flat panel computer. The flat panel computer is removably connected onto the back plate through the second connection structure. In the present invention, the flat panel computer is removably mounted on the back plate through the second connection structure. When the computer is required to be used at other location and a mass of keyboard input is not needed, it only requires to take off the flat panel computer from the back plate so as to easily carry the computer from one location to another location for use, thus the portability is greatly increased.

Abstract: A power supply assembly includes an enclosure body, a cover panel mounted to the enclosure body, a power supply unit, and a positioning element. The enclosure body includes a bottom panel, a rear panel, and a side panel. The power supply unit is mounted in the enclosure body and is prevented from moving in a first direction substantially perpendicular to the rear panel and a second direction substantially perpendicular to the side panel. The positioning element includes a plate body, a first positioning portion, and a second positioning portion. The power supply unit is sandwiched between the bottom panel and the plate body. The first positioning portion is for preventing the power supply unit from moving along a first direction substantially parallel to the bottom panel. The second positioning portion for preventing the power supply unit from moving along a second direction parallel to the bottom panel.

Abstract: An open frame chassis has a top opening and a bottom opening permitting ambient airflow. A plurality of modules, each enclosing electrical components in thermal contact with a heat sink area of their corresponding module, can each be inserted in the chassis. Ambient air may flow from the bottom opening across the heat sink area of each module to the top opening to passively cool the modules and electrical components. Key pins guide the modules into place and prevent incorrect insertion of a different type of electrical module not corresponding to the electrical connection of the chassis for that slot. Guide pins on corners of the modules mate with guide holes in the chassis to secure the module to the chassis and decrease vibration. Both sides of the chassis have side openings through which the fins of the modules in the end slots of the chassis may be exposed.

Abstract: A storage apparatus includes: a storage drive providing a physical storage area for creating a logical storage area used by an external apparatus; a storage controller including a plurality of central processing units (CPUs) executing data write processing from the external apparatus to the storage drive, and data read processing from the storage drive; a plurality of cooling fans cooling the storage drive; a temperature sensor detecting a temperature of air introduced or discharged by the cooling fans; and a revolving speed sensor detecting a revolving speed of each cooling fan. Any of the CPUs executes operation control processing in which, through a data network path to the storage drive for the data write and read processing, measurement values of the temperature and revolving speed sensors are acquired and a revolving speed setup value of the fans is calculated and is transmitted to the cooling fans.

Abstract: Systems and methods for reducing problems and disadvantages associated with traditional approaches to cooling information handling resources are provided. A method for cooling information handling resources, may include conveying a flowing fluid proximate to one or more information handling resources such that the flowing fluid is thermally coupled to the one or more information handling resources and heat generated by the one or more information handling resources is transferred to the flowing fluid. The method may also include conveying the flowing fluid to a cooling unit such that heat is transferred from the flowing fluid.

Abstract: A fluid cooling system comprising a pipe unit through which coolant fluid flows. The pipe unit is provided with one or more actuators at least a part of which is formed of shape memory alloy. The actuators are configured to extend by applied heat.

Abstract: An electric power conversion apparatus includes: a channel case in which a cooling water channel is formed; a double side cooling semiconductor module that comprises an upper and lower arms series circuit of an inverter circuit; a capacitor module; a direct current connector; and an alternate current connector. The semiconductor module comprises a first and a second heat dissipation metals whose outer surfaces are heat dissipation surfaces, the upper and lower arms series circuit is disposed tightly between the first heat dissipation metal and the second heat dissipation metal, and the semiconductor module further comprises a direct current positive terminal, a direct current negative terminal, and an alternate current terminal which protrude to outside. The channel case is provided with the cooling water channel which extends from a cooling water inlet to a cooling water outlet, and a first opening which opens into the cooling water channel.

Abstract: An electrical component is mounted a circuit board. A case covers the circuit board. The circuit board includes a plate-like metal core and an insulation portion. The insulation portion covers a surface of the metal core. The metal core is provided with a heat radiation portion exposed from the case.

Abstract: An integrated circuit card includes a laminate, solder bumps, a die and a package. The laminate includes a core board sandwiched between two conductive layers. The conductive layers are connected to each other with solder bumps filled in apertures defined in the core board. The die is provided on one of the conductive layers. The package is provided on the die and an area of the conductive layer around the die.

Abstract: The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.

Abstract: The manufacturing method for electronic substrate includes: forming an active region on a first face of a substrate; forming a first part of an interconnection pattern as a passive element on a second face of the substrate; forming an insulating layer as a stress-relieving layer on the second face of the substrate; and forming a second part of the interconnection pattern as the passive element on the insulating layer.

Abstract: An electronic assembly (20; 30; 40; 50) for attachment to a fabric substrate (60; 82, 102) having a conductor pattern (62a-b; 85a-b; 107a-c) on a first side (63; 86; 108) thereof. The electronic assembly comprises an electronic device (23; 42; 64), and at least a first clamping member (21; 41; 65). The electronic assembly is, furthermore, adapted to clamp the electronic device (23; 42; 64) to the first side (63; 86; 108) of the fabric substrate (60; 82, 102) in such a way that the electronic device (23; 42; 64) is electrically connected to the conductor pattern (62a-b; 85a-b; 107a-c).

Abstract: According to one embodiment, an electronic apparatus includes a first housing comprising a first wall and a second wall located on an opposite side of the first wall; a second housing; a hinge configured to connect the first housing to the second housing so that the first housing and the second housing can be pivoted relative to each other; a component housed in a component housing portion formed at the first wall; and a fixing member comprising a housing fixing portion fixed to the first housing, a hinge fixing portion to which the hinge is fixed, and a supporting portion configured to support the component at a location close to the first wall, the supporting portion being located between the first wall and the second wall.

Abstract: An electronic apparatus wiring harness is provided that includes: a fixed-side casing and a moving-side casing, the moving-side casing being provided with a moving-side casing base which is rotatably journalled to the fixed-side casing, and a sliding portion which is provided so as to be slidable on a slide surface provided in the moving-side casing base. The circuit of the sliding portion and the circuit of the fixed-side casing are electrically connected together by an electric wire, which is a wiring harness having a flat cable portion having electric wire bodies arranged in parallel and formed in a tape shape having a jacket strip portion in which a number of the electric wire bodies are bundled; the flat cable portion is arranged in a bent manner so as to form a U shape on the slide surface of the moving-side casing base.

Abstract: A DC-DC converter includes a plurality of switch elements connected in series between both ends of a DC power source, a series circuit of a primary winding of a transformer and a capacitor, connected between a connection point of the plurality of switch elements and an end of the DC power source, a rectifying-smoothing circuit to rectify and smooth a voltage generated by a secondary winding of the transformer into a DC voltage, and a controller to change a switching frequency of the plurality of switch elements according to a feedback signal generated from the DC voltage and alternately turn on/off the plurality of switch elements. The controller includes a nonlinear response unit 11a to nonlinearly change the switching frequency according to a feedback amount represented by the feedback signal.

Abstract: An energy output circuit and its control method includes a switch device (2), a transformer (4) and a controller (1). The switch device (2) is connected between a primary of the transformer (4) and an input power source in series. The controller (1) calculates an energy output waveform and sends a command according to a request or a level to control the switch device (2), to control the on/off time of the primary of the transformer (4). The transformer (4) is an ordinary low-frequency transformer.

Abstract: A power supply including a converter, a capacitance, and a hiccup control module. The converter converts an input voltage to both an output voltage and a preliminary standby voltage when in its active state. The capacitance stores the preliminary standby voltage which is charged to an upper voltage level when the converter is in its active state and which is discharged to a lower voltage level when the converter is in its inactive state. During the standby mode, the hiccup control module operates the converter in hiccup mode by toggling between placing the converter into its inactive state when the preliminary standby voltage is charged to the upper voltage level and placing the converter into its active state when the preliminary standby voltage is discharged to the lower voltage level. The hiccup mode of the power supply eliminates a need for a separate standby converter.

Abstract: An example power supply includes a first power converter, a second power converter, and a shared clamp reset circuit. The first power converter is adapted to convert an input to a first output and includes a first transformer having a first primary winding. The second power converter is also adapted to convert the input to a second output and includes a second transformer having a second primary winding. The second primary winding of the second transformer is not the first primary winding of the first transformer. The shared clamp reset circuit is coupled to the first primary winding of the first transformer and is coupled to the second primary winding of the second transformer to manage leakage inductance energy within the first transformer and within the second transformer.

Abstract: A power supply includes a first power converter having a first transformer coupled to an input of the power supply and to a first output of the power supply. A clamp reset circuit is coupled to the first transformer. The clamp reset circuit includes a capacitor coupled to the first power converter and a Zener diode coupled to the capacitor. A second power converter is coupled to the clamp reset circuit. The second power converter includes a second transformer coupled to the clamp circuit and to a second output of the power supply. The capacitor is coupled to store energy received from the first power converter and the second power converter. The Zener diode is coupled to prevent the energy received from the first power converter and the second power converter from exceeding a threshold. The Zener diode limits voltage on the capacitor.

Abstract: Methods and circuits for synchronous rectifier control are disclosed herein. In one embodiment, a synchronous rectifier control circuit can include: (i) a first sense circuit to sense a voltage between first and second power terminals of a synchronous rectifier device prior to a turn-on of the device, where a timing of the turn-on of the synchronous rectifier device is adjustable using a first control signal generated from the first sense circuit; (ii) a second sense circuit configured to sense a voltage between the first and second power terminals after a turn-off of the device, where a timing of the turn-off of the device is adjustable using a second control signal generated from the second sense circuit; and (iii) a driver control circuit configured to receive the first and second control signals, and to generate therefrom a gate control signal configured to drive a control terminal of the synchronous rectifier device.

Abstract: Constant on-time control circuit includes a comparing circuit including a comparator including a positive input end for receiving a control voltage; a negative input end for receiving a feedback voltage from the output voltage of the DC/DC converter; and an output end for outputting a comparing signal; and a voltage adjusting circuit coupled to the output end of the comparator for adjusting the control voltage; and a pulse generator coupled to the output end of the comparator for generating a pulse signal to control a switch set of the DC/DC converter according to the comparing signal.

Abstract: A method of operating a DC-DC converter according to the current mode control is provided. A current measuring signal for determining a turn-off time of a converter switching element is supplied to a PWM controller and a voltage that is proportional to the current measuring signal is compared by a comparator to a reference voltage. When the reference voltage is exceeded, the converter switching element is turned off.

Abstract: The present power supply device includes a microcomputer that detects a current input to an active filter, a voltage input to the active filter, and a voltage output from the active filter, decreases a target voltage as the input current increases, and controls an IGBT to turn on/off the IGBT to match the input current and the input voltage in phase with each other and also match the output voltage to the target voltage. Thus, as the input current increases, the target voltage is decreased. A power supply terminal can have a voltage with a low noise level.

Abstract: Provided is a DC-DC converter including a soft start circuit capable of prolonging a soft start time without increasing a capacitance used in the soft start circuit. A soft start is implemented by gradually increasing a limiting level of an inductor current or a reference voltage. The soft start time is adjusted by varying a frequency of CLOCK signals supplied to switch circuits. The soft start time may be prolonged without increasing a chip size because the capacitance does not need to be increased to prolong the soft start time.

Abstract: The present invention relates to a control method for a soft switch circuit in a switch power supply, which controls first and second main power switch devices to be turned on and turned off constantly to generate an alternating main power filter current, and controls forward and backward auxiliary switch devices to be turned on and turned off to generate an intermittent alternating resonant current across a resonant branch in the same direction as the main power filter current to thereby achieve zero-voltage turn-on of the first and second main power switch devices; and further controls the forward and backward auxiliary switch devices to be turned on and turned off to generate compensation currents across the resonant branch in the opposite direction to the alternating main power filter current in at least a period of time during resting of the resonant current to thereby accomplish a charging and discharging process of resonant capacitors in a dead time.

Abstract: A switching power supply includes a rectifier circuit, a converter, a detecting unit, a control unit, a switching unit, and a protection unit. The rectifier circuit is used for rectifying an input voltage into a first direct current voltage. The converter is configured for generating a first current according to the first direct current voltage. The detecting unit is used for generating a detected voltage according to the first current. The control unit is configured for generating a control signal. The switching unit is used for enabling the converter, and conducting the first current to the detecting unit when receiving the control signal. The protection unit is configured for shunting the first current with the detecting unit when the first current becomes a large current surge. The control unit stops generating the control signal when determining that the detected voltage is equal to or higher than a predetermined value.

Abstract: A control method implemented in a power converter, such as a variable speed drive, is disclosed. This control method is designed to make the power converter operate when the latter is connected to the network in single-phase mode. The power converter includes a controlled current source connected in series to its DC power supply bus. This controlled current source includes an electronic converter provided with two controlled switching arms. The switching arms are controlled by alternating a modulation phase with a saturation phase, the saturation phase being applied for a determined duration ? in order to make the power converter operate in discontinuous mode.

Abstract: An arrangement for exchanging power, in shunt connection, with a three-phase electric power network includes a Voltage Source Converter having at least three phase legs with each a series connection of switching cells. Each switching cell has at least two semiconductor assemblies connected in series and having each a semiconductor device of turn-off- type and a rectifying element connected in anti-parallel therewith and at least one energy storing capacitor. A control unit is configured to control the semiconductor devices of each switching cell and to deliver a voltage across the terminals thereof being zero or U, in which U is the voltage across the capacitor. The control unit is also configured to calculate a value for amplitude and phase position for a second negative sequence-current or a zero-sequence voltage or a value of a dc current.

Abstract: A switching power controller circuit comprises a first terminal pin for a high potential of a power supply for the controller circuit, a second terminal pin for providing output of switch drive signals and for receiving feedback signals, and a third terminal pin for receiving external current signals and for a low potential of the power supply. The switching power controller further comprises a clock generator, a pulse width modulation (PWM) generator, a reference generator, a power switch driver, a feedback signal sampler, a PWM comparator and a floating sampler.

Abstract: A control device for a rectifier of a switching converter, the converter powered by an input voltage and suitable for providing an output current. The rectifier is suitable for rectifying an output current of the converter and includes at least one transistor. The control device is suitable for driving the at least one transistor. The control device has a first circuit suitable for identifying the start and the end of every converter switching half-cycle and measuring the duration thereof, a second circuit suitable for generating a signal for turning on the transistor after a given number of measured converter switching half-cycles and when the output current of the converter becomes greater than a reference current.

Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

Abstract: A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor substrate to define the active region. A source region and a drain region are spaced apart from each other within the active region with a channel region disposed between the source region and the drain region. A gate electrode crosses over the channel region between the source region and the drain region, and a gate insulating layer is disposed between the gate electrode and the channel region. An edge insulating layer thicker than the gate insulating layer is disposed on a lower surface of the gate electrode around the boundary of the trench isolation region and the active region.

Abstract: Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).

Abstract: A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, which is effective in improving areal efficiency by sharing the latch block among the sub blocks in the unit mat.

Abstract: A nonvolatile semiconductor memory device includes: a memory element in which a rate of charge discharge between two electrodes of the memory element differs according to a logical value of stored information; cell wiring connected to one electrode of the memory element; a sense amplifier having a sense node connected to the cell wiring, the sense amplifier reading the logical value of the information by comparing a potential of the sense node with a reference potential; and a readout control circuit capable of switching between a dynamic sense operation performing readout by precharging the cell wiring and discharging or charging the cell wiring via the memory element and a static sense operation performing readout in a state of a current load being connected to the sense node.

Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.

Abstract: The present invention relates to a memristor, and more particularly, to a method of implementing a memristor-based multilevel memory using a reference resistor array and a write-in circuit and a read-out/restoration circuit for the memristor-based multilevel memory, in which a memristor can be used as a multilevel memory. In the present invention, a reference resistance value is written in a selected memristor of a memristor array by applying repeatedly the current pulses of which widths are proportional to the difference between the resistances of the selected memristor and the selected node of the reference resistor array.

Abstract: A non-volatile semiconductor storage device includes a memory cell array having plural electrically rewritable memory cells, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner, and a data writing unit having a voltage supply circuit which supplies a voltage needed to write data to the plural memory cells, and a resistance state detecting circuit which detects a resistance state of the variable resistive element at the time of writing the data. The data writing unit stops the supply of the voltage to the memory cell where a resistance state of the variable resistive element becomes a desired resistance state, among the plural memory cells, according to the detection result of the resistance state detecting circuit.

Abstract: According to one embodiment, an information recording and reproducing device includes a recording layer and a driving unit. The recording layer includes a first layer containing a first compound. The first compound includes a first positive ion element. The first positive ion element is made of a transition metal element and serves as a first positive ion. The second positive ion element serves as a second positive ion. The driving unit is configured to generate a phase change in the recording layer and to record information by at least one of application of a voltage and application of a current to the recording layer. The coordination number of the first positive ion element at a position of a second coordination of the second positive ion element is 80% or more and less than 100% of the coordination number when the first compound is assumed to be a perfect crystal.

Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.

Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

Abstract: Disclosed are methods, systems and devices including local data lines. In some embodiments, the device includes a local data line connected to a plurality of access devices, at least a portion of a capacitor plate connected to the plurality of access devices, and a global data line connected to the local data line by the capacitor plate.

Abstract: A magnetoresistance effect element includes: a magnetization free layer; a spacer layer provided adjacent to the magnetization free layer; a first magnetization fixed layer provided adjacent to the spacer layer on a side opposite to the magnetization free layer; and at least two second magnetization fixed layers provided adjacent to the magnetization free layer. The magnetization free layer, the first magnetization fixed layer, and the second magnetization free layers respectively have magnetization components in a direction substantially perpendicular to film surfaces thereof. The magnetization free layer includes: two magnetization fixed portions; and a domain wall motion portion arranged between the two magnetization fixed portions. Magnetizations of the two magnetization fixed portions constituting the magnetization free layer are fixed substantially antiparallel to each other in directions substantially perpendicular to the film surface.

Abstract: A memory includes: memory devices that each store data of one bit; and a read unit that, by using one predetermined memory device of the memory devices that are included in a memory block having a predetermined unit number of the memory devices as an inversion flag device, reads out data of (the predetermined unit number ?1) bits that is written in the other memory devices with the bits being inverted in a case where the data of one bit written in the inversion flag device is a first value representing any one of “0” and “1” and directly reads out the data of (the predetermined unit number ?1) bits that is written in the other memory devices in a case where the data of one bit written in the inversion flag device is a second value other than the first value.

Abstract: A magnetoresistive bridge nonvolatile memory device having a flat, continuous folded closed magnetic loop, the magnetic loop having a side for holding four sense metal terminated magnetic shunts, and four planar central parallel rectangular giant magnetoresistive GMR resistors, each of the four central parallel rectangular giant magnetoresistive GMR resistors being located on the side of the continuous folded closed magnetic loop between each of two of the sense metal terminated magnetic shunts, each two of the four sense metal terminated magnetic shunts electrically connected to adjacent ends of a central parallel rectangular giant magnetoresistive GMR resistor.

Abstract: A method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state. The first read current is less than the second read current. Then the first bit line read voltage is compared with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

Abstract: A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and second contact holes. PN diodes are formed in the first contact holes. Heat sinks are formed in the first contact holes on the PN diodes, and contact plugs fill the second contact holes. A second insulation layer having third contact holes is formed on the first insulation layer. Heaters fill the third contact holes. A stack pattern of a phase change layer and a top electrode is formed to contact the heaters. The heat sink quickly cools heat transferred from the heater to the phase change layer.

Abstract: A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to a number of activated comparison signals for each comparison event, as well as according to a ratio of a set current pulse width and a reset current pulse width as applied to the of phase-change memory cells.