Abstract: An organic light emitting device includes an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode laminated in this order, wherein the hole injection layer comprises a mixture of an inorganic material comprising at the least of one of an alkali metal oxide, an alkaline earth metal oxide, a halogen compound of an alkali metal, a halogen compound of an alkaline earth metal, and an organic material comprising at least one of compounds represented by Formula 1: wherein R1, R2, R3, R4, R5 and R6 are each independently selected from a substituted or unsubstituted C6 to C30 aromatic group and a C5 to C29 heterocyclic group containing N, S, or O, wherein the substituent is selected from a C1 to C6 aliphatic group and a C6 to C12 aromatic group.

Abstract: A light-emitting device having the quality of an image high in homogeneity is provided. A printed wiring board (second substrate) (107) is provided facing a substrate (first substrate) (101) that has a luminous element (102) formed thereon. A PWB side wiring (second group of wirings) (110) on the printed wiring board (107) is electrically connected to element side wirings (first group of wirings) (103, 104) by anisotropic conductive films (105a, 105b). At this point, because a low resistant copper foil is used to form the PWB side wiring (110), a voltage-drop of the element side wirings (103, 104) and a delay of a signal can be reduced. Accordingly, the homogeneity of the quality of an image is improved, and the operating speed of a driver circuit portion is enhanced.

Abstract: The present invention provides, among other things, a copolymer comprising at least one donor monomer and at least one acceptor monomer. The polymer may optionally further comprise at least one additional comonomer. The polymers are useful as a charge-transport, semiconducting, electrochemical conducting, photoconducting, or light emitting material. Microelectronic devices comprising such polymers (e.g., as a heterojunction therein) are also described.

Abstract: An organic electroluminescence device, including: an anode; a cathode opposed to the anode; and a first emitting layer and a second emitting layer between the anode and the cathode in this sequence from the anode, wherein: the first emitting layer and the second emitting layer each include a host and a phosphorescent dopant; the host of the first emitting layer and the host of the second emitting layer each have a triplet energy of 2.8 eV or more; the host of the first emitting layer has an ionization potential of 5.5 eV or less; and an affinity Af1 of the host of the first emitting layer is smaller than an affinity Af2 of the host of the second emitting layer.

Abstract: The present invention relates to a light emitting device comprising: a transparent substrate (11); partially transparent an anode layer (12) or layer assembly arranged on said substrate (11); a light emitting layer (13) arranged on said anode layer (12); and a transparent cathode layer (14) arranged on said light emitting layer; (13) wherein said anode layer (12) or layer assembly comprises a first surface (15) facing said substrate (11) and a second surface (16) facing said light emitting layer (13) and is positioned opposite to said first surface (15); said first surface (15) comprises a transparent conductive material; said second surface (16) comprises first (17) and second domains (18); said first domains (17) are conductive and non-transparent; said second domains (18) are transparent and electrically isolating; and said first domains (17) are in direct contact with said light emitting layer (13) and are arranged to allow electrical contact between said first surface (15) and said light emitting layer (

Abstract: An organic electroluminescence display unit including: a lower electrode for each device; a first hole injection/transport layer provided on the lower electrode for each device; a second organic light emitting layer of the first color provided on the first hole injection/transport layer for the second organic electroluminescence device; a second hole injection/transport layer provided on the entire surfaces of the second organic light emitting layer and the first hole injection/transport layer for the first organic electroluminescence device, and being made of a low molecular material; a blue first organic light emitting layer provided on the entire surface of the second hole injection/transport layer; and an electron injection/transport layer having at least one of electron injection characteristics and electron transport characteristics, and an upper electrode that are provided in sequence on the entire surface of first organic light emitting layer.

Abstract: A thin film transistor includes a contact layer that contains an organic semiconductor material and an acceptor material or a donor material provided between an organic semiconductor layer and a source electrode/a drain electrode.

Abstract: An organic EL display includes: lower electrodes arranged on a substrate so as to correspond to red, green and blue organic EL elements, respectively; hole injection/transport layers arranged on the lower electrodes so as to correspond to the red, green and blue organic EL elements, respectively, the hole injection/transport layers having one or both of hole injection and hole transport properties; red and green organic light-emitting layers arranged on the hole injection/transport layers for the red and green organic EL elements, respectively, and including a low-molecular material; a blue organic light-emitting layer arranged on whole surfaces of the red and green organic light-emitting layers and the hole injection/transport layer for the blue organic EL element; and an electron injection/transport layer and an upper electrode arranged on a whole surface of the blue light-emitting layer, the electron injection/transport layer having one or both of electron injection properties and electron transport proper

Abstract: The present invention is to provide a method of favorably forming an organic EL device with the inverted structure by the wet process. On that account, an organic EL device includes a cathode, an electron injection layer, a light emitting layer, a hole transport layer, a hole injection layer, an anode are formed in this order on a substrate. The electron injection layer is formed by applying ink between banks and drying the ink. The ink is formed by dissolving a polymer compound having an organic phosphine oxide skeleton in an alcohol solvent. The light emitting layer is formed by applying ink between components of the bank and the drying the ink. The ink is formed by dissolving material for light emitting layer such as polyphenylene vinylene (PPV) derivative or polyfluorene derivative in a nonpolar solvent.

Abstract: When attaching a substrate with an EL element formed thereon and a transparent sealing substrate, the periphery of a pixel portion is surrounded with a first sealing agent that maintains a gap between the two pieces of substrates, an entire surface of the pixel portion is covered with a second transparent sealing agent so that the two pieces of substrate is fixed with the first sealing agent and the second sealing agent. Consequently, the EL element can be encapsulated by curing the first sealing agent and the second sealing agent without enclosing a drying agent and doing damage to the EL element due to UV irradiation even when a sealing device only having a function of UV irradiation is used.

Abstract: An organic electroluminescent device including a driving element having a driving gate electrode connected to the switching element, the driving gate electrode formed uniformly on the substrate, a driving source electrode having a first driving source electrode along a first direction and a plurality of second driving source electrodes extending from the first driving source electrode along a second direction crossing the first direction, a driving drain electrode spaced apart from the driving source electrode, the driving drain electrode having a first driving drain electrode along the first direction and a plurality of second driving drain electrodes extending from the first driving drain electrode along the second direction, wherein the plurality of second driving source electrodes alternate with the plurality of second driving drain electrodes, wherein the driving source electrode and the driving drain electrode including an interval therebetween are facing the driving gate electrode.

Abstract: A method for manufacturing an organic semiconductor layer formed of a mixture of a first and of a second organic semiconductor materials includes the steps of: forming a porous solid volume formed of the first semiconductor material, of intercommunicating porosity and capable of receiving a second semiconductor material; depositing, at least on an external surface of the porous solid volume, a liquid including the second semiconductor material dissolved or dispersed in a solvent, the solvent being inert with respect to the first semiconductor material and having an evaporation temperature lower than the evaporation temperature of the second semiconductor material; and once the porous solid volume has been at least partially impregnated with the liquid, evaporating the solvent by heating up to a temperature higher than the evaporation temperature of said solvent and lower than the evaporation temperature of the first and of the second semiconductor materials.

Abstract: The present invention relates to an electronic device comprising anode, cathode and at least one organic layer which comprises a compound of the formula (I) to (IV). The invention furthermore encompasses the use of compounds of the formula (I) to (IV) in an electronic device and to a compound of the formula (Ic) to (IVc).

Abstract: An active matrix substrate includes a plurality of pixel electrodes (19a) arranged in a matrix, and a plurality of TFTs (5a) connected to the respective corresponding pixel electrodes (19a). Each TFT (5a) includes a gate electrode (11aa) provided on an insulating substrate (10a), a gate insulating layer (12) covering the gate electrode (11aa), an oxide semiconductor layer (13a) provided on the gate insulating layer (12) over the gate electrode (11aa) and having a channel region (C), and a source electrode (16aa) and a drain electrode (16b) provided on the oxide semiconductor layer (13a), overlapping the gate electrode (11aa) and facing each other with the channel region (C) being interposed between the source and drain electrodes. A protection insulating layer (17) made of a spin-on glass material is provided on the channel region (C) of the oxide semiconductor layer (13a).

Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Abstract: A transistor which includes an oxide semiconductor and can operate at high speed is provided. A highly reliable semiconductor device including the transistor is provided. An oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer formed in a groove of a base insulating layer. The channel formation region is embedded in a position overlapping with a gate electrode which has a side surface provided with a sidewall. The groove includes a deep region and a shallow region. The sidewall overlaps with the shallow region, and a connection portion between a wiring and the electrode layer overlaps with the deep region.

Abstract: The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.

Abstract: To provide a miniaturized transistor having favorable electric characteristics. An oxide semiconductor layer is formed to cover a source electrode layer and a drain electrode layer, and then regions of the oxide semiconductor layer which overlap with the source electrode layer and the drain electrode layer are removed by polishing. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing the regions of the oxide semiconductor layer overlapping with the source electrode layer and the drain electrode layer. Further, a sidewall layer having conductivity is provided on a side surface of a gate electrode layer in a channel length direction; thus, the sidewall layer having conductivity overlaps with the source electrode layer or the drain electrode layer with a gate insulating layer provided therebetween, and a transistor substantially including an Lov region is provided.

Abstract: In a transistor using an oxide semiconductor, entry of hydrogen atoms into an oxide semiconductor film adversely affects reliability. Water is a typical substance including a hydrogen atom, which could enter a semiconductor device after manufacture. Thus, an object of the invention is to reduce the amount of substances including a hydrogen atom, particularly water, entering a semiconductor device using an oxide semiconductor. It was found that a silicon oxynitride film with high density sufficiently prevents entry of water, and does not swell much even in the atmosphere containing water. Accordingly, a silicon oxynitride film with high density is provided as a protective film so as to prevent entry of water into a semiconductor device using an oxide semiconductor. Specifically, a silicon oxynitride film used as the protective film has a density of 2.32 g/cm3 or more.

Abstract: A semiconductor device that is less influenced by variations in characteristics between transistors or variations in a load, and is efficient even for normally-on transistors is provided. The semiconductor device includes at least a transistor, two wirings, three switches, and two capacitors. A first switch controls conduction between a first wiring and each of a first electrode of a first capacitor and a first electrode of a second capacitor. A second electrode of the first capacitor is connected to a gate of the transistor. A second switch controls conduction between the gate and a second wiring. A second electrode of the second capacitor is connected to one of a source and a drain of the transistor. A third switch controls conduction between the one of the source and the drain and each of the first electrode of the first capacitor and the first electrode of the second capacitor.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, a channel layer, and a passivation layer. The channel layer has a first surface and an opposed second surface, where the first surface is disposed over at least a portion of the gate dielectric. The channel layer also has a first oxide composition including at least one predetermined cation. The passivation layer is disposed adjacent to at least a portion of the opposed second surface of the channel layer. The passivation layer has a second oxide composition including the at least one predetermined cation of the first oxide composition and at least one additional cation that increases a bandgap of the passivation layer relative to the channel layer.

Abstract: An object is to provide a semiconductor device including a thin film transistor with excellent electrical characteristics and high reliability and a method for manufacturing the semiconductor device with high mass productivity. A main point is to form a low-resistance oxide semiconductor layer as a source or drain region after forming a drain or source electrode layer over a gate insulating layer and to form an oxide semiconductor film thereover as a semiconductor layer. It is preferable that an oxygen-excess oxide semiconductor layer be used as a semiconductor layer and an oxygen-deficient oxide semiconductor layer be used as a source region and a drain region.

Abstract: An ultraviolet sensor has a p-type semiconductor layer composed of a solid solution of NiO and ZnO, and an n-type semiconductor layer composed of ZnO and joined to the p-type semiconductor layer such that a part of the surface of the p-type semiconductor layer is exposed. In the p-type semiconductor layer, trivalent Ni is contained in a crystal grain in a state of being solid-solved with the solid solution of NiO and ZnO. The trivalent Ni can be contained in the crystal grain of the p-type semiconductor layer by adding NiOOH to NiO and ZnO, and firing the resulting mixture. Thereby, an inexpensive ultraviolet sensor capable of being downsized, which can easily detect the intensity of ultraviolet light by a photovoltaic power without utilizing a peripheral circuit can be realized.

Abstract: The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.

Abstract: An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad.

Abstract: A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

Abstract: A display device according to an exemplary embodiment of the present invention includes a display portion including a plurality of display pixels displaying an image and a dummy portion including a plurality of dummy pixels formed in a periphery region of the display portion. An electrostatic test element group (TEG) may be formed in at least one of the dummy pixels.

Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling.

Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.

Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.

Abstract: An image sensor array includes image sensors having photo TFTs to generate photocurrent in response to received images. The photo TFTs each have their respective gate electrodes and source electrodes independently biased to reduce the effects of dark current. Storage capacitors are coupled to each photo TFT and discharged upon generation of a photocurrent. Each storage capacitor is coupled to a readout TFT that passes a current from the storage capacitor to a data line. The photo TFT may be disposed above the storage capacitor to increase the exposed surface area of the photo TFT.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.

Abstract: To suppress a decrease in on-state current in a semiconductor device including an oxide semiconductor. Provided is a semiconductor device including the following: an oxide semiconductor film which serves as a semiconductor layer; a gate insulating film including an oxide containing silicon, over the oxide semiconductor film; a gate electrode which overlaps with at least the oxide semiconductor film, over the gate insulating film; and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In the semiconductor device, the oxide semiconductor film overlapping with at least the gate electrode includes a region in which a concentration of silicon distributed from the interface with the gate insulating film toward the inside of the oxide semiconductor film is lower than or equal to 1.1 at. %.

Abstract: The concentration of impurity elements included in an oxide semiconductor film in the vicinity of a gate insulating film is reduced. Further, crystallinity of the oxide semiconductor film in the vicinity of the gate insulating film is improved. A semiconductor device includes an oxide semiconductor film over a substrate, a source electrode and a drain electrode over the oxide semiconductor film, a gate insulating film which includes an oxide containing silicon and is formed over the oxide semiconductor film, and a gate electrode over the gate insulating film. The oxide semiconductor film includes a region in which the concentration of silicon is lower than or equal to 1.0 at. %, and at least the region includes a crystal portion.

Abstract: The present invention provides a TFT-LCD array substrate having a gate-line metal layer, a data-line metal layer crossing the gate-line metal layer and a plurality of layers covering a periphery of the gate-line metal layer and the data-line metal layer; the gate-line metal layer has first gate lines and second gate lines parallel and alternately arranged, the date-line metal layer has first data lines and second data lines parallel and alternately arranged; the first gate line and the second gate line are electrically connected; the first data line and the second data line are electrically connected. The present invention further provides a manufacturing method of the TFT-LCD array substrate. Implementing the TFT-LCD array substrate and the manufacturing method can reduce the occurrence of line-broken in the active array of TFT-LCD, increase the aperture ratio of the product and enhance yield rate of the products.

Abstract: In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.

Abstract: The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip configuration on the insulating substrate and comprising a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a surface of the semiconductor substrate, and a drain pad electrode disposed on a back side surface of the semiconductor substrate; agate connector disposed on the gate pad electrode; and a source connector disposed on the source pad electrode. The gate connector, the gate pad electrode and the signal wiring electrode are bonded, and the source connector, the source pad electrode and the power wiring electrode are bonded, by using solid phase diffusion bonding.

Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.

Abstract: A nitride semiconductor growth substrate includes a principal surface including a C-plane of a sapphire substrate, and a convex portion that is formed on the principal surface, has a cone or pyramid shape or a truncated cone or pyramid shape, is disposed to form a lattice pattern in a top view thereof, and includes a side surface inclined at an angle of less than 90 degrees relative to the principal surface. The convex portion has a height of 0.5 to 3 ?m from the principal surface. A distance between adjacent ones of the convex portion is 1 to 6 ?m. The side surface of the convex portion has a surface roughness (RMS) of not more than 10 nm.

Abstract: A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

Abstract: A transistor which includes an electron transit layer and an electron supply layer which are stacked in a thickness direction of a substrate; an electron transit layer formed over the substrate in parallel to the electron transit layer and the electron supply layer; an anode electrode which forms a Schottky junction with the electron transit layer; and a cathode electrode which forms an ohmic junction with the electron transit layer are provided. The anode electrode is connected to a source of the transistor, and the cathode electrode is connected to a drain of the transistor.

Abstract: Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a plurality of lamination units being continuously laminated. The lamination unit includes: a composition modulation layer formed of a first and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein; a termination layer formed on an uppermost portion of the composition modulation layer, the termination layer acting to maintain the compressive strain existing in the composition modulation layer; and a strain reinforcing layer formed on the termination layer, the strain reinforcing layer acting to enhance the compressive strain existing in the composition modulation layer.

Abstract: A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.

Abstract: A light-emitting diode (LED) and fabricating method thereof. The method includes: providing a first substrate and forming an epitaxial portion on the first substrate; forming at least one reflection layer on the epitaxial portion; forming a metal barrier portion on the reflection layer; etching the epitaxial portion and the barrier portion by a first etching process, so as to form a plurality of epitaxial layers and a plurality of metal barrier layers, an etch channel is formed between adjacent epitaxial layers, and each metal barrier layer enwraps a corresponding reflection layer and covers all of a surface of a corresponding epitaxial layer; forming a first bonding layer on the metal barrier layer; and forming a second substrate on the first bonding layer and removing the first substrate.

Abstract: Single crystal substrates are made of silicon carbide, and each have a first front-side surface and a first backside surface opposite to each other. A support substrate has a second front-side surface and a second backside surface opposite to each other. A connection layer has silicon carbide as a main component, and lies between the single crystal substrates and the support substrate for connecting each of the first backside surfaces and the second front-side surface such that each of the first backside surfaces faces the second front-side surface.

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract: Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.

Abstract: A light emitting device includes: a light emitting unit and a light receiving unit which are provided on a same substrate, wherein the light emitting unit includes an active layer sandwiched between a first clad layer and a second clad layer, a first electrode electrically connected to the first clad layer, and a second electrode electrically connected to the second clad layer.