Abstract: A physically uncloneable function (PUF) sense and response module fabricated from a stack of integrated circuit chip layers. At least one of the PUF chips in the stack has a unique identifier resulting from random effects of fabrication processes. The PUF chip generates the fingerprint at power-on resulting that in turn is used to generate a private key. The private key generates a public key used to communicate with the outside world. The encrypted data from the outside world is decrypted with the private key. The public key is stored for comparison with pubic keys generated at subsequent power-up operations. If the key changes, tampering is indicated and a predetermined tamper response event is generated such as the erasing of the contents of a memory.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: Electronic interface and method for reading a capacitive sensor that includes one input capacitor (30) or several input capacitors, in which the capacitive sensor is excited with a two-level voltage (Vlow, Vhigh) and read by a charge-sense amplifier whose output is sampled in four successive instants. An evaluation unit (333) is arranged to compute two difference values (V12, V34) between two pairs of samples corresponding to different voltage levels and to combine said difference values into an output value (V_out_raw) proportional to the charge transferred to the input of the charge-sense amplifier and an error value (error_bit) sensitive to a time derivative of a noise current din/dt.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: The present invention relates to a driver unit that locates the transmitter, which transmits magnetic field around the card insertion slot in order to prevent fraud in self-service terminals (SST) such as ATM, which enables transactions with magnetic tape cards.

Abstract: In a multiphase electrical power assignment, a processor: receives instructions to connect a bi-directional power device to a multiphase premise power source; determines that the power device is to be coupled to a target phase's phase connection; confirms that the power device is not coupled to any phase connections; and couples the power device to the phase connection, where the power device's power signal is synchronized with the phase connection's power signal. When the power device is in a connected state, the processor: issues a command to place each phase connection switch in an open state; in response to confirming that the phase connection switches are in the open state, issues commands to the power device so that a power signal of the power device will be synchronized with the target phase; and closes the phase connection switch corresponding to the target phase.

Abstract: A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit.

Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.

Abstract: The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

Abstract: An ILFD controller sets a control parameter on the basis of a frequency of a frequency-divided signal and a frequency of a reference signal measured by a clock counter. A VCO controller selects an oscillation band that defines an oscillation frequency of a VCO and also selects an oscillation band of the VCO on the basis of the frequency of the reference signal and a frequency of a frequency-divided signal that is a result obtained by frequency-dividing an output signal, which is delivered from the VCO in response to the selected oscillation band, by means of an ILFD and a frequency divider.

Abstract: The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b1, b2, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b1, b2, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate.

Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.

Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.

Abstract: A method and a circuit configuration are provided for generating a multiphase PWM signal. For this purpose a number of PWM generators are provided, which respectively have one counter, two comparators and one state memory, each PWM generator outputting a PWM signal, which represents a phase of the multiphase PWM signal, the PWM generators being coupled with one another via multiplexers such that the counters of the PWM generators that are coupled with one another are clocked identically.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: A voltage controlled variable resistor circuit is configured to variably attenuate a variable source signal. A fixed attenuation circuit is coupled to receive the variable source signal and output an attenuated variable source signal. The variable source signal is further applied across a variable resistive divider formed of a fixed resistive circuit and a variable resistive circuit. The variable resistive circuit has a first input configured to receive the attenuated variable source signal and a second input configured to receive a variable resistance control signal. The variable resistive circuit is configured to have a resistance which is variable in response to the attenuated variable source signal and the variable resistance control signal.

Abstract: An embodiment of the invention provides an electronic device. The electronic device includes a digital-to-analog converter (DAC), a transmitter front-end (TX FE), an amplifier, an analog-to-digital converter (ADC), and a swap circuitry. The TX FE has a first and a second input end coupled to a first and a second output end of the DAC, respectively. The ADC has a first and a second input end coupled to a first and a second output end of the amplifier, respectively. The swap circuitry is configured to couple the first and second output ends of the DAC to a first and a second input end of the amplifier in a normal state, respectively, and couple the first and second output ends of the DAC to the second and first input ends of the amplifier in a swapped state, respectively.

Abstract: A low-side off-detection signal compares the gate signal of a low-side transistor with a predetermined first level to generate a low-side off-detection signal indicating that the low-side transistor is off. The low-side detection transistor is of the same type as the low-side transistor, with the source connected to the ground terminal, and the gate receiving the low-side transistor gate signal. A first resistor is arranged between the drain of the low-side detection transistor and the power supply terminal. A first bypass circuit is arranged in parallel with the first resistor, and is configured to switch to the conduction state when a control signal is a level which instructs the low-side transistor to switch off, and to switch to the cut-off state when the control signal level instructs the low-side transistor to switch on. The drain signal of the low-side detection transistor is output as the low-side off-detection signal.

Abstract: A detection device includes a resonance unit having a coil and a capacitor, an oscillation unit for oscillating the resonance unit, and a signal processing unit for detecting the oscillation state of the resonance unit and outputting an object detection signal when oscillation is stopped. The signal processing unit intermittently executes a self-diagnosis mode by forcibly oscillating the oscillation unit to determine whether or not an abnormality occurs in the resonance unit.

Abstract: A device includes a source for transmitting an electronic charge through a conduction path; a drain for receiving the electronic charge; a stack for providing at least part of the conduction path; and a gate operatively connected to the stack for controlling a conduction of the electronic charge. The stack includes an insulator layer, an N-polar layer and a barrier layer selected such that, during an operation of the device, the conduction path formed in the N-polar layer includes a two-dimensional electron gas (2DEG) channel and an inversion carrier channel.

Abstract: A memory element capable of operating at high speed and reducing power consumption and a signal processing circuit including the memory element are provided. As a writing transistor, a transistor which is formed using an oxide semiconductor and has significantly high off-state resistance is used. In a memory element in which a source of the writing transistor is connected to an input terminal of an inverter, a control terminal of a transfer gate, or the like, the threshold voltage of the writing transistor is lower than a low-level potential. The highest potential of a gate of the writing transistor can be a high-level potential. When the potential of data is the high-level potential, there is no potential difference between a channel and the gate; thus, even when the writing transistor is subsequently turned off, a potential on the source side hardly changes.

Abstract: A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed.

Abstract: An integrated circuit for providing a differential interface for an envelope tracking signal is described. The integrated circuit includes a subtraction module having a first input for receiving a digital envelope tracking signal and a second input for receiving a second signal, wherein the subtraction module is arranged to subtract the second signal from the digital envelope tracking signal and produce an envelope tracking signal with a reduced average direct current (DC) component; a digital-to-analog converter (DAC) arranged to receive the envelope tracking signal with the reduced average DC component and produce a differential analog version thereof; and a modulator operably coupled to a differential output of the DAC, wherein the modulator comprises a DC input point arranged to insert a DC component into the differential analog version of the envelope tracking signal.

Abstract: A PAPR observation unit that measures PAPR in a distributed output of an input signal and PAPR in a combined output of a linear transmission path and a third order distortion generation path, a distortion observation unit that observes distortion in the output of a power amplifier, and a controller are provided, where the controller includes a third order out-of-band distortion compensation coefficient control unit that adjusts coefficients corresponding to an outside of an input signal band among frequency characteristic compensator coefficients on the basis of distortion observed by the distortion observation unit and a third order in-band distortion coefficient control unit that adjusts coefficients corresponding to an inside of the input signal band among frequency characteristic compensator coefficients on the basis of the observed PAPR.

Abstract: There is provided a power amplifier capable of compensating for a distortion without deteriorating a gain of input voltage. The power amplifier includes an input terminal to which an input voltage is applied; a class AB power amplification circuit connected to the input terminal; and an element connected between the input terminal and the class AB power amplification circuit, turned on when the input voltage is equal to or greater than a predetermined value, and varying impedance thereof according to the input voltage.

Abstract: A switching amplifying method or a switching amplifier for obtaining one or more linearly amplified replicas of an input signal, is highly efficient, and does not have the disadvantage of “dead time” problem related to the class D amplifiers. Said switching amplifier comprises: an inductance means; a switching unit for switching a current from a DC voltage to the inductance means; a switching power transmitting unit for blocking a current when the switching unit switches on, and conducting the current from the inductance means to a filter unit positively or negatively according to the polarity of the input signal when the current from the DC voltage to the inductance means is switched off; an amplifier control unit to control the switching unit and the switching power transmitting unit according to the input signal; said filter unit filtering the current from the switching power transmitting unit to get an output signal.

Abstract: First and second channel bridge amplifiers are dynamically configured to drive either speakers or headphones. The first channel bridge amplifier includes a first amplifier driving one end of a first speaker through a mechanical switch in a headphone-jack, and a second amplifier driving another end of the first speaker. The second channel bridge amplifier includes third and fourth amplifiers driving respective ends of a second speaker. To suppress click and pop, an amplifier control circuit maintains certain amplifiers (depending on headphone or speaker mode) tri-stated until input coupling capacitors have fully charged and an input signal exceeding a predetermined amount is detected.

Abstract: A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.

Abstract: There is provided an integrated circuit comprising a main push-pull amplifier (108, 110) with balanced outputs and an additional push-pull amplifier (862, 863) with balanced outputs. Each of these balanced outputs is connected to an off-chip load (822) via respective bonding wires (818, 828, 830, 880) to provide a combined amplified signal to the load. The additional amplifier serves to compensate for crossover distortions generated by the main amplifier.

Abstract: A power amplifier tube and a power amplification method are disclosed in the present invention. The power amplifier tube includes a high voltage heterojunction bipolar transistor (HVHBT) power amplifier tube core and a high electron mobility transistor (HEMT) power amplifier tube core, and the HVHBT power amplifier tube core and the HEMT power amplifier tube core are integrated in the same encapsulation. In the present invention, it should be configured as a Doherty amplifier, and the power tube is designed in a breakthrough combination manner of new power amplifier tube cores, compared with all the existing Doherty amplifiers which employ LDMOS power amplifier tube cores, the power amplification with high efficiency can be achieved on the basis of ensuring small volume of power amplifier tube.

Abstract: Disclosed herein is a circuit for preventing an element from being damaged although output impedance of a final transistor is changed in a power amplifier. The power amplifier includes: a power stage amplifying a signal; a transformer connected to an output terminal of the power stage and coupling a signal output from the power stage; and a controller controlling a bias voltage from the power stage according to the coupled signal. Although output impedance is changed, damage to the power amplifier can be prevented. Also, the power amplifier can be automatically controlled to maintain performance thereof by sensing an operational state in which output impedance is normal.

Abstract: The low-noise amplifier with through mode is configured such that a source grounded transistor and a gate grounded transistor are connected in cascode, and a load impedance element and a switching transistor are serially connected between the drain of the gate grounded transistor and a power supply, and a through pass circuit is connected between an input terminal and an output terminal. The gate voltage of the gate grounded transistor is regulated by a bias circuit and the voltage of a mode control terminal is converted by a level shifter to control the gate voltage of the switching transistor, whereby, in the case of using only transistors whose terminal-to-terminal breakdown voltages are each equal to or less than the power supply voltage, it becomes feasible to prevent voltages equal to or more than the terminal-to-terminal breakdown voltages from being applied between the terminals of each transistor.

Abstract: Circuitry, which includes a linear amplifier and a linear amplifier power supply, is disclosed. The linear amplifier at least partially provides an envelope power supply signal to a radio frequency (RF) power amplifier (PA) using a selected one of a group of linear amplifier supply voltages. The linear amplifier power supply provides at least one of the group of linear amplifier supply voltages. Selection of the selected one of the group of linear amplifier supply voltages is based on a desired voltage of the envelope power supply signal.

Abstract: A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.

Abstract: An oscillator circuit includes an amplifier including at least two terminals for receiving a crystal and an automatic amplitude control loop coupled to the amplifier including biasing circuitry switched between a first operational mode and a second operational mode. The first operational mode occurs during an initial time period and the second operational mode occurs after the initial time period is expired. The biasing circuitry includes first and second PMOS transistor circuits, each transistor circuit including an unswitched PMOS transistor and a switched PMOS transistor. Alternatively, the biasing circuitry can include first and second NMOS transistor circuits, each transistor circuit including an unswitched NMOS transistor and a switched NMOS transistor. The biasing circuitry is under control of an internally generated control signal.

Abstract: An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array.

Abstract: Methods and apparatus for tuning devices having mechanical resonators are described. In one implementation, a mechanical resonator and a phase shifter are configured in a feedback loop, so that the phase shifter shifts the phase of the resonator output signal. The amount of phase shift induced by the phase shifter may be variable. In another implementation, an LC tuning subcircuit is coupled to a mechanical resonator. In some implementations, the LC tuning subcircuit has a variable capacitance. One or more of the apparatus described herein may be implemented as part, or all, of a microelectromechanical system (MEMS).

Abstract: The invention concerns an oscillator generating a wave composed of a frequency of on the order of terahertz from a beat of two optical waves generated by a dual-frequency optical source (10). The oscillator comprises: a modulator (12) the transfer function of which is non-linear for generating harmonics with a frequency of less than one terahertz for each of the optical waves generated by the dual-frequency optical source, an optical detector (14) able to detect at least one harmonic for each of the optical waves generated by the dual-frequency optical source and transforming the harmonics detected into an electrical signal, a phase comparator (15) for comparing the electrical signal with a reference electrical signal, means (16) for controlling at least one element of the dual-frequency optical source with a signal obtained from the signal resulting from the comparison.

Abstract: A push-push oscillator circuit with a first oscillation branch with a first active device and a first tank adapted to provide a signal having a fundamental frequency f0, a second oscillation branch with a second active device and a second tank symmetrical to the first oscillation branch and adapted to provide a signal having the fundamental frequency f0. Output branches are coupled to the first oscillation branch and the second oscillation branch to provide signals having the second harmonic frequency 2f0 of the fundamental signal based on the signals having the fundamental frequency f0 and/or to provide signals having the fundamental frequency f0; The push-push oscillator circuit further comprises at least one terminal branch with a terminal adapted to provide a component of a differential signal having the second harmonic frequency 2f0 or the fundamental frequency f0. The at least one terminal branch comprises a RF stub.

Abstract: A variable frequency oscillator includes an inductance unit having a first inductance, a first variable capacitor coupled across the inductance unit, and a second variable capacitor coupled across a part of the inductance unit. The inductance of the part of the inductance unit coupled by the second variable capacitor is a proportion of the first inductance.

Abstract: A tunable inductor circuit is disclosed. The tunable inductor circuit includes a first inductor. The tunable inductor circuit also includes a second inductor in parallel with the first inductor. The tunable inductor circuit also includes a switch coupled to the second inductor. A resistance of the switch is added in parallel to the first inductor based on operation of the switch.

Abstract: Injection locked dividers provide a divided clock signal after being driven by a injected clock signal that is a multiple of the divided clock signal. At injected clock signal at 60 GHz generates a differential 30 GHz clock signal. One innovative construction of the injection locked oscillator reduces the internal capacitive at a node by associating the parasitic capacitance at this node with the inductors of the tapped inductor resonant circuit. This provides more energy flow in the injection pulses applied to the legs of the injection locked circuit providing an increase locking range.

Abstract: The present invention discloses an oscillating device for frequency detection, an ultrasonic transceiver system and a frequency detection method thereof. The oscillating device for frequency detection, which is applicable for detecting a transducer having a lowest impedance frequency and a highest impedance frequency, comprises an oscillating circuit. The oscillating circuit has a loop gain whose maximum value occurs at the lowest impedance frequency of the transducer and whose minimum value occurs at the highest impedance frequency of the transducer, wherein a difference of a phase of the loop gain and an impedance phase of the transducer is zero between the lowest impedance frequency and the highest impedance frequency, and the loop gain is of a value greater than 1 at a frequency where the phase difference is zero.

Abstract: A high-frequency module has a structure including balanced terminals, with high design flexibility and good transmission characteristics. Wiring patterns to be connected to balanced terminals of SAW filters of SAW duplexers are located on a second layer to a sixth layer of a layered body. The characteristic impedances of first wiring patterns defining a pair of parallel or substantially parallel lines match, the characteristic impedances of second wiring patterns defining a pair of parallel or substantially parallel lines match, the characteristic impedances of third wiring patterns defining a pair of parallel or substantially parallel lines match, and the characteristic impedances of fourth wiring patterns defining a pair of parallel or substantially parallel lines match.

Abstract: A circuit card is provided that includes ground traces that extend from a resistor to a commoning bar, where a resultant electrical length between the resistor and the commoning bar and is configured to reduce energy carried on the ground terminals that could otherwise result in cross-talk. In an embodiment, the ground trace may be configured in a meandering manner. In another embodiment, the ground trace may be split and joined by an inductor.

Abstract: A device for improving the filter effect of a filter connected up between an electrical energy source and a source of interference is provided. The filter is configured to feed back interference transients from ground to an input of the source of interference generating the interference transients. The device includes a measuring device for determining a leakage current flowing through the filter and a final control element configured to modify a limit frequency of the filter such that the leakage current through the filter is damped to below a predefined level if the measuring device detects the leakage current.

Abstract: A directional coupler is disclosed integrated on a single chip and an integrated circuit based on a standard CMOS process and relates to a field of radio frequency communication. In exemplary implementations, by using a standard CMOS process technology, the directional coupler integrated by a CMOS process is formed by a coil winded by a upper layer of metal lines, a coil winded by a lower layer of metal lines, two tuning capacitor array, and a matching resistor. Two terminals of the coil are a direct terminal and an input terminal; two terminals of the coil are a coupled terminal and an isolation terminal; the terminals of the coils and are intersected at 90°; the coil is winded by an upper metal layer and the coil is winded by a lower metal layer. Further, the insertion loss is low and the isolation degree is large.

Abstract: In a directional coupler, sub-lines or main lines are electromagnetically coupled to each other to degrade isolation characteristics. A capacitor is located between the sub-lines or between the main lines to cause the isolation characteristics to have poles in order to improve the isolation characteristics of the directional coupler.

Abstract: A filter includes: a coupled multi-mode acoustic wave filter connected between an input terminal and an output terminal; a first inductor connected between the coupled multi-mode acoustic wave filter and a ground terminal; an acoustic wave resonator, one end of which is connected between the input terminal or the output terminal and the coupled multi-mode acoustic wave filter; and a second inductor connected between another end of the acoustic wave resonator and the ground terminal.

Abstract: In an example embodiment, an in-phase recombinant waveguide combiner/divider device can comprise: a single waveguide input; N waveguide outputs, wherein N is an integer greater than 2; a first waveguide dividing portion; a second waveguide dividing portion; a third waveguide dividing portion; and a waveguide combining portion. The waveguide combining portion can be configured to combine two signals that are each respectively received from the second waveguide dividing portion and third waveguide dividing portion. In general an in-phase recombinant waveguide combiner/divider can comprise more junctions than output ports of a conservative power divider network structure. In an example embodiment, for a N-way waveguide power divider, there can be at least N+1 waveguide junctions.