Patents Issued in June 6, 2013
  • Publication number: 20130143387
    Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
    Type: Application
    Filed: November 19, 2012
    Publication date: June 6, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Publication number: 20130143388
    Abstract: A method for manufacturing a semiconductor device includes forming a starting-point crack on a cleavage line on a surface of a semiconductor substrate; forming preliminary cracks intermittently along the cleavage line on the surface of the semiconductor substrate; and cleaving the semiconductor substrate along the cleavage line passing through the preliminary cracks, from the starting-point crack, wherein each of the preliminary cracks has a crack joining the cleavage line from outside of the cleavage line, in a direction of a progress of cleaving.
    Type: Application
    Filed: August 17, 2012
    Publication date: June 6, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Katsumi ONO, Masato NEGISHI, Masato SUZUKI
  • Publication number: 20130143389
    Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.
    Type: Application
    Filed: January 16, 2013
    Publication date: June 6, 2013
    Applicant: Silicon Genesis Corporation
    Inventor: Silicon Genesis Corporation
  • Publication number: 20130143390
    Abstract: A dicing/die bonding integral film of the present invention includes a base film, a pressure-sensitive adhesive layer which is formed on the base film and to which a wafer ring for blade dicing is bonded, and a bonding layer formed on the adhesive layer and having a central portion to which a semiconductor wafer to be diced is bonded, wherein a planar shape of the bonding layer is circular, an area of the bonding layer is greater than an area of the semiconductor wafer and smaller than an area of each of the base film and the adhesive layer, and a diameter of the bonding layer is greater than a diameter of the semiconductor wafer and less than an inner diameter of the wafer ring, and a difference in diameter between the bonding layer and the semiconductor wafer is greater than 20 mm and less than 35 mm,
    Type: Application
    Filed: July 13, 2011
    Publication date: June 6, 2013
    Applicant: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Rie Katou, Takayuki Matsuzaki, Shinya Katou, Ryoji Furutani, Tatsuya Sakuta, Kouji Komorida
  • Publication number: 20130143391
    Abstract: Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Te LIN, Chih-Lin WANG, Yi-Huang WU, Tzong-Sheng CHANG
  • Publication number: 20130143392
    Abstract: A method of fabricating a diode in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface and forming a n-type GaN drift layer coupled to the first surface of the n-type GaN substrate. The method also includes forming an in-situ SixNy layer coupled to the n-type GaN drift layer opposite the n-type GaN substrate and at least partially removing portions of the SixNy layer and the n-type GaN drift layer to form a plurality of void regions and a remaining portion of the SixNy layer. The method further includes selectively regrowing a p-type epitaxial layer in the void regions.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: EPOWERSOFT, INC.
    Inventors: Linda Romano, David P. Bour, Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, Thomas R. Prunty
  • Publication number: 20130143393
    Abstract: Provided is an apparatus for manufacturing a compound semiconductor, which forms a compound semiconductor layer using a metal-organic chemical vapor deposition method. The apparatus is characterized in that: the apparatus is provided with a reaction container, a holder, which is disposed in the reaction container and has placed thereon a subject, on which the layer is to be formed, the subject having facing up the subject surface where the layer is to be formed, and a raw material supply port, through which the raw material gas of the compound semiconductor is supplied to the inside of the reaction container from the outside; the holder is in contact with the lower surface of the subject, the contact being inside of the outer circumferential portion of the subject to the center of the upper surface of the holder; and that the holder has a supporting portion, which supports the subject such that a predetermined interval is maintained between the upper surface of the holder and the lower surface of the subject.
    Type: Application
    Filed: August 16, 2011
    Publication date: June 6, 2013
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Hideki Yasuhara, Akira Bandoh
  • Publication number: 20130143394
    Abstract: A method of forming a semiconductor substrate including forming a base layer of a Group 13-15 material on a growth substrate during a growth process, forming a mask having mask regions and gap regions overlying the base layer during the growth process, and preferentially removing a portion of the base layer underlying the mask during the growth process.
    Type: Application
    Filed: November 19, 2012
    Publication date: June 6, 2013
    Applicant: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
    Inventor: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
  • Publication number: 20130143395
    Abstract: A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 6, 2013
    Inventors: Chan-Long Shieh, Gang Yu
  • Publication number: 20130143396
    Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.
    Type: Application
    Filed: November 20, 2012
    Publication date: June 6, 2013
    Applicant: UNIVERSITY OF SOUTH CAROLINA
    Inventor: UNIVERSITY OF SOUTH CAROLINA
  • Publication number: 20130143397
    Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C.M. Fuller, Pratik P. Joshi, Mahmoud Khojasteh, Rajiv M. Ranade, George G. Totir
  • Publication number: 20130143398
    Abstract: A method for manufacturing a MOSFET includes the steps of: preparing a substrate made of silicon carbide; forming a drain electrode making ohmic contact with the substrate; and forming a backside pad electrode on and in contact with the drain electrode. The drain electrode formed in the step of forming the drain electrode is made of an alloy containing Ti and Si. Further, the backside pad electrode formed is maintained at a temperature of 300° C. or smaller until completion of the MOSFET. Accordingly, the manufacturing process can be efficient while achieving excellent adhesion between the electrodes.
    Type: Application
    Filed: September 11, 2012
    Publication date: June 6, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroyuki Kitabayashi, Hideto Tamaso, Taku Horii
  • Publication number: 20130143399
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Application
    Filed: January 31, 2013
    Publication date: June 6, 2013
    Applicant: International Rectifier Corporation
    Inventor: International Rectifier Corporation
  • Publication number: 20130143400
    Abstract: A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 6, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Publication number: 20130143401
    Abstract: Disclosed methods cap exposed surfaces of copper lines with a layer of metal or metal-containing compound combined with silicon. In some cases, the metal or metal-containing compound forms an atomic layer. In certain embodiments, the methods involve exposing the copper surface first to a metal containing precursor to form an atomic layer of adsorbed precursor or metal atoms, which may optionally be converted to an oxide, nitride, carbide, or the like by, e.g., a pinning treatment. Subsequent exposure to a silicon-containing precursor may proceed with or without metallic atoms being converted.
    Type: Application
    Filed: June 1, 2012
    Publication date: June 6, 2013
    Inventors: Jengyi Yu, Gengwei Jiang, Pramod Subramonium, Roey Shaviv, Hui-Jung Wu, Nagraj Shankar
  • Publication number: 20130143402
    Abstract: The disclosure provides a method for forming a dense Cu thin film by atomic layer deposition, comprising the following steps of: (A) providing an additive gas; (B) choosing a copper-containing metal-organic complex as a precursor; (C) using a carrier gas to introduce the additive gas into the precursor cell mixing with the precursor; (D) pre-depositing the precursor on the surface of the substrate with a TaNx thin film at a first temperature; (E) removing the excess copper-containing metal-organic complex and the excess additive gas; (F) introducing a reducing gas into the reactive system and annealing at a second temperature to reduce the Cu2O thin film to form a Cu thin film on the substrate and (G) removing the excess reducing gas from the reactive system.
    Type: Application
    Filed: February 15, 2013
    Publication date: June 6, 2013
    Applicant: NANMAT TECHNOLOGY CO., LTD.
    Inventor: Nanmat Technology Co., Ltd.
  • Publication number: 20130143403
    Abstract: Disclosed herein is an etching composition for texturing a crystalline silicon wafer, comprising, based on a total amount of the composition: (A) 0.1 to 20 wt % of an alkaline compound; (B) 0.1 to 50 wt % of a cyclic compound having a boiling point of 100° C. or more; (C) 0.00001 to 10 wt % of a silica-containing compound; and (D) residual water. The etching composition can maximize the absorbance of light of the surface of a crystalline silicon wafer.
    Type: Application
    Filed: August 12, 2011
    Publication date: June 6, 2013
    Applicant: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Hyung-Pyo Hong, Jae-Youn Lee, Dae-Sung Lim
  • Publication number: 20130143404
    Abstract: The polishing liquid according to the embodiment comprises abrasive grains, an additive and water, wherein the abrasive grains satisfy either or both of the following conditions (a) and (b). (a) Producing absorbance of at least 1.50 for light with a wavelength of 400 nm in an aqueous dispersion with a content of the abrasive grains adjusted to 1.0 mass %, and also producing light transmittance of at least 50%/cm for light with a wavelength of 500 nm in an aqueous dispersion with a content of the abrasive grains adjusted to 1.0 mass %. (b) Producing absorbance of at least 1.000 for light with a wavelength of 290 nm in an aqueous dispersion with a content of the abrasive grains adjusted to 0.0065 mass %, and also producing light transmittance of at least 50%/cm for light with a wavelength of 500 nm in an aqueous dispersion with a content of the abrasive grains adjusted to 1.0 mass %.
    Type: Application
    Filed: January 31, 2013
    Publication date: June 6, 2013
    Inventors: Tomohiro IWANO, Takenori NARITA, Daisuke RYUZAKI
  • Publication number: 20130143405
    Abstract: A silicon-wafer processing fluid used for processing a silicon wafer contains a friction modifier containing a nitrogen-containing compound, pH of the nitrogen-containing compound being in a range from 2 to 8 when a mass ratio with water (i.e. nitrogen-containing compound/water) is 1/99. The nitrogen-containing compound is preferably a heterocyclic compound. The silicon-wafer processing fluid restrains an abrasion of abrasive grains rigidly attached to a wire and generation of hydrogen.
    Type: Application
    Filed: August 23, 2011
    Publication date: June 6, 2013
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventor: Tomohiko Kitamura
  • Publication number: 20130143406
    Abstract: A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Rung Hsu, Sung-Hsun Wu, Kuo Bin Huang
  • Publication number: 20130143407
    Abstract: The present invention relates to a method for producing a thin single crystal silicon having large surface area, and particularly relates to a method for producing a silicon micro and nanostructure on a silicon substrate (or wafer) and lifting off the silicon micro and nanostructure from the silicon substrate (or wafer) by metal-assisted etching. In this method, a thin single crystal silicon is produced in the simple processes of lifting off and transferring the silicon micro and nanostructure from the substrate by steps of depositing metal catalyst on the silicon wafer, vertically etching the substrate, laterally etching the substrate. And then, the surface of the substrate is processed, for example planarizing the surface of the substrate, to recycle the substrate for repeatedly producing thin single crystal silicons. Therefore, the substrate can be fully utilized, the purpose of decreasing the cost can be achieved and the application can be increased.
    Type: Application
    Filed: March 7, 2012
    Publication date: June 6, 2013
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: CHING-FUH LIN, TZU-CHING LIN, SHU-JIA SYU
  • Publication number: 20130143408
    Abstract: Method of forming a protective hard mask layer on a substrate in a semiconductor etch process, comprising the step of applying by solution deposition on the substrate a solution or colloidal dispersion of an alumina polymer, said solution or dispersion being obtained by hydrolysis and condensation of monomers of at least one aluminium oxide precursor in a solvent or a solvent mixture in the presence of water and a catalyst. The invention can be used for making a hard mask in a TSV process to form a high aspect ratio via a structure on a semiconductor substrate.
    Type: Application
    Filed: March 29, 2010
    Publication date: June 6, 2013
    Applicant: SILECS OY
    Inventors: Juha T Rantala, Thomas Gädda, Wei-Min Li, David A. Thomas, William McLaughlin
  • Publication number: 20130143409
    Abstract: Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure.
    Type: Application
    Filed: January 31, 2013
    Publication date: June 6, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Frank Scott JOHNSON
  • Publication number: 20130143410
    Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 6, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Publication number: 20130143411
    Abstract: Disclosed are systems and methods for improving front-side process uniformity by back-side metallization. In some implementations, a metal layer can be formed on the back side of a semiconductor wafer prior to certain process steps such as plasma-based processes. Presence of such a back-side metal layer reduces variations in, for example, thickness of a deposited and/or etched layer resulting from the plasma-based processes. Such reduction in thickness variations can result from reduced variation in radio-frequency (RF) coupling during the plasma-based processes. Various examples of wafer types, back-side metal layer configurations, and plasma-based processes are disclosed.
    Type: Application
    Filed: November 15, 2012
    Publication date: June 6, 2013
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventor: Skyworks Solutions, Inc.
  • Publication number: 20130143412
    Abstract: A method and apparatus for preparing thin TEM samples in a manner that reduces or prevents bending and curtaining is realized. Embodiments of the present invention deposit material onto the face of a TEM sample during the process of preparing the sample. In some embodiments, the material can be deposited on a sample face that has already been thinned before the opposite face is thinned, which can serve to reinforce the structural integrity of the sample and refill areas that have been over-thinned due to a curtaining phenomena. In other embodiments, material can also be deposited onto the face being milled, which can serve to reduce or eliminate curtaining on the sample face.
    Type: Application
    Filed: May 25, 2012
    Publication date: June 6, 2013
    Applicant: FEI Company
    Inventors: Michael Moriarty, Stacey Stone, Jeff Blackwood
  • Publication number: 20130143413
    Abstract: The back side of a wafer having a plurality of devices formed on the front side thereof is ground to thereby reduce the thickness of the wafer. A resin layer is formed on the front side of the wafer and is cured. The resin layer is planarized while the back side of the wafer is held on a chuck table and the resin layer formed on the front side of the wafer is exposed. The resin layer is bonded to a hard plate through a bonding member, and the back side of the wafer is ground by using a grinding unit of a grinding apparatus to thereby reduce the thickness of the wafer to a predetermined thickness while the hard plate bonded to the wafer is held on a chuck table of the grinding apparatus.
    Type: Application
    Filed: November 29, 2012
    Publication date: June 6, 2013
    Applicant: DISCO CORPORATION
    Inventor: Disco Corporation
  • Publication number: 20130143414
    Abstract: Embodiments of methods for fabricating polymer nanostructures and nanostructured electrodes are disclosed. Material layers are deposited onto polymer nanostructures to form nanostructured electrodes and devices including the nanostructured electrodes, such as photovoltaic cells, light-emitting diodes, and field-effect transistors. Embodiments of the disclosed methods are suitable for commercial-scale production of large-area nanostructured polymer scaffolds and large-area nanostructured electrodes.
    Type: Application
    Filed: August 11, 2011
    Publication date: June 6, 2013
    Applicant: Arizona Board of Regents on Behalf of the University of Arizona
    Inventors: Jayan Thomas, Nasser N. Peyghambarian, Robert A. Norwood, Palash Gangopadhyay
  • Publication number: 20130143415
    Abstract: Provided are atomic layer deposition apparatus and methods including a gas distribution plate comprising a plurality of elongate gas ports including at least one first reactive gas port in fluid communication with a first reactive gas and at least one second reactive gas port in fluid communication with a gas manifold. The gas manifold is in fluid communication with at least a second reactive gas different from the first reactive gas and a purge gas. Also provided are atomic layer deposition apparatus and methods including linear energy sources in one or more of region before the gas distribution plate and a region after the gas distribution plate.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Joseph Yudovsky, Mei Chang, Steven D. Marcus, Garry K. Kwong
  • Publication number: 20130143416
    Abstract: A technique comprising: using a laser beam to ablate a target surface (2) via projection lens (12) as part of a process of defining one or more elements of one or more electronic devices, wherein the ablating is performed whilst extracting material ablated from the target surface via an extraction device inlet (6) having at least a portion at a level between said target surface (2) and said projection lens (12) and at the level of a plume of ablated material above said target surface.
    Type: Application
    Filed: June 3, 2011
    Publication date: June 6, 2013
    Applicant: PLASTIC LOGIC LIMITED
    Inventor: Shane Norval
  • Publication number: 20130143417
    Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.
    Type: Application
    Filed: November 16, 2012
    Publication date: June 6, 2013
    Inventor: STEPHEN MOFFATT
  • Publication number: 20130143418
    Abstract: A method of performing rapid thermal annealing on a substrate including heating the substrate to a first temperature in a rapid thermal annealing system having a front-side heating source and a backside heating source. The method further includes raising the temperature of the substrate from the first temperature to a second temperature greater than the first temperature. The backside heating source provides a greater amount of heat than the front-side heating source during the raising of the temperature of the substrate.
    Type: Application
    Filed: January 30, 2013
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung TSAI, Chii-Ming WU, Da-Wen LIN
  • Publication number: 20130143419
    Abstract: An electronic apparatus assembly including an electronic apparatus and a detachable connector is provided. The electronic apparatus has a cavity, a first magnetic element and a set of first terminals. The first magnetic element and the set of first terminals are disposed in the cavity. The detachable connector has an inserting portion, a body portion, a second magnetic element and a set of second terminals. The inserting portion is adapted to be inserted into the cavity. The body portion is connected to the inserting portion. The second magnetic element and the set of second terminals are disposed on the inserting portion. When the inserting portion is inserted into the cavity, the first magnetic element and the second magnetic element are mutually attracted. The two sets of terminals are mutually contacted, and the body portion is adapted to be supported on a plane to stand the electronic apparatus on the plane.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: HTC CORPORATION
    Inventors: Chih-Sheng Wei, Chin-Chung Shih, Chih-Shan Yeh, Yuan-Hung Chang
  • Publication number: 20130143420
    Abstract: The present invention is an electrical connector in which a substrate (such as a printed circuit board or PCB) includes a plurality of apertures (or vias) and some of those apertures are filled with two materials to improve the characteristics of the electrical interconnection. The preferred process of crating the filled vias includes the steps of plating the vias with an electrically-conductive material to create an electrically-conductive path between portions of the substrate and components associated with the substrate and partially filling the apertures, then filling at least a portion of the apertures or vias with a second or different filling material to seal at least apart of the electrically conductive path through the plating. The second filling material may be chosen to provide thermal compensation for the connection.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: David Noel Light, Dinesh Sundararajan Kalakkad, Peter Tho Nguyen
  • Publication number: 20130143421
    Abstract: The present invention relates to a USB connector, which comprises: a connector main body having its front being downwardly extended thereby forming a stop part having a first lead angle; and a substrate having plural first contact pads and plural second contact pads, so as to form a USB connector. Said USB connector allows a USB2.0 connector and a USB3.0 connector to be respectively inserted.
    Type: Application
    Filed: March 21, 2012
    Publication date: June 6, 2013
    Inventors: Chia-Hsin Tsai, Charles C. Lee
  • Publication number: 20130143422
    Abstract: Disclosed herein is a power connector. The power connector includes a body, a power source terminal provided in the body, and connected with a power source line, a ground terminal provided in the body, and connected with a ground line, and an interference removal unit connected between the power source terminal and the ground terminal to remove electromagnetic interference. Here, a stop band filter is formed inside the power connector, so that parasitic component signals generated in the internal power source line are prevented from being transmitted as a constant power source even though a separate EMI filter is not formed inside the system. In addition, noise signals included in the constant power source are removed, thereby realizing smooth power supply.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 6, 2013
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Samsung Electro-Mechanics Co., Ltd.
  • Publication number: 20130143423
    Abstract: A connector, an electrified grid element and the combination. First and second contacts with first and second contact portions are secured in the housing of the connector. The second contact portion is offset from a first surface of the connector a greater distance that the first contact portion. An electrified grid has a first conductor and a second conductor, with the first conductor having an opposite polarity to the second conductor. A first insulator member is positioned proximate the first conductor and a second insulator member is positioned proximate the second conductor. The first and second insulator members prevent the mating of the connector to the electrified grid unless the connector is properly oriented in the electrified grid, thereby insuring proper polarity between the connector and the electrified grid.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventors: Marek LUKSIC, Philip Clay BRANDBERG
  • Publication number: 20130143424
    Abstract: In an electrical plug connector comprising an insulating contact adapter the contact adapter has a first wing which can be pivoted between an open and a closed position. The contact adapter is designed to enclose a metal contact element between the first wing and a wall of the contact adapter when the first wing is in the closed position.
    Type: Application
    Filed: August 8, 2011
    Publication date: June 6, 2013
    Applicant: TYCO ELECTRONICS AMP GMBH
    Inventors: Lam Nguyen Nhu, Uwe Gassauer, Stefan Konrad Nagel
  • Publication number: 20130143425
    Abstract: The invention relates to a connection assembly (1) for closing an electric contact, comprising a connection part (3) having at least one first electric contact (5, 17) and a movable cover element (6, 15) for covering the contact (5, 17) and a base part (10) that can be connected to the connection part (3) and that has at least one second electric contact (6, 15), wherein the connection part (3) comprises an opening (4, 20) that can be closed by the cover element (6, 15). The cover element (6) is arranged such that, when the connection part (3) is connected to the base part (10), it exposes the opening (4) such that the first contact (5, 17) is connected to the second contact (6, 15) in a conductive manner.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 6, 2013
    Applicant: MSX Technology AG
    Inventor: Albin Smrke
  • Publication number: 20130143426
    Abstract: A busbar of the present invention increases yield per metal material in comparison to plate-shaped bus bars, enables provision of protrusions on a member located inside relative to a conductor, and enables formation of the busbar in a bent shape. The busbar of the present invention is provided with a busbar insulator (22), a busbar conductor (23), a busbar insulator (24), a busbar conductor (25), and a busbar insulator (26) formed outside of a busbar center conductor (21). These conductors and insulators are arranged alternately from the inner side towards the outer side in a radial direction (R) that intersects at right angles with the axial direction (A) of the bus bar. The busbar conductors (23, 25) are provided with openings (23o, 25o) along the whole length in the axial direction (A) thereof.
    Type: Application
    Filed: September 27, 2011
    Publication date: June 6, 2013
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Naoya Fujiwara, Akio Sugimoto, Hiroshi Hashimoto, Takayasu Fujiura, Naoki Kikuchi, Koji Inoue
  • Publication number: 20130143427
    Abstract: Electrical connector assemblies, light bases with one or more electrical connector assemblies, and methods for connecting one or more electrical wires to one or more sheet-metal connectors are disclosed. An electrical connector assembly for an electrical distribution system is disclosed, which includes an electrically insulated housing with a wire-connection port and a blade-connection port. The wire-connection port is designed to receive an electrical wire, while the blade-connection port is designed to receive an electrically conductive blade. An electrical conductor is disposed within the housing, extending between the blade-connection and wire-connection ports. A first threadless fastener secures the wire in the wire-connection port and electrically couples the wire to the electrical conductor. A second threadless fastener secures the blade in the blade-connection port and electrically couples the blade to the electrical conductor.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: Schneider Electric USA, Inc.
    Inventors: Paula Bulnes Abundis, Fabiola Gutiérrez Gómez
  • Publication number: 20130143428
    Abstract: A locking socket includes a shell and a buckle mechanism. The shell forms a slot and plug holes adapted for receiving a plug. The buckle mechanism is pivotably disposed to the shell and is exposed out of the shell via the slot. The buckle mechanism further forms a buckle portion which is able to alternatively lock on or release the plug when the buckle mechanism pivots so that the locking socket of the present invention is adapted for the plug to insert in. Also, the buckle mechanism alternatively abuts against the plug to prevent the plug from detachment. Thereby, the present invention provides a locking socket with simpler structure, improved structure intensity, and better positioning.
    Type: Application
    Filed: December 1, 2012
    Publication date: June 6, 2013
    Inventor: CHI-TSAI CHANG
  • Publication number: 20130143429
    Abstract: To prevent, with a simple structure, damage on a component such as a conductive contact at the time of operation of an actuator, an actuator pinching a signal transmission medium by being moved to a connection acting position facing a wiring board is provided with a protective projection protruding toward the wiring board with the actuator being moved to the connection acting position. With this, a gap between the actuator and the printed wiring board is covered with the protective projection from outside, the components such as conductive contacts disposed inside the gap between the actuator and the printed wiring board are prevented from being in contact with a nail of an operator.
    Type: Application
    Filed: August 2, 2011
    Publication date: June 6, 2013
    Applicant: DAI-ICHI SEIKO CO., LTD.
    Inventor: Yoshinobu Shimada
  • Publication number: 20130143430
    Abstract: The invention relates to a coaxial connector with a female and a male connector part. The two connector parts each have an inner ventilation channel which extends in the longitudinal direction of the connector and which opens out into at least one outwardly extending, stepped (when viewed in the longitudinal section) ventilation channel.
    Type: Application
    Filed: May 5, 2011
    Publication date: June 6, 2013
    Inventors: Edén Sorolla Rosario, Michael Mattes, Daniel Schonherr, David Raboso Garcia-Baquero, Josef Fuchs, Holger Karstensen
  • Publication number: 20130143431
    Abstract: A transfer plug assembly includes a first plug, first flexible link, second flexible link, and a second plug. A first end of each the first flexible link and the second flexible link are connected to two lateral sides of the first plug respectively. A second end of each the first flexible link and the second flexible link are connected to two lateral sides of the second plug respectively. The second plug serves to connect the first plug. Through the linking of the first and second flexible links, the second plug will hang around the first plug and is accessible nearby. The flexible linking of the first and second links will provide free movability between the first plug and the second plug.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Inventor: Po-Hsun Lin
  • Publication number: 20130143432
    Abstract: A straddled vehicle is provided which is equipped with a charging port structure in which a charging port is fixedly disposed within a recess provided in a wall member, a base end part of a cover member that is capable of closing the charging port is pivotably supported at a position adjacent to the charging port, and a lid that is capable of closing the recess so as to cover the cover member from the outside is pivotably supported on the wall member, wherein retaining means (93) retains a closed state of the lid (77) in response to the lid (77) being closed, releasing means (94) is operable so as to release the retention of the closed state of the lid (77) by the retaining means (93), and coupling means (95) is operable in association with operation of the retaining means (93) when closing the lid (77) and pivots the cover member (76) toward the closing side. Thus it is possible to prevent closing of a lid from being forgotten while reducing the cost of surface treatment, etc. of a cover member and the lid.
    Type: Application
    Filed: June 9, 2011
    Publication date: June 6, 2013
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Yusaku Yamashita, Hiroshi Iwakami, Hiroyuki Shinmura
  • Publication number: 20130143433
    Abstract: A connection terminal includes a bushar, wherein at least one insertion opening for accommodating a bridging device is formed on the bushar, wherein the insertion opening is designed in the form of a material passage having a hole collar, wherein the hole collar of the material passage encircles the insertion opening. The hole collar extends away from the surface of the bushar in the opposite direction to the insertion direction of the bridging device.
    Type: Application
    Filed: June 30, 2011
    Publication date: June 6, 2013
    Applicant: PHOENIX CONTACT GMBH & CO. KG
    Inventor: Ralph Hoppmann
  • Publication number: 20130143434
    Abstract: A connector assembly for installation on a ceiling grid having conductors therein. Contacts are mounted in a housing of the connector, with the contacts having contact portions. Mounting members are mounted in the housing, with the mounting members having grid mounting sections. A cam member is provided in the housing, with the cam member being movable between a first position and a second position. As the cam member is moved from the first position to the second position, the cam member biases the contact portions of the contacts into electrical engagement with the conductors of the ceiling grid and biases the grid mounting sections of the mounting members into mechanical engagement with the ceiling grid to provide a mechanical connection between the ceiling grid and the connector.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventors: Edmund Luther JACOBS, Marek LUKSIC, Philip Clay BRANDBERG
  • Publication number: 20130143435
    Abstract: A terminal in accordance with one exemplary embodiment of the present disclosure includes a terminal body, a substrate mounted onto the terminal body, and a socket module coupled to the substrate to transfer an electrical signal by being electrically connected to an inserted plug, and the socket module includes a housing having an opening at one surface thereof, the plug being inserted into the opening, and a coupling unit formed at at least one side of the housing, and slidable with respect to the substrate upon being coupled to the substrate. This may allow a substrate assembly coupled with the socket module to become slimmer by a thickness of the substrate, resulting in providing a more size-reduced terminal.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 6, 2013
    Applicant: LG ELECTRONICS INC.
    Inventor: LG ELECTRONICS INC.
  • Publication number: 20130143436
    Abstract: A connector for installation on a grid having conductors therein and a method of installation therefore. The connector has a housing with at least one contact mounted in the housing which makes an electrical connection with the conductors of the grid when the connector is mated with the grid. At least one mounting member is movable between a first position in which a grid mounting section of the at least one mounting member is positioned in the housing and a second position in which the grid mounting section extends beyond a top surface of the housing to provide a mechanical connection between the grid and the connector.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventor: Philip Clay BRANDBERG