Abstract: The invention relates to OLED devices (1) operational at high voltages providing a good life time performance, which can be manufactured with reduced effort and costs.

Abstract: A method of fabricating a high-density laser diode stack is disclosed. The laser diode bars each have an emitter surface and opposing surfaces on either side of the emitter surface. Each laser diode bar has metallization layers on the opposing surfaces and a solder layer on at least one of the metallization layers. The solder layer is applied to a semiconductor wafer prior to cleaving the wafer to create the laser diode bars. The laser diode bars are arranged in a stack such that the emitter surfaces of the bars are facing the same direction. The stack of laser diode bars is placed in a vacuum chamber. An anti-reflection coating is deposited on the emitter surfaces of the laser diode bars in the chamber. The laser diode bars are joined by applying a temperature sufficient to reflow the solder layers in the chamber.

Abstract: In accordance with certain embodiments, phosphor arrangements are formed via adhering phosphors to activated regions on a substrate and transferring them to a different substrate.

Abstract: A method for making light emitting diode includes following steps. A substrate is provided. A first semiconductor layer is grown on a surface of the substrate. A patterned mask layer is located on a surface of the first semiconductor layer, and the patterned mask layer includes a number of bar-shaped protruding structures, a slot is defined between each two adjacent protruding structures to expose a portion of the first semiconductor layer. The exposed first semiconductor layer is etched to form a protruding pair. A number of three-dimensional nano-structures are formed by removing the patterned mask layer. An active layer and a second semiconductor layers are grown on the number of three-dimensional nano-structures in that order. A first electrode is electrically connected with the first semiconductor layer. A second electrode is located to cover the entire surface of the second semiconductor layer which is away from the active layer.

Abstract: A method for making light emitting diode includes the following steps. A substrate is provided. A first semiconductor layer is grown on a surface of the substrate. A patterned mask layer is located on a surface of the first semiconductor layer, and the patterned mask layer includes a number of bar-shaped protruding structures, a slot is defined between each two adjacent protruding structures to expose a portion of the first semiconductor layer. The exposed first semiconductor layer is etched to form a protruding pair. A number of three-dimensional nano-structures are formed. An active layer and a second semiconductor layers are grown on the number of three-dimensional nano-structures in that order. The substrate is removed and a surface of the first semiconductor layer is exposed. A first electrode is applied to cover the exposed surface. A second electrode is electrically connected with the second semiconductor layer.

Abstract: A method for making light emitting diode is provided. The method includes following steps. A substrate is provided. A first semiconductor layer is grown on a surface of the substrate. A patterned mask layer is located on a surface of the first semiconductor layer, and the patterned mask layer includes a number of bar-shaped protruding structures, a slot is defined between each two adjacent protruding structures to expose a portion of the first semiconductor layer. The exposed first semiconductor layer is etched to form a protruding pair. A number of three-dimensional nano-structures are formed by removing the patterned mask layer. An active layer and a second semiconductor layers are grown on the number of three-dimensional nano-structures in that order. A first electrode is electrically connected with the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer.

Abstract: A method of manufacturing a light-emitting device including a light-emitting element which emits light with a predetermined wavelength and a wavelength conversion portion including a fluorescent substance which is excited by the light emitted from the light-emitting element to emit fluorescence with a wavelength different from the predetermined wavelength, includes the followings. First, spraying so as to apply a liquid mixture containing a layered silicate mineral and a translucent ceramic precursor on the light-emitting element from a nozzle is performed while the nozzle is moved relative to the light-emitting element. Subsequently, forming of the wavelength conversion portion by heating the sprayed and applied liquid mixture is performed.

Abstract: A light-emitting element includes a n-type silicon oxide film and a p-type silicon nitride film. The n-type silicon oxide film and the p-type silicon nitride film formed on the n-type silicon oxide film form a p-n junction. The n-type silicon oxide film includes a plurality of quantum dots composed of n-type Si while the p-type silicon nitride film includes a plurality of quantum dots composed of p-type Si. Light emission occurs from the boundary between the n-type silicon oxide film and the p-type silicon nitride film by injecting electrons from the n-type silicon oxide film side and holes from the p-type silicon nitride film side.

Abstract: In this embodiment, an interval distance between a deposition source holder 17 and an object on which deposition is performed (substrate 13) is reduced to 30 cm or less, preferably 20 cm or less, more preferably 5 to 15 cm, and a deposition source holder 17 is moved in an X direction or a Y direction in accordance with an insulator (also called a bank or a barrier) in deposition, and a shutter 15 is opened or closed to form a film. The present invention can cope with an increase in size of a deposition apparatus with a further increase in size of a substrate in the future.

Abstract: A light-emitter is configured so that at least a hole injection layer and a light-emitting layer are laminated between a first electrode and a second electrode, and the light-emitting layer is formed in an area defined by a bank. In the area defined by the bank, the hole injection layer is formed so as to have a recess in an upper surface thereof. An upper peripheral edge of the recess is covered with a part of the bank. The light-emitting layer is formed with respect to the recess formed in the hole injection layer by a laser transfer method.

Abstract: Methods and devices for fabricating tri-layer beams are provided. In particular, disclosed are methods and structures that can be used for fabricating multilayer structures through the deposition and patterning of at least an insulation layer, a first metal layer, a beam oxide layer, a second metal layer, and an insulation balance layer.

Abstract: A heat treatment method of the present invention includes mounting a plurality of semiconductor wafers upright on a treatment boat in parallel to each other, inserting the treatment boat in a space above an injector located in a tube to be oriented to plane surfaces of the semiconductor wafers in parallel to an extending direction of the tube, and heating the tube while continuously supplying source gas into the tube through openings of the injector.

Abstract: In one embodiment, a method of manufacturing a solar cell includes forming a first electrode over a substrate; forming a light-converting layer over the first electrode and patterning the light-converting layer to form a plurality of patterned light-converting layers that are spaced apart from each other; forming a transparent insulating layer over the first electrode including the patterned light-converting layers; and forming a second electrode over the transparent insulating layer.

Abstract: An embodiment of the invention discloses a manufacture method of a sensor comprising: preparing gate scanning lines on a substrate; depositing a gate insulating layer on the gate scanning lines; sequentially depositing a gate insulation thin film, an active layer thin film, an ohmic contact layer thin film, a first conducting layer thin film and a photoelectric conversion layer thin film, and after the depositing, processing a lamination structure of the thin films with a gray-tone mask plate to obtain switch devices and photoelectric sensing devices; and then sequentially preparing a first passivation layer, bias lines and a second passivation layer.

Abstract: A pixel of an image sensor, the pixel includes a floating diffusion node to sense photo-generated charge, a reset diode to reset the floating diffusion node in response to a reset signal, and a set diode to set the floating diffusion node.

Abstract: A photovoltaic cell can include a dopant in contact with a semiconductor layer.

Abstract: At least part of a dielectric layer is implanted to form implanted regions. The implanted regions affect the etch rate of the dielectric layer during the formation of the openings through the dielectric layer. Metal contacts may be formed within these openings. The dielectric layer, which may be SiO2 or other materials, may be part of a solar cell or other device.

Abstract: A method for forming a transparent conductive oxide (TCO) film for use in a TFPV solar device comprises the formation of a tin oxide film doped with between about 5 volume % and about 40 volume % antimony (ATO). Advantageously, the Sb concentration generally ranges from about 15 volume % to about 20 volume % and more advantageously, the Sb concentration is about 19 volume %. The ATO films exhibited almost no change in transmission characteristics between about 300 nm and about 1100 nm or resistivity after either a 15 hour exposure to water or an anneal in air for 8 minutes at 650 C, which indicated the excellent duarability. Control sample of Al doped zinc oxide (AZO) exhibited degradation of resistivity for both a 15 hour exposure to water and an anneal in air for 8 minutes at 650 C.

Abstract: Methods for increasing the power output of a TFPV solar panel using thin absorber layers comprise techniques for roughening and/or texturing the back contact layer. The techniques comprise roughening the substrate prior to the back contact deposition, embedding particles in sol-gel films formed on the substrate, and forming multicomponent, polycrystalline films that result in a roughened surface after a wet etch step, etc.

Abstract: A composition and method for forming a field effect transistor with a stable n-doped nano-component. The method includes forming a gate dielectric on a gate, forming a channel comprising a nano-component on the gate dielectric, forming a source over a first region of the nano-component, forming a drain over a second region of the nano-component to form a field effect transistor, and exposing a portion of a nano-component of a field effect transistor to dihydrotetraazapentacene to produce a stable n-doped nano-component, wherein dihydrotetraazapentacene is represented by the formula: wherein in the dihydrotetraazapentacene chemical structure, each of R1, R2, R3, and R4 can be hydrogen, an alkyl group of C1 to C16 carbons, an alkoxy group, an alkylthio group, a trialkylsilane group, a hydroxymethyl group, a carboxylic acid group or a carboxylic ester group.

Abstract: There is provided a method of forming an organic thin film, capable of forming a single-crystal organic thin film easily and rapidly while controlling a thickness and a size. After an organic solution is supplied to one surface (a solution accumulating region wide in width, and a solution constricting region narrow in width and connected thereto) of a film-formation substrate supported by a support controllable in temperature, a movable body controllable in temperature independently of the support is moved along a surface of the support while being kept in contact with the organic solution. The temperature of the support is set at a temperature positioned between a solubility curve and a super-solubility curve concerning the organic solution, and the temperature of the movable body is set at a temperature positioned on a side higher in temperature than the solubility curve.

Abstract: A method for manufacturing an oxide thin film transistor with leakage currents less than 10?14 angstrom includes the steps of forming an oxide semiconductor active layer by a deposition process. In the deposition process, an electric power is in a range from 1.5 kilowatts to 10 kilowatts. The oxide thin film transistor manufactured by the above methods has advantages of low leakage currents, high electron mobility, and excellent temperature stability. The present invention also provides a method for manufacturing a display device. The display quality of the display device can be improved.

Abstract: A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured.

Abstract: The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer.

Abstract: Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Abstract: A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.

Abstract: An adhesive film for a semiconductor may include about 60 wt % to about 80 wt % of a thermoplastic resin based on a total solid content of the adhesive film, a phenolic curing agent, and an amine curing agent, and the adhesive film may have a storage modulus of about 2 MPa or more and a reaction curing rate of about 50% or more when cured at 150° C. for 20 minutes.

Abstract: A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Abstract: A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.

Abstract: Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed.

Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Abstract: A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier.

Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.

Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

Abstract: Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract: A method of manufacturing a nitride semiconductor device including: forming a nitride semiconductor layer over a substrate wherein the nitride semiconductor layer has a 2DEG channel inside; forming a drain electrode in ohmic contact with the nitride semiconductor layer and a source electrode spaced apart from the drain electrode, in Schottky contact with the nitride semiconductor layer, wherein the source electrode has an ohmic pattern in ohmic contact with the nitride semiconductor layer inside; forming a dielectric layer on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and forming a gate electrode on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed on the dielectric layer over a drain-side edge portion of the source electrode.

Abstract: A catalyst film (2) is formed over a substrate (1). A graphene (3) is grown on the catalyst film (2). A gap through which a lower surface of the catalyst film (2) is exposed is formed. The catalyst film (2) is removed through the gap.

Abstract: A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

Abstract: A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

Abstract: In one aspect, a method of forming a polysilicon (poly-Si) layer and a method of manufacturing a thin film transistor (TFT) using the poly-Si layer is provided. In one aspect, the method of forming a polysilicon (poly-Si) layer includes forming an amorphous silicon (a-Si) layer on a substrate in a chamber; cleaning the chamber; removing fluorine (F) generated while cleaning the chamber; forming a metal catalyst layer for crystallization, on the a-Si layer; and crystallizing the a-Si layer into a poly-Si layer by performing a thermal processing operation.

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.

Abstract: A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a minute structure, and the second phase change material layer pattern may fully fill the minute structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material.

Abstract: An electric circuit chip includes: a substrate made of glass or a semiconductor; and a circuit which is disposed in an inside of the substrate, has a first end portion and a second end portion exposed at specific surfaces of the substrate, and includes a spiral inductor.

Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.

Abstract: In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.