Abstract: A heat exchange device includes a housing, an internal circulating fan, an external circulating fan and a heat exchange unit. The internal and external circulating fans and the heat exchange unit are disposed in the housing. The internal and external circulating fans are disposed at the same side relative to the heat exchange unit. A closed-type electronic apparatus including the heat exchange device is also disclosed.

Abstract: A cooling system including several air jet elements, a heat exchange assembly and a frame is provided. The cooling system is applied to a rack server configured to receive a plurality of electronic assemblies. The air jet elements receive a high-pressure air and convert the high-pressure air into a low-temperature air. The heat exchange assembly is disposed in the frame and is connected to the air jet elements so as to perform a heat exchange between the low-temperature air and a high-temperature air generated by the rack server so as to lower the temperature of the high-temperature air. The frame is applied to accommodate the heat exchange assembly.

Abstract: As applications of variable frequency drives (VFD) (50) continue to grow so do challenges to provide VFD (50) systems meeting application specific requirements. For multiple reasons to include safety standards and electromagnetic interference, reduced ground leakage current is desirable. Building high output voltage VFDs (50) using transistors rated at voltages lower than the VFD output voltage is desireable for economic reasons. The apparatus and method described herein meet these challenges and others, in part by placing an electrically insulating plate (cp176) having high thermal conductivity, a low dielectric constant, and high dielectric strength between the heat sink plate of a VFD power semiconductor module and a grounded cooling plate (80 TE).

Abstract: A semiconductor apparatus 10 includes a radiator 30 on which plural semiconductor modules 20 that include semiconductor elements 21 are mounted, the semiconductor apparatus 10 characterized by the radiator 30 including a first main surface 30B and a second main surface 30C configured to be located on the opposite side of the first main surface 30B. Semiconductor module mount-surfaces 30B1, 30B2, 30C1, 30C2 are arranged in the first main surface 30B and the second main surface 30C in a zigzag pattern in cross-sectional view; and the semiconductor modules 20 are mounted onto some or all of the semiconductor module mount-surfaces 30B1, 30B2, 30C1, 30C2.

Abstract: A desk-top storage solution for portable computing devices is formed as a storage tray. The storage tray has pockets sized to cradle individual portable computing devices. Each pocket includes a wire management system to enable an electrical connector to be provided within the pocket and secured relative to the pocket to enable the portable computing device to be quickly electrically connected to the storage tray. A USB hub is provided within the storage tray which interconnects with the electrical connectors and enables the portable computing devices to be charged while stored in the storage tray and also synchronized with an external computer while contained within the storage tray. The storage tray has a lid that is connected to the base by position control friction hinges which regulate the motion of the lid relative to the base during ascent/descent while the lid is moved between open and closed positions.

Abstract: An input/output module for a building automation system includes a mounting plate, a circuit board, and a cover. The mounting plate has at least two fastener receptacles (24-30) positioned to align with fastener receptacles of a standard electrical junction box (90). The mounting plate further includes at least two openings, each opening sized to receive one or more wires therethrough. The circuit board supports an interface circuit configured to communicate on a building network. The circuit board also includes device input terminals and device output terminals. The interface circuit is configured to provide an interface between the building network and devices connected to the input and output terminals. The circuit board is configured to be mounted to the mounting plate. The cover is sized to fit over the mounting plate and circuit board.

Abstract: Provided in some embodiment is a module locking device including a first member coupled to a computer chassis during use, a second member coupled to the first member via a hinge. The hinge enables the second member to move between a first position that inhibits removal of one or more modules from the computer chassis during use and a second position that facilitates removal of one or more modules from the computer chassis during use. The module locking device also includes a locking mechanism that selectively locks the second member in the first position to inhibit removal of one or more modules from the computer chassis during use.

Abstract: A bookmark memory stick includes a PC board, a flat, elongated insulative holder shell having a recessed accommodation portion accommodating the PC board and a retaining hole disposed near the top end thereof, a metal cover shell surrounding the insulative holder shell and a clip, which has a transverse locating base fitted into a locating notch at the top end of the insulative holder shell, a double-bevelled clamping plate obliquely downwardly extended from the front side of the transverse locating base toward the inside of the metal cover shell and stopped against a inverted T-plate of the insulative holder shell and then curved obliquely outwardly for clamping a sheet member on the inverted T-plate, a back plate extended from the back side of the transverse locating base and inserted into the inner top side of the metal cover shell, and a hook plate obliquely extended from the back plate and engaged into the retaining hole of the insulative holder shell.

Abstract: System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.

Abstract: A computer system includes a serial advanced technology attachment dual-in-line memory module (SATA DIMM) with a circuit board, a motherboard, and an indicating unit. An edge connector is set on a bottom edge of the circuit board to engage in a memory slot of the motherboard. A SATA connector is arranged on the circuit board and connected to a storage device interface of the motherboard. The indicating unit is connected to the motherboard for indicating the data transfer rates of the SATA DIMM module through two light emitting diodes.

Abstract: A mountable electronic circuit module which produces appropriate characteristics without a complicated structure can be a DC-DC converter including a baseboard made of a magnetic material. A helical electrode is provided in the baseboard so as to function as a smoothing inductor device. Capacitor devices in addition to a DC-DC converter IC are mounted on a main surface of the baseboard. A circuit electrode arranged to connect the circuit devices is provided to enable the circuit devices to function as the DC-DC converter. The DC-DC converter is mounted on a motherboard through external connection electrodes of the capacitor devices.

Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

Abstract: A first backplane for being electrically coupled to a second backplane, a system monitoring module, and at least one transducer monitoring module includes a system interface bus configured to be coupled to the system monitoring module and the second backplane. The intermediate backplane also includes at least one monitor interface bus configured to be coupled to the at least one transducer monitoring module and the second backplane and an intermediate backplane bus configured to be coupled to the at least one transducer monitoring module and the system monitoring module.

Abstract: The invention provides a shield cover adapted to cover at least a first electronic component mounted on a first surface of a circuit board. The first electronic component has a metal shell or has a ground/earth terminal on a lateral surface thereof. The shield cover has a contact portion being elastically contactable with a lateral surface of the metal shell or the ground/earth terminal of the first electronic component.

Abstract: An electronic device includes an EMI shielding board, two electronic components and a flat cable. The EMI shielding board includes a first side and a second side opposite to the first side. The two electronic components are arranged at the first side of the EMI shielding board. The flat cable is connected between the two electronic components. The EMI shielding board further includes a first through slot and a second through slot both configured therein. The flat cable passes through the EMI shielding board via the first and second through slots. A part of the flat cable is on the first side of the EMI shielding board, and the remaining part of the flat cable is on the second side of the EMI shielding board.

Abstract: Power supplies, power adapters, and related methods are disclosed. One example power supply includes an open loop DC to DC converter having an input for connecting to an input power source and an output for supplying a DC output voltage or current and an enable/disable circuit coupled to the open loop DC to DC converter. The enable/disable circuit is configured to enable and disable the open loop DC to DC converter as a function of the DC output voltage or current. One example method includes determining a DC output voltage or current from an open loop DC to DC converter and enabling and disabling the open loop DC to DC converter as a function of the determined DC output voltage or current.

Abstract: An embodiment of a multidirectional signal converter includes first and second converter nodes, a transformer, and first and second stages. The transformer includes first and second windings, and the first stage is coupled between the first converter node and the first winding of the transformer. The second stage includes a first node coupled to the second converter node, a second node coupled to a node of the second winding of the transformer, and a filter node, is operable as a boost converter while current is flowing out from the second converter node, and is operable as a buck converter while current is flowing out from the first converter node. For example, in an embodiment, such a multidirectional signal converter may be a bidirectional voltage converter that handles power transfer between two loads. Such a voltage converter may have improved conversion efficiency and a smaller size and lower component count as compared to a conventional multidirectional voltage converter.

Abstract: An open loop half-bridge power converter is provided for effective zero volt switching during all operating conditions, the converter including: an oscillating inverter circuit having a pair of switches coupled to a load circuit; an inverter drive circuit effective to provide driver signals to the inverter circuit; and a control circuit for providing control signals to the drive circuit. The control circuit is configured to increase a switching frequency of the switching devices in response to a predetermined condition such as startup or short circuit conditions. The inverter as a result continues to operate at a full duty cycle in response to the increased switching frequency, and zero volt switching is ensured throughout the duration of the predetermined condition.

Abstract: A feedback circuit for an isolated power converter includes an opto-coupler and a reversed polarity regulator. The opto-coupler provides a current related to an output voltage of the isolated power converter. When the isolated power converter enters light load, the output voltage rises and the reversed polarity regulator reduces the current to decrease the power consumption and thus improve the light load efficiency of the isolated power converter.

Abstract: The power supply apparatus for obtaining a direct current from an alternating voltage source includes a first DC/DC converter for outputting a first direct current and a second DC/DC converter for a second direct current lower than the first direct current from the first DC/DC converter, and the output voltage of the first DC/DC converter is changed to a lower direct current and the second DC/DC converter is driven in a continuously-conducting state.

Abstract: Disclosed is a high boost ratio DC converter, wherein the first and second switches are controlled by a control chip and the control chip controls the first and second switches in the following sequence: the first and second switches both conduct; the first switch conducts and the second switch is cut off; the first and second switches both conduct; the first switch is cut off and the second switch conducts thus making a first and second inductors and a first and second clamp capacitors charge to a first and second output capacitors. Then the first and second output capacitors discharge a load. Therefore, the load voltage output from the DC power supply will be boosted owing to the discharged load from the first and second output capacitors. The boost ratio is 4/(1?D).

Abstract: An AC/DC power converter has an AC input and a DC output, with an input rectifier circuit coupled to the AC input. The input rectifier circuit includes a passive half-bridge rectifier circuit functional to provide passive rectification of an AC input power sign and at least one current shaper circuit. The current shaper circuit includes an input inductor coupled between the AC input and a switch node in the input active rectifier circuit. The input current shaper circuit is functional to shape an AC input current signal associated with an AC input power signal to a substantially sinusoidal current signal. A bulk capacitor circuit is coupled to the input active rectifier circuit. A DC/AC converter circuit is coupled to the bulk capacitor circuit. A resonant circuit is coupled to the DC/AC converter circuit and an output rectifier circuit may be coupled between the resonant circuit and the DC output.

Abstract: An apparatus and method for controlling the delivery of a pre-determined amount of power from a DC source to an AC grid includes an inverter and an inverter controller. The inverter includes an input converter, an energy storage capacitor, and an output converter. The inverter controller includes an input converter controller and an output converter controller. The input converter controller includes feedforward controller configured to perform a calculation to determine a value for the duty cycle for the input converter such that: (1) the input converter delivers the pre-determined amount of power and (2) the magnitude of a ripple signal reflected into the input source is attenuated toward zero. The input converter controller may also include a quadrature corrector configured to determine the effectiveness of the calculation in attenuating the ripple and to adaptively alter the calculation to improve the effectiveness.

Abstract: Systems and methods of operating a voltage converter are provided. The converter includes an output inductor and an output capacitor coupled to a rectifier circuit. The converter also includes a clamp circuit having a clamping diode and a clamping capacitor coupled in series, with the serial combination in parallel with the output inductor. The clamp circuit can also include a recovery inductor coupled to the output capacitor, and a switch configured to selectively couple and decouple the recovery inductor in parallel with the clamping capacitor.

Abstract: Voltage source converter based on a chain-link cell topology including one or more phases, each of the phases having one or more series-connected chain-link cell modules connected to each other. The output voltage of the voltage source converter is controlled by control signals applied to the series-connected chain-link cell modules. In case of failure of a chain-link cell module, that module is controlled, by the control signals, such that zero output voltage is provided at its output voltage AC terminal.

Abstract: A power converter includes a DC/AC converter with input terminals and output terminals. A DC/DC converter includes input terminals for receiving a DC input voltage and output terminals for providing a DC output voltage. The output terminals are coupled to the input terminals of the DC/AC converter. The DC/DC converter also includes a control circuit that is configured to control an output current of the DC/DC converter dependent on a reference signal. The reference signal has a frequency that is dependent on a frequency of the AC output voltage.

Abstract: Disclosed is a power converter including a power factor corrector and a DC/DC converter and a power conversion method.

Abstract: The present invention is a single-phase voltage source DC-AC power converter and a three-phase voltage source DC-AC power converter.

Abstract: Control systems, methods and power conversion systems are presented for reducing common mode voltages in AC motor loads driven by inverter PWM control using switching sequences with only active vectors where a first vector of each switching sequence differs by one phase switching state from a last vector of a switching sequence of an adjacent sector, along with enhanced deadtime compensation and reflected wave reduction techniques in providing pulse width modulated switching signals to a switching inverter.

Abstract: A Converter (1a.1c) for single-phase and three-phase Operation which comprises a three-phase rectifier to which three coils (La, Lb, Lc) are connected on the mains side is described. A first coil (La) is provided on the mains side with a switch (S) which connects the first coil (La) to the mains during three-phase Operation and connects it via a capacitor (C) either to the lower end (FP) of the rectifier or on the mains side to another coil (Lb, Lc) during single-phase Operation. In addition, a d.c. voltage supply and a battery charger (5a.5c) which comprise the Converter (1a.1c) according to the invention are described.

Abstract: Technology leading to a size reduction in a power conversion apparatus comprising a cooling function and technology relating to enhancing productivity and enhancing reliability necessary for commercial production are provided. Series circuits comprising an upper arm and lower arm of an inverter circuit are built in a single semiconductor module 500. The semiconductor module has cooling metal on two sides. An upper arm semiconductor chip and lower arm semiconductor chip are wedged between the cooling metals. The semiconductor module is inserted inside a channel case main unit 214. A DC positive electrode terminal 532, a DC negative electrode terminal 572, and an alternating current terminal 582 of a semiconductor chip are disposed in the semiconductor module. The DC terminals 532 and 572 are electrically connected with a terminal of a capacitor module. The alternating current terminal 582 is electrically connected with a motor generator via an AC connector.

Abstract: A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.

Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

Abstract: A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.

Abstract: A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.

Abstract: A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.

Abstract: According to one embodiment, a resistance change type memory includes a memory cell and a capacitor which are provided on a semiconductor substrate. The memory cell includes a resistance change type memory and a select transistor. The resistance change type storage element changes in resistance value in accordance with data to be stored. The select transistor includes a first semiconductor region provided in the semiconductor substrate, and a gate electrode facing the side surface of the first semiconductor region via a gate insulating film. The capacitor includes a second semiconductor region provided in the semiconductor substrate, a capacitor electrode facing the side surface of the second semiconductor region, and a first capacitor insulating film provided between the second semiconductor region and the capacitor electrode.

Abstract: A two-dimensional array of switching devices comprises a plurality of crossbar tiles. Each crossbar tile has a plurality of row wire segments intersecting a plurality of column wire segments, and a plurality of switching devices each formed at an intersection of a row wire segment and a column wire segment. The array has a plurality of lateral latches disposed in a plane of the switching devices. Each lateral latch is linked to a first wire segment of a first crossbar tile and a second wire segment of a second crossbar tile opposing the first wire segment. The lateral latch is operable to close or open to form or break an electric connection between the first and second wire segments.

Abstract: A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein.

Abstract: A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.

Abstract: In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

Abstract: A high threshold five transistor SRAM bit cell with cross-coupled inverters has a single BIT line, a common logic 1 supply voltage, and two logic 0 virtual ground source voltages. The BIT line is coupled to the bit cell by a pass transistor. When BIT line and virtual ground lines are not otherwise being used, they are connected to a common standby voltage that substantially lowers bit cell standby leakage. Writing is performed by driving a data signal through the pass transistor and is facilitated by creating a voltage differential on the virtual ground lines. Reading is also performed through the pass transistor wherein the BIT line is initially at the standby voltage, and is then driven lower or higher depending upon the data value stored in the bit cell.

Abstract: A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.

Abstract: In a memory, the MTJ elements respectively have a first end electrically connected to any one of a source and a drain of one of the cell transistors. First bit lines each of which is electrically connected to the other one of the source and the drain of one of the cell transistors. Second bit lines each of which is electrically connected to a second end of one of the MTJ elements. Word lines each of which is electrically connected to a gate of one of the cell transistors or functions as a gate of one of the cell transistors. A plurality of the second bit lines correspond to one of the first bit lines. A plurality of the MTJ elements share the same word line and the same active area. The active area is continuously formed in an extending direction of the first and second bit lines.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: Method for writing and reading more than two data bits to a MRAM cell comprising a magnetic tunnel junction formed from a read magnetic layer having a read magnetization, and a storage layer comprising a first storage ferromagnetic layer having a first storage magnetization, a second storage ferromagnetic layer having a second storage magnetization; the method comprising: heating the magnetic tunnel junction above a high temperature threshold; and orienting the first storage magnetization at an angle with respect to the second storage magnetization such that the magnetic tunnel junction reaches a resistance state level determined by the orientation of the first storage magnetization relative to that of the read magnetization. The method allows for storing at least four distinct state levels in the MRAM cell using only one current line to generate a writing field.

Abstract: A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a second region thereof, the second region different from the first region.

Abstract: A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free region, a pinned region, and a heating region configured to generate and transfer heat to the free region when a programming current is directed to the cell. The heat transferred from the heating region increases the temperature of the free region, which decreases the magnetization and the critical switching current density of the free region. In some embodiments, the heating region may also provide a current path to the free region, and the magnetization of the free region may be switched according to the spin polarity of the programming current, programming the memory cell to a high resistance state or a low resistance state.

Abstract: Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.