Abstract: A fabricating method of grid points on light guiding plate, a fabricating method of light guiding plate, and a backlight module comprising the light guiding plate fabricated by the fabricating method of light guiding plate and a display device. The fabricating method of grid points on a light guiding plate comprises following steps of: forming a layer of photosensitive material on a mold for the light guiding plate (S1); and performing photolithography on the photosensitive material in order to form grid points on the light guiding plate (S2). Since the mold for the light guiding plate is not etched directly, the grid points on the light guiding plate can be made without damaging the surface of the mold for the light guiding plate, and the cost for polishing the mold surface is saved and the overall process is simplified.

Abstract: Windows, or other types of transparent materials, may be constructed to passively allow light from alternate sources to pass therethrough, while also being able to actively produce artificial light for providing illumination from one side of the window by means of an incorporated optical waveguide that accepts light from an edge of the window and disperses it from only one side of the window.

Abstract: A power adapter comprising a POE connector for receiving electrical power from the power lines of a POE cable, a transformer circuit and a USB connector for delivering electrical power to a USB powered device, wherein a POE cable provides power to the USB powered device. The power adapter can have a POE receptacle for receiving an Ethernet plug, to receive the POE power, and a USB receptacle to receive a USB plug from a USB powered device, or dedicated wires from one or more of the POE power supply and/or the USB powered device. Also, a method for providing USB power comprising the steps of running a POE cable from a power source to an adapter, adapting the POE power from the POE cable to USB power and making the USB power available to one or more USB powered devices.

Abstract: Power supplies and power controllers are disclosed. A disclosed power supply has a power controller, a power switch, an auxiliary winding, a first circuit and a second circuit. The power controller is a monolithic integrated circuit with a multi-function pin and a gate pin. A control node of the power switch is coupled to the gate pin. The first circuit is coupled between the multi-function pin and the auxiliary winding and has a diode. The second circuit is coupled between the multi-function pin and a ground line, and has a thermistor.

Abstract: Disclosed include power controllers and related control methods. A disclosed power controller has a pulse generator, a sample/hold device, a comparator, and a switch controller. The pulse generator provides an enable signal, defining an enable time. The comparator has two inputs capable of being coupled to a reference signal and a feedback signal, respectively, and an output coupled to a compensation capacitor. When enabled by the enable signal, the comparator charges/discharges the compensation capacitor. The switch controller controls a power switch according to a compensation voltage of the compensation capacitor. A feedback voltage of the feedback signal is able to correspond to an output voltage of the power supply.

Abstract: A DC-DC converter in which a primary side and a secondary side are insulated by a transformer, includes: two diodes having anodes respectively connected to both ends of a secondary winding of the transformer and cathodes connected to each other; a series circuit composed of a resistor and a capacitor connected in series; and a snubber circuit formed by connecting the cathodes of the diodes to the connection point between the resistor and the capacitor. Surge voltage caused on the secondary side of the transformer is clamped at the voltage of the capacitor, and surge energy stored in the capacitor is regenerated to a load via the resistor. Thus, surge voltage caused on the secondary side of the transformer is suppressed with a simple configuration, and effective use of surge energy is ensured.

Abstract: A method of controlling an LLC resonant converter includes programming a burst stop frequency and a burst start frequency in response to a maximum switching frequency of the LLC resonant converter. The burst stop frequency and the burst start frequency are fractions of the maximum switching frequency. The LLC resonant converter is switched in response to a feedback signal to regulate an output of the LLC resonant converter. The steps of switching the LLC resonant converter in a run state in response to the feedback signal reaching a value corresponding to the programmed burst start frequency, and stopping the switching of the LLC resonant converter in a stop state in response to the feedback signal reaching a value corresponding to the programmed burst stop frequency are repeated.

Abstract: In a switching power supply device with reduced size and increased power conversion efficiency, a secondary-side rectifier circuit includes an adder-rectifier circuit that stores a voltage generated in a secondary winding in a capacitor as electrostatic energy in an on period of one of a high-side and low-side switching circuits or, and adds the voltage in the capacitor and the voltage generated in the secondary winding and outputs the sum as a direct-current voltage during in an on period of the other of the high-side and low-side switching circuits. A switching control circuit adjusts an output power to be output from the secondary-side rectifier circuit, by using on-period ratio controller that controls a proportion of periods during which the respective high-side side and low-side switching elements are brought into a conductive state.

Abstract: A resonant power converter includes a resonance tank formed by a capacitance component and an inductance component, at least two switches connected to the resonance tank and a voltages source in a bridge configuration, a number of snubber capacitors connected in parallel to each of the switches, a controller configured to control ON and OFF timings of the at least two switches so as to excite the resonance tank, and a voltage sensor configured to sense a voltage drop across at least one of the switches. The controller is configured to switch the at least one of the switches to the ON state when the absolute value of the sensed voltage drop reaches a minimum.

Abstract: In a switching power supply device with reduced size and increased power conversion efficiency, a first resonant circuit including a series resonant inductor and a series resonant capacitor, and a second resonant circuit including a series resonant inductor and a series resonant capacitor, are caused to resonate with each other to cause sympathetic vibration of each resonant circuit, such that transmission is performed by utilizing both magnetic field coupling and electric field coupling between a primary winding and a secondary winding. Operation at a switching frequency higher than a specific resonant frequency of an overall multi-resonant circuit allows a ZVS operation to be performed, enabling a significant reduction in switching loss and high-efficiency operation.

Abstract: The present invention relates to control circuits and methods for a flyback converter and AC-DC power converters thereof. In one embodiment, a control circuit can include: (i) a turn-on signal generating circuit that is configured, in each switching cycle, to receive a drain-source voltage of a power switch of the flyback converter, and to activate a turn-on signal to turn on the power switch when the drain-source voltage reaches a valley value; (ii) a turn-off signal generating circuit that is configured, in each switching cycle, to activate a turn-off signal to turn off the power switch based on a power switch feedback error signal after a power switch conducting time interval has elapsed; and (iii) where input current and voltages of the flyback converter can be maintained as substantially in phase, and an output electrical signal of the flyback converter can be maintained as substantially constant.

Abstract: An isolated switching mode power supply, having: an input terminal; an output terminal; a transformer having a primary winding and a secondary winding; a primary power switch coupled to the primary winding; a secondary power switch coupled between the secondary winding and the output terminal of the power supply; a secondary controller configured to generate a frequency modulation signal based on the output voltage and the first feedback signal; a coupled device configured to provide a frequency control signal based on the output voltage and the frequency modulation signal; and a primary controller configured to provide a switching signal to control the primary power switch based on the current sense signal and the frequency control signal.

Abstract: A switching mode power supply, having: an input port; an output port; an energy storage component and a pair of power switches coupled between input port and the output port; an error amplifier configured to generate an amplified error signal based on the feedback signal and the reference signal; an error comparator configured to generate a frequency control signal based on the amplified error signal and the first sawtooth signal; a peak current generator configured to generate a peak current signal based on the frequency control signal; a peak current comparator configured to generate a current limit signal based on the peak current signal and the current sense signal; and a logic circuit configured to generate a switching signal to control the power switches based on the frequency control signal and the current limit signal.

Abstract: An isolated switching power supply apparatus includes a transformer, a primary-side circuit that includes at least a switching element and supplies input power from an input terminal to a primary winding by controlling on/off of the switching element, and a secondary-side circuit that is electrically isolated from the primary-side circuit and that outputs output power resulting from power conversion performed by the transformer from a secondary winding to an output terminal. The apparatus includes a first circuit board to which the primary winding is connected and that includes the primary-side circuit and the input terminal, and a second circuit board to which the secondary winding is connected and that includes the secondary-side circuit and the output terminal. The first and second circuit boards are stacked in a multilayer manner. The primary and secondary windings are arranged around a core that extends through the first and second circuit boards.

Abstract: A method to control a voltage source converter (CON1; CON2) in a HVDC system comprises the step of controlling a frequency and a voltage amplitude of an AC voltage (UV1; UV2) generated by the voltage source converter (CON1; CON2) independently of the conditions in an AC network (N1; N2) connected to the voltage source converter (CON1; CON2). This method is performed by a control unit of a HVDC system. In a special embodiment, the method forms the basis of a method to black start an AC network, where the AC network comprises transmission lines and is connected to at least two AC power stations, where one of the at least two AC power stations is connected via a HVDC system to the AC network.

Abstract: An embodiment multilevel inverter comprises a first boost apparatus having an input coupled to a positive dc bus and a second boost apparatus having an input coupled to a negative dc bus. The multilevel inverter further comprise a first switch coupled to an input of an L-C filter and the first boost apparatus, a second switch coupled to the input of the L-C filter and the second boost apparatus, a third switch coupled between the positive dc bus and the first switch and a fourth switch coupled between the negative dc bus and the second switch.

Abstract: A method for limiting an output power of an inverter having an output bridge and an upstream boost converter includes determining a first measurement variable representative of a bridge temperature and a second measurement variable representative of an output power of the inverter. The method also includes determining a third measurement variable representative of a generator voltage at generator connections of the inverter or a fourth measurement variable representative of an output voltage at a power output of the inverter, and reducing the output power supplied to a power supply grid to a reduced power value. The reduced power value is determined based on the first measurement variable, the second measurement variable and at least one of the third and fourth measurement variables.

Abstract: The present invention relates to a method of generating various alternating current waveforms, at power level. The AC mains power supply is rectified, processed by various circuits, controlled by a control unit and inverted as required at the output. This method may be employed with converter isolation from the mains. It is also possible to employ the system so that the input current is sinusoidal and the power factor of the converter is unity. The present invention produces preferably the sinusoidal output waveform with fundamental component at the desired frequency, where this waveform is produced employing a DC bus from which output voltage with the fundamental component at the desired shape and frequency is obtained using pulse width modulation techniques. The output stage is simply an inverter which inverts this waveform at zero-crossings of the rectified waveform to obtain an AC output.

Abstract: Provided is a switching power supply device capable of sufficiently removing ripple noise due to the switching frequency, the ripple noise being superimposed on an AC line, thereby stabilizing an output voltage. The switching power supply device includes: a switch including a first main terminal and a second main terminal, the first main terminal being connected to an inductor, the second main terminal being connected to a predetermined constant power supply unit, the switch being configured to connect or disconnect between the inductor and the constant power supply unit; and a control circuit configured to drive the switch at a predetermined switching frequency. The control circuit varies the switching frequency in accordance with a ratio of a connected time of the switch to a disconnected time of the switch.

Abstract: The present application provides a drive unit for a switching element, the driving unit having a function that is capable of promptly detecting the flow of excess current. The unit is usable for an electrical rotating machine. A drive unit for a switching element, comprising: a sense terminal output current detecting means for detecting an output current of a sense terminal that outputs a minute current having correlation with a current flowing between an input terminal and an output terminal of a switching element; a switching element drive control means for restricting the driving of the switching element when the output current detected by the sense terminal output current detecting means exceeds a predetermined threshold value; and a threshold changing means for changing the threshold value on the basis of a difference of electric potential between the input terminal and the output terminal of the switching element.

Abstract: A power source circuit includes a switching circuit 4 that converts a direct current voltage obtained by converting an alternating voltage from an alternating power source input through a pair of power supply lines 2 and 3 into a predetermined direct current voltage by a switching operation. A fuse 5 is provided on one power supply line 2. A series circuit 9 including a first line bypass capacitor 7 and a resistor element 8 is connected between one power supply line 2 and a ground 6. A second line bypass capacitor 10 is connected between the other power supply line 3 and the ground 6. Imbalance of the circuit by an excess current protection element is prevented to reduce common mode noise.

Abstract: A Graëtz-bridge converter-rectifier in which at least one rectifier arm situated between a single AC terminal and a single DC terminal includes multiple unidirectional electronic components connected in parallel and connected on one side to the DC terminal by means of a conductive component set and on the other side to the AC terminal. The invention is characterized in that the component set for at least one rectifier arm includes a plurality of separate component busbars each having at least one end connected to the DC terminal, the unidirectional components being divided between the component busbars into as many component sets connected in parallel as there are component busbars.

Abstract: In a preferred embodiment, a voltage inverter comprises a voltage converter circuit and a controller. The voltage inverter produces a time-varying output voltage from an input voltage, which can be a DC input voltage or an AC input voltage. The controller provides a control signal at a duty ratio determined dynamically by a set of signals. The set of signals include the time-varying output voltage, a predetermined output voltage, a gain factor and an inductor current in the voltage converter circuit. The predetermined output voltage can have an AC waveform or an arbitrary time-varying waveform. The voltage inverter operates to match the time-varying output voltage to the predetermined output voltage. Input-output linearization is used to design a buck inverter, and input-output linearization with leading edge modulation is used to design boost and buck-boost inverters under conditions where left half plane zero effects are present.

Abstract: A method and apparatus for power conversion. In one embodiment, the method comprises operating an inverter in bursts by (i) enabling power production by the inverter during a first plurality of periods, and (ii) disabling power production by the inverter during a second plurality of periods.

Abstract: A power conversion apparatus includes: a bridge circuit between AC and DC ends; a converter circuit between the bridge circuit and the DC end; and a control device for the converter circuit. The converter circuit includes: first and second switches in series between terminals of the bridge circuit; third and fourth switches in series between terminals of the DC end; and a reactor between an intermediate point of the first and second switches and an intermediate point of the third and fourth switches. The control device includes: a first controller defining a part of a cycle of an AC voltage as a stop period and stopping switching the first and second switches during the stop period; and a second controller performing voltage/power factor correction controls over an entire cycle by switching the third and/or fourth switches.

Abstract: The present invention provides a circuit of reducing electro-magnetic interference for a power converter. The circuit includes an oscillator, a switching voltage divider, and a sample-and-hold circuit. The oscillator has a terminal for receiving a modulation voltage. The modulation voltage is correlated with an input voltage obtained from an input of the power converter. The switching voltage divider is enabled and disabled by a switch to attenuate the input voltage into a sampled voltage in response to a sampling signal. The sample-and-hold circuit receives the sampled voltage to generate the modulation voltage. A switch of the sample-and-hold circuit controlled by a holding signal conducts the sampled voltage to a capacitor of the sample-and-hold circuit to generate the modulation voltage across the capacitor.

Abstract: A method for operating an electrical circuit is described. The electrical circuit is equipped with a power converter (10) that has at least one series connection (11, 12, 13) consisting of at least four power semiconductor elements. The electrical circuit is equipped with at least one capacitor (Cd1, Cd2) connected in parallel to the series connection (11, 12, 13). In the power converter (10), at least one resistor has been connected in parallel to the middle two power semiconductor elements. In the method, at least one of the power semiconductor elements is conductively connected and in this way a discharging current is generated from the capacitor (Cd1, Cd2) through the conductively connected power semiconductor element and the resistor.

Abstract: A method for reducing thermal cycling of a semiconductor power switch includes obtaining a value indicative of a junction temperature of the power switch. The method also includes selecting one of several pre-determined gate drive voltages, based on the obtained value, and providing the selected gate drive voltage to a gate of the power switch. This reduces thermal cycling of a power switch relative to the thermal cycling that would be present during operation at a single gate temperature.

Abstract: In one aspect, a method of converting power is described. One embodiment of the method comprises receiving direct current (DC) power; channeling the DC power through an inverter including a first bridge and a second bridge, wherein each of the first bridge and the second bridge includes at least one switch; controlling the at least one switch of the first bridge and the at least one switch of the second bridge to convert the DC power to alternating current (AC) power; and, channeling the AC power through an inductor that includes a first winding and a second winding, wherein the first winding is coupled to an output of the first bridge and the second winding is coupled to an output of the second bridge and wherein the inductor is configured to have a first magnetic path for common mode inductance and a second magnetic path for differential mode inductance.

Abstract: A power conversion apparatus according to an embodiment includes a cooling jacket. The cooling jacket includes a mounting face on which a power module including a power semiconductor device is mounted, a plurality of radiation fins that are arranged along a predetermined direction over the substantially whole area of the back side of the mounting face, and a boss that is placed along the predetermined direction in the central area of the substantially whole area of the back side.

Abstract: An electrical circuit, in particular a circuit used for generating electric power, wherein this circuit comprises a generator with n phases, a converter and a transformer to which a p-phase load can be connected. The converter comprises m partial converters, each of the partial converters is composed of p units and each of these units is provided with n/m switching circuits. The switching circuits of the individual units are connected symmetrical to the generator.

Abstract: A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.

Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

Abstract: To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored.

Abstract: A photonic quantum memory is provided. The photonic quantum memory includes entanglement basis conversion module configured to receive a first polarization-entangled photon pair and to produce a second entangled photon pair. The second polarization-entangled photon pair can he a time-bin entangled or a propagation direction-entangled photon pair. The photonic quantum memory further includes a photonic storage configured to receive the second entangled photon pair from the basis conversion module and to store the second entangled photon pair.

Abstract: Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.

Abstract: Example embodiments include a method for massive parallel stress testing of resistive type memories. The method can include, for example, disabling one or more internal analog voltage generators, configuring memory circuitry to use a common plane voltage (VCP) pad or external pin, connecting bit lines of the memory device to a constant current driver, which works in tandem with the VCP pad or external pin to perform massive parallel read or write operations. The inventive concepts include fast test setup and initialization of the memory array. The data can be retention tested or otherwise verified using similar massive parallel testing techniques. Embodiments also include a memory test system including a memory device having DFT circuitry configured to perform massive parallel stress testing, retention testing, functional testing, and test setup and initialization.

Abstract: Various embodiments comprise apparatuses having at least two resistance change memory (RCM) cells. In one embodiment, an apparatus includes at least two electrical contacts coupled to each of the RCM cells. A memory cell material is disposed between pairs of each of the electrical contacts coupled to each of the RCM cells. The memory cell material is capable of forming a conductive pathway between the electrical contacts with at least a portion of the memory cell material arranged to cross-couple a conductive pathway between select ones of the at least two electrical contacts electrically coupled to each of the at least two RCM cells. Additional apparatuses and methods are described.

Abstract: In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

Abstract: Hybrid resistive memory devices and methods of operating and manufacturing the same, include at least two resistive memory units. At least one of the at least two resistive memory units is a resistive memory unit configured to operate in a long-term plasticity state.

Abstract: A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second electrode is configured by a P type semiconductor. The control unit, when performing a setting operation of a memory cell, applies a voltage such that a current flows in a direction from the first electrode toward the second electrode.

Abstract: An erase method of a resistive random access memory which includes a plurality of cell strings, each having a plurality of memory cells and a string selection transistor, includes applying a first voltage to bit lines connected with string selection transistors of the plurality of cell strings, applying a turn-on voltage to at least one string selection line selected from string selection lines connected with the string selection transistors, applying a turn-off voltage to unselected string selection lines of the string selection lines, applying a second voltage to at least one word line selected from word lines connected with memory cells of the plurality of cell strings, and floating unselected word lines of the word lines.

Abstract: A non-volatile memory device includes a first electrode, a resistive switching material stack overlying the first electrode. The resistive switching material stack comprising a first resistive switching material and a second resistive switching material. The second resistive switching material overlies the first electrode and the first resistive switching material overlying the second resistive switching material. The first resistive switching material is characterized by a first switching voltage having a first amplitude. The second resistive switching material is characterized by a second switching voltage having a second amplitude no greater than the first switching voltage. A second electrode comprising at least a metal material physically and electrically in contact with the first resistive switching material overlies the first resistive switching material.

Abstract: Disclosed is a memory element, a stack, and to a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching.

Abstract: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.

Abstract: An apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a single-port memory device and control circuitry coupled between the first and second ports and the single port of the single-port memory device. The clock generator generates first and second clock signals having respective first and second clock rates, the clock rate of the second clock signal being an integer multiple of the clock rate of the first clock signal. The first and second memory drivers are configured to operate using the first clock signal at the first clock rate, and the single-port memory device is configured to operate using the second clock signal at the second clock rate.

Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected.

Abstract: Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin.

Abstract: An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

Abstract: A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.