Abstract: A light emitting device comprises a pair of electrodes and a mixed layer provided between the pair of electrodes. The mixed layer contains an organic compound which contains no nitrogen atoms, i.e., an organic compound which dose not have an arylamine skeleton, and a metal oxide. As the organic compound, an aromatic hydrocarbon having an anthracene skeleton is preferably used. As such an aromatic hydrocarbon, t-BuDNA, DPAnth, DPPA, DNA, DMNA, t-BuDBA, and the like are listed. As the metal oxide, molybdenum oxide, vanadium oxide, ruthenium oxide, rhenium oxide, and the like are preferably used. Further, the mixed layer preferably shows absorbance per 1 ?m of 1 or less or does not show a distinct absorption peak in a spectrum of 450 to 650 nm when an absorption spectrum is measured.

Abstract: A problem is to provide a transparent conductive laminate body that has a low surface resistivity and an organic thin film device using the laminate body, and the problem is solved by a transparent conductive laminate body having a transparent substrate having laminated directly on at least one surface thereof in this order a conductive metal pattern layer and a conductive organic layer having a conductive organic polymer compound, a material for forming the conductive metal pattern layer being at least one metal selected from gold, silver, copper and platinum, or an alloy having the metal, and an organic thin film device using the same.

Abstract: A method for fabricating an organic electroluminescence device according to the present invention includes: preparing an organic electroluminescence device having a lower electrode, an organic layer including an emitting layer, an upper electrode, and a shorted part in which the lower electrode and the upper electrode are shorted; and irradiating a part surrounding the shorted part in which the lower electrode and the upper electrode are shorted to alter a material composing the lower electrode or the upper electrode and to form a space between the lower electrode and the upper electrode in a region corresponding to a region surrounded by an altered part.

Abstract: An organic EL device includes: a first substrate having electrical conductivity; an organic layer formed on the first substrate; a second substrate having translucency; and an electrode layer formed on the second substrate. The electrode layer on the first substrate and the organic layer on the second substrate contact each other. The organic layer is not formed in the peripheral portion of the second substrate. In the region where the organic layer is not formed, a portion of the electrode layer is provided to extend, and the first substrate is not present to face the extended electrode layer, and the portion of the electrode layer is exposed to form an electrode portion. Thus, the electrode portion can be formed by a simple procedure in which, for example, the first substrate is removed, and the organic EL device can be efficiently manufactured.

Abstract: A surface light emitter according to an embodiment of the present invention, includes: a base material; a plurality of ribbon-shaped organic electroluminescent elements provided side by side on the base material; and a lenticular sheet that is attached to the base material and the ribbon-shaped organic electroluminescent elements through an adhesion layer, and that has a plurality of convex cylindrical lenses provided side by side. A direction in which the convex cylindrical lenses extend and a direction in which the ribbon-shaped organic electroluminescent elements extend are substantially parallel to each other.

Abstract: A composition for forming an insulating material used in electronic devices which includes, as a polymerizable component, a monomer comprising two or more (meth)acrylic moieties and a polycyclic alicyclic structure.

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract: The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.

Abstract: A thin film transistor structure is provided. The thin film transistor structure includes a first transistor having a first active layer, a second transistor having a second active layer, a first protection layer contacting the first active layer, and a second protection layer contacting the second active layer. The oxygen contents of the first and the second protection layers are controlled to affect the oxygen vacancy number of the first and the second active layers to satisfy the various electronic requirements of the first and the second transistors.

Abstract: In order to form a structure in which an oxide semiconductor layer through which a carrier flows is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which a carrier flows is away from the gate insulating film containing silicon is provided. Specifically, a buffer layer is provided between the gate insulating film and the oxide semiconductor layer. Both the oxide semiconductor layer and the buffer layer are formed using materials containing indium and another metal element. The composition of indium with respect to gallium contained in the oxide semiconductor layer is higher than the composition of indium with respect to gallium contained in the buffer layer. The buffer layer has a smaller thickness than the oxide semiconductor layer.

Abstract: To provide a novel light-emitting device that can be manufactured with high productivity. In a light-emitting device in which a light-emitting diode (LED) layer is provided over a substrate, a metal oxide semiconductor (c-axis aligned crystalline oxide semiconductor (CAAC-OS)) substrate including a crystal part having a c-axis which is substantially perpendicular to a surface of the substrate is used as the substrate. The substrate may have either a single-layer structure of a CAAC-OS substrate or a structure in which a thin CAAC-OS substrate is stacked over a base substrate.

Abstract: A transistor including an oxide semiconductor film, which has stable electric characteristics is provided. A transistor including an oxide semiconductor film, which has excellent on-state characteristics is also provided. A semiconductor device in which an oxide semiconductor film having low resistance is formed and the resistance of a channel region of the oxide semiconductor film is increased. Note that an oxide semiconductor film is subjected to a process for reducing the resistance to have low resistance. The process for reducing the resistance of the oxide semiconductor film may be a laser process or heat treatment at a temperature higher than or equal to 450° C. and lower than or equal to 740° C., for example. A process for increasing the resistance of the channel region of the oxide semiconductor film having low resistance may be performed by plasma oxidation or implantation of oxygen ions, for example.

Abstract: In a display portion of a liquid crystal display device, the dead space corresponding to a unit pixel is reduced while the aperture ratio of the unit pixel is increased. One amplifier circuit portion is shared by a plurality of unit pixels, so that the area of the amplifier circuit portion corresponding to the unit pixel is reduced and the aperture ratio of the unit pixel is increased. In addition, when the amplifier circuit portion is shared by a larger number of unit pixels, a photosensor circuit corresponding to the unit pixel can be prevented from increasing in area even with an increase in photosensitivity. Furthermore, an increase in the aperture ratio of the unit pixel results in a reduction in the power consumption of a backlight in a liquid crystal display device.

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer.

Abstract: A semiconductor device is provided which is used as a power device for a high-power application, includes an oxide semiconductor, and has high withstand voltage and high reliability. A semiconductor device for a high-power application with high productivity is also provided. In a crystal part included in an oxide semiconductor film having a crystalline structure, a c-axis is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film, triangular or hexagonal atomic arrangement which is seen from the direction perpendicular to the a-b plane is formed, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis.

Abstract: An oxide semiconductor sputtering target which is used for depositing a thin film having high electron mobility and high operational reliability, a method of manufacturing thin-film transistors (TFTs) using the same, and a TFT manufactured using the same. The oxide semiconductor sputtering target is used in a sputtering process for depositing an active layer on a TFT. The oxide semiconductor sputtering target is made of a material based on a composition including indium (In), tin (Sn), gallium (Ga) and oxygen (O). The method includes the step of depositing an active layer using the above-described oxide semiconductor sputtering target. The thin-film transistor may be used in a display device, such as a liquid crystal display (LCD) or an organic light-emitting display (OLED).

Abstract: A highly reliable semiconductor device that includes a transistor including an oxide semiconductor, which can display a high-definition image and can be manufactured with a high yield. The semiconductor device includes a pixel portion including a plurality of pixels, a gate signal line driver circuit portion, and a source signal line driver circuit portion including a first circuit that controls timing of sampling video signals and a second circuit that samples the video signals in accordance with the timing and then inputs the sampled video signals to the pixels. The second circuit includes a plurality of transistors in each of which an oxide semiconductor stacked layer is used as a channel formation region, the first circuit and the second circuit are electrically connected to each other by a wiring, and the wiring is electrically connected to gates of at least two transistors of the plurality of transistors.

Abstract: A method of fabricating a thin-film transistor, the method including: film-forming an active layer, that contains as a main component thereof an oxide semiconductor structured by O and at least two elements among In, Ga and Zn, in a film formation chamber into which at least oxygen is introduced, and b) heat treating the active layer at less than 300° C. in a dry atmosphere, wherein the film-forming a) and the heat treating are carried out such that, given that an oxygen partial pressure with respect to an entire pressure of an atmosphere within the film formation chamber in the film-forming is PO2depo (%), and an oxygen partial pressure with respect to an entire pressure of an atmosphere during the heat treating is PO2anneal (%), the oxygen partial pressure PO2anneal (%) at the time of the heat treating b) satisfies a relationship: ?20/3PO2depo+40/3?PO2anneal??800/43PO2depo+5900/43.

Abstract: A thin-film semiconductor device includes a gate electrode formed above a substrate; a gate insulating film formed to cover the gate electrode; a semiconductor layer formed above the gate insulating film and having a channel region; a channel protective layer formed above the semiconductor layer and containing an organic material which includes silicon, oxygen, and carbon; an interfacial layer which is formed in contact with the channel protective layer between the semiconductor layer and the channel protective layer, and which includes carbon as a major component, the carbon originating from the organic material; and a source electrode and a drain electrode which are electrically connected to the semiconductor layer.

Abstract: A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: A seed layer structure is annealed. The seed layer structure comprises a crystallization catalyst material on a seed semiconductor over a substrate. The seed semiconductor comprises an amorphous portion. Annealing of the seed layer structure converts the amorphous portion into a crystalline portion. The crystalline portion is connected to the substrate by subsurface crystal legs. The crystallization catalyst material formed underneath the crystalline portion by annealing is removed from the underneath of the crystalline portion.

Abstract: A semiconductor-to-metal interface with ohmic contact is provided. The interface includes a semiconductor material, a metal layer, and a silicon carbide layer disposed between the semiconductor material and the metal layer. The silicon carbide layer causes the formation of a semiconductor-to-metal interface with ohmic contact. Applications include forming a photovoltaic device with ohmic contact by disposing a layer of silicon carbide over the photovoltaic material before depositing a bottom electrode layer of metal to complete the bottom of a photovoltaic cell.

Abstract: A thin film transistor array panel includes: a semiconductor layer disposed on an insulation substrate; a gate electrode overlapping the semiconductor layer; a source electrode and a drain electrode overlapping the semiconductor layer; a first barrier layer disposed between the source electrode and the semiconductor layer; and a second barrier layer disposed between the drain electrode and the semiconductor layer, wherein the first barrier layer and the second barrier layer include nickel-chromium (NiCr).

Abstract: In a method of forming an active pattern, a gate metal layer is formed on a base substrate. The gate metal layer is patterned to form a gate line, and a gate pattern spaced apart from the gate line. A gate insulation layer is formed on the base substrate including the gate line and the gate pattern thereon, to form a first protruded boundary surface corresponding to an area including the gate pattern. An amorphous semiconductor layer is formed on the base substrate including the gate insulation layer thereon, to form a second protruded boundary surface corresponding to the first protruded boundary surface. The amorphous semiconductor layer is crystallized by illuminating a laser to the amorphous semiconductor layer on the second protruded boundary surface.

Abstract: An array substrate for a liquid crystal display (LCD) and manufacturing method thereof are provided. The array substrate for a liquid crystal display (LCD) includes: a substrate, including: a gate electrode, a pixel electrode, and a common electrode, a gate pad formed on the substrate, and connected to the gate electrode, a gate insulating layer formed on the gate pad, a first protective layer formed on the gate insulating layer, a second protective layer formed on the first protective layer, a first metal layer formed on the second protective layer, and connected to the gate pad through a first contact hole which exposes the gate pad, a third protective layer formed on the first metal layer and the second protective layer, and a second metal layer formed on the third protective layer, and connected to the first metal layer through a second contact hole which exposes the first metal layer.

Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

Abstract: The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), wherein the barrier layer includes an oxidized portion of the barrier layer, a gate dielectric disposed on the oxidized portion of the barrier layer, and a gate electrode disposed on the gate dielectric, wherein the oxidized portion of the barrier layer is disposed in a gate region between the gate electrode and the buffer layer.

Abstract: A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer.

Abstract: A semiconductor light emitting device is provided and includes a protective element including a first lower conductivity-type semiconductor layer and a second lower conductivity-type semiconductor layer. First and second lower electrodes are connected to the first lower conductivity-type semiconductor layer and the second lower conductivity-type semiconductor layer, respectively. A light emitting structure includes a first upper conductivity-type semiconductor layer, an active layer, and a second upper conductivity-type semiconductor layer sequentially formed on the protective element. First and second upper electrodes are connected to the first upper conductivity-type semiconductor layer and the second upper conductivity-type semiconductor layer, respectively.

Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.

Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.

Abstract: A semiconductor device includes a first semiconductor die including a normally-off transistor and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT. One of a source terminal and a drain terminal of the normally-off transistor is electrically coupled to a gate terminal of the normally-on GaN HEMT, and the other one of the source terminal and the drain terminal of the normally-off transistor is electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT. The second semiconductor die further includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells, and a voltage clamping element electrically coupled between the gate terminal and one of the source terminal and the drain terminal of the normally-on GaN HEMT.

Abstract: A groove structure formed on a surface of a substrate. The groove structure includes a lateral epitaxial pattern in a cross section perpendicular to the surface, which has: a first edge inclined to the surface; a second edge adjacent to first edge and parallel to the surface; a third edge parallel to the first edge, having a projection on the surface covering the second edge; and a fourth edge adjacent to the third edge. A first intersection between the second edge and the third edge on the second edge and an injection of a second intersection between the third edge and the fourth edge on the second edge are located on two sides of a third intersection between the first edge and the second edge, or the injection of the second intersection between the third edge and the fourth edge on the second edge coincides with the third intersection.

Abstract: A semiconductor structure having: a doped silicon carbide heat spreader; a semi-insulating silicon carbide layer disposed over the doped silicon carbide heat spreader; and a nitride (such as GaN, Indium nitride, Aluminum nitride) semiconductor layer disposed on the semi-insulating silicon carbide layer.

Abstract: Provided are an epitaxial silicon carbide single crystal substrate having a high-quality silicon carbide single crystal thin film with less stacking faults on a silicon carbide single crystal substrate and a production method therefor. The epitaxial silicon carbide single crystal substrate is produced by growing a silicon carbide epitaxial layer on a silicon carbide single crystal substrate having an off-angle of 4° or less so that the number of stacking faults emitting light at wavelengths ranging from 400 to 600 nm by photoluminescence on the substrate is less than 10/cm2 in total. Additionally, the method for producing the epitaxial silicon carbide single crystal substrate forms the epitaxial layer by using chlorosilane as a silicon-based material gas and hydrocarbon gas as a carbon-based gas, at a growth temperature of 1600° C. to 1700° C., at a C/Si ratio of 0.5 to 1.0, and at a growth rate of 1 to 3 ?m/hr.

Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.

Abstract: A heterogeneous stack structure is provided which includes one or more optical signal-based chips and multiple electrical signal-based chips. The optical chip(s) and the electrical chip(s) are different layers of the stack structure, and the optical chip(s) includes optical signal paths extending at least partially laterally within the optical chip(s). Electrical signal paths are provided extending between and coupling the optical chip(s) and the electrical chips. The electrical signal paths include one or more through substrate vias (TSVs) through one or more electrical chips of the multiple electrical chips in the stack structure. In one embodiment, the optical chip(s) is configured laterally to locally distribute, via one or more paths of the electrical signal paths, a timing reference signal for one or more electrical chips in the stack. Conversion between optical and electrical signals within the stack structure occurs within the optical chip(s).

Abstract: An LED luminaire has a dye-sensitized solar cell for converting light emitted from a light source to electric energy and uses the converted electric energy. Since the dye-sensitized solar cell plays a role of a diffusion plate, the LED luminaire may diffuse light and convert wasted light into power.

Abstract: A multichip package structure for generating a symmetrical and uniform light-blending source includes a substrate unit, a light-emitting unit and a package unit. The substrate unit includes a substrate body and at least one bridging conductive layer disposed on the top surface of the substrate body. The light-emitting unit includes at least two first light-emitting elements diagonally disposed on the substrate body and electrically connected to the substrate body and at least two second light-emitting elements diagonally disposed on the substrate body and electrically connected to the substrate body. The package unit includes at least two first light-transmitting package bodies respectively covering the at least two first light-emitting elements and at least two second light-transmitting package bodies respectively covering the at least two second light-emitting elements.

Abstract: A high voltage LED package includes a substrate and LED chips formed on a top surface of the substrate. A periphery of each LED chip is roughened. The LED chips are electrically connected in series.

Abstract: A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

Abstract: A display device in which light leakage in a monitor element portion is prevented without increasing the number of steps and cost is provided. The display device includes a monitor element for suppressing influence on a light-emitting element due to temperature change and change over time and a TFT for driving the monitor element, in which the TFT for driving the monitor element is provided so as not to overlap the monitor element. Furthermore, the display device includes a first light shielding film and a second light shielding film, in which the first light shielding film is provided so as to overlap a first electrode of the monitor element and the second light shielding film is electrically connect to the first light shielding film through a contact hole formed in an interlayer insulating film. The contact hole is formed so as to surround the outer edge of the first electrode of the monitor element.

Abstract: A lighting device includes a heat sink, through which air can flow transversely to its longitudinal extension and a plurality of semiconductor light sources, in particular light-emitting diodes, arranged on the heat sink, wherein at least two of the semiconductor light sources are aligned in different directions.

Abstract: LED light source having at least one light-emitting component. The light-emitting component is at least partly protected with a transparent protective material, which contains aliphatic thermoplastic polyurethane (TPU). A light-source band also includes at least one light-emitting component.

Abstract: An organic light emitting display device including a plurality of sub pixels, each of the sub pixels including an emissive layer between a pixel electrode and a counter electrode; and a partition wall defining regions of the plurality of sub pixels, wherein the partition wall is not located between at least one pair of adjacent sub pixels of the plurality of sub pixels.

Abstract: Disclosed is a light-emitting element comprising a plurality of light-emitting units which are separated from one another by a charge generation layer. The light-emitting units each have a light-emitting layer which is featured by a stack of two layers. Each of the two layers includes a host material and a phosphorescent material where the phosphorescent material in one of the two layers is blue emissive while the phosphorescent material in the other of the two layers exhibits a maximum emission peak in a range from 500 nm to 700 nm. The phosphorescent material exhibiting a maximum emission peak in a range from 500 nm to 700 nm may be different from light-emitting unit to light-emitting unit. An additive may be included in at least one of the two layers so that an exciplex is formed with the host material.

Abstract: An optoelectronic semiconductor device includes a first light source that emits green, white or white-green light and includes a semiconductor chip that emits in the blue spectral range, and a first conversion element attached directly to the semiconductor chip, a second light source that emits red light, having a semiconductor chip, that emits in a blue spectral range, and having a second conversion element attached directly to the semiconductor chip, and/or having a semiconductor chip that emits in a red spectral range, a third light source that emits blue light and has a semiconductor chip emitting in the blue spectral range, and a filler body having a matrix material into which a conversion agent is embedded, wherein the filler body is disposed downstream of the light sources collectively.

Abstract: Systems and methods for improved light emitting efficiency of a solid state transducer (SST), for example light emitting diodes (LED), are disclosed. One embodiment of an SST die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. The reflective material has a higher reflectivity than a base material of the connectors such that light traveling toward the connectors reflects back out of the device.