Abstract: An apparatus and a method for the contactless detection of vehicles via one or more magnetometers for measuring the geomagnetic field, in which at least one magnetometer includes a device for measuring the gravitational field.

Abstract: A nuclear magnetic flowmeter with a measuring tube, a signal apparatus for generating signals to excite a medium flowing through the tube and/or for evaluating signals of the excited medium, at least one signal coil located on the measuring tube for sending signals from the signal apparatus and/or for receiving signals of the excited medium and a matching device between the signal apparatus and the signal coil which has a reactive adjustment object a value of which can be rotationally adjusted mechanically and an adjusting apparatus which is assigned to the adjustment object. The adjustment apparatus has a rotary final control element which influences the adjustment object, a rotary actuator which acts on the rotary final control element, a torque clutch between the rotary actuator and the rotary final control element which transmits a torque generated by the rotary actuator to the rotary final control element, and a rotary stop.

Abstract: A local coil system for a magnetic resonance imaging system and a magnetic resonance imaging system include a local coil. The local coil includes a pressure element that may be filled with a fluid, and a controllable fluid supply device that at least at the imposition of the local coil to the object under examination and/or during the operation of the local coil, is coupled to the pressure element. The controllable fluid supply device is embodied such that the pressure of the pressure elements attained with the aid of the fluid, imposed on the object under examination may be changed, at least area by area.

Abstract: In a method for image data acquisition using a magnetic resonance system, in order to excite nuclear spin signals, a sequence of high-frequency pulses is irradiated into an examination subject while gradients are simultaneously switched for position encoding of the excited nuclear spin signals. The rise times of the gradients used during the sequence are adjusted dynamically with each high-frequency pulse irradiation.

Abstract: A system acquires MR image data of a portion of patient anatomy associated with spin lattice relaxation time in a rotating frame using an RF (Radio Frequency) signal generator and a magnetic field gradient generator. The RF (Radio Frequency) signal generator generates RF excitation pulses in anatomy and enables subsequent acquisition of associated RF echo data. The magnetic field gradient generator generates anatomical volume select magnetic field gradients for phase encoding and readout RF data acquisition in a three dimensional (3D) anatomical volume. The RF signal generator and the gradient generator use in order, a saturation pulse, a T1 spin lattice relaxation rotating frame preparation pulse sequence and a spoiler gradient, in acquiring image data of the 3D volume showing luminance contrast associated with T1 spin lattice relaxation in a rotating frame.

Abstract: A microwave resonator device (1), being configured in particular for electron spin resonance measurements, comprises a resonator being resonant with first and second microwave field modes and including first and second resonance sections (7, 8) arranged along a longitudinal axis (2) of the resonator, and a coupling unit being arranged between the first and second resonance sections, wherein the coupling unit includes a conducting plate (16) being arranged on the longitudinal axis (2) and covering a central portion of a cross-sectional area of the resonator, the conducting plate (16) is adapted to adjust a first mode frequency of the first microwave field mode, and the conducting plate (16) is arranged at a field minimum of the second microwave field mode. Furthermore, a method of conducting an electron spin resonance measurement with a sample to be investigated is described.

Abstract: In one embodiment, an electromagnetic shielding of a device is disclosed for a magnetic resonance system. The device is shielded via a conductive layer which surrounds an inner part of the device in such a manner that an electrical current path completely around the inner part can be formed in the layer. The layer is arranged between a housing of the device, surrounding the inner part, and the inner part. In another embodiment, an electromagnetic shielding of a device is disclosed for a magnetic resonance system, wherein the device is shielded via a conductive layer which surrounds the device in such a manner that an electrical current path completely around the device is formed. In this situation, the device having the layer is mounted by way of projections on the magnetic resonance system. Each projection has a contact surface with the layer, at which the respective projection contacts the layer.

Abstract: According to one embodiment, an MRI apparatus (20) obtains a nuclear magnetic resonance signal from an RF coil device (100) which detects the nuclear magnetic resonance signal emitted from an object (P), and this MRI apparatus (20) includes a first radio communication unit (200), a second radio communication unit (300) and an image reconstruction unit (56). The first radio communication unit (200) obtains the nuclear magnetic resonance signal detected by the RF coil device (100), and wirelessly transmits the nuclear magnetic resonance signal in a digitized state via an induced electric field. The second radio communication unit (300) receives the nuclear magnetic resonance signal wirelessly transmitted from the first radio communication unit (200) via the induced electric field. The image reconstruction unit (56) reconstructs image data of the object (P) based on the nuclear magnetic resonance signal received by the second radio communication unit (300).

Abstract: A method for producing at least one saddle coil for a gradient coil layer for a magnetic resonance tomography system is provided. At least one half cylinder-shaped, premolded saddle coil is arranged between an inner shell and an outer shell of a casting apparatus. The shells of the casting apparatus are closed, and the space between the shells is filled with a casting compound.

Abstract: In one embodiment, an MRI apparatus (20A and 20B) includes a first radio communication unit (200A to 200E), a second radio communication unit (300), an image reconstruction unit (56) and a table (34) for loading an object. The first radio communication unit obtains a nuclear magnetic resonance signal detected by an RF coil device (100), and wirelessly transmits the nuclear magnetic resonance signal in a digitized state via an induced electric field. The second radio communication unit receives the nuclear magnetic resonance signal via the induced electric field. The image reconstruction unit reconstructs image data based on the nuclear magnetic resonance signal. The table includes a supporting unit (500A to 500E) which detachably supports the first radio communication unit to the second radio communication unit so that an interval between the first and second radio communication units enables radio communication via the induced electric field.

Abstract: The present invention suggests an apparatus for detecting the operation status of a fluorescent light source. The apparatus comprises an antenna for receiving and sending electromagnetic waves. The apparatus further comprises a modulation frequency correlator and a signal generator for generating an indication signal. According to a second aspect the present invention proposes a method for detecting the operation status of a fluorescent light source. The method comprises the steps of: receiving an electromagnetic wave; detecting a modulation of the received electromagnetic wave; correlating the modulation frequency of the received electromagnetic wave with a predetermined frequency; generating an indication signal if a correlation between the modulation frequency and the predetermined frequency is detected.

Abstract: Feedback from a solenoid is achieved by adding at least one variable resistance in parallel with the solenoid current feedback circuit for position detection. The resistance has current flowing therethrough when a switching device actuated by the solenoid is in one position or transitions from one position to at least one other position. A feedback current may be measured in the current feedback circuit and the position of the switching device in response to actuation thereof by the solenoid may be determined from the measured feedback current.

Abstract: The present inventions, in one aspect, are directed to techniques and/or circuitry to determining data which is representative of the state of health, or a change therein, of the battery using the data which is representative of (i) the relaxation time of the battery and/or (ii) the overpotential of the battery. In another aspect the present inventions are directed to techniques and/or circuitry to adapt one or more characteristics of a charge signal using data which is representative of the state of health, or a change therein, of the battery. In yet another aspect the present inventions are directed to techniques and/or circuitry to determine a state of charge of the battery using data which is representative of the state of health, or a change therein, of the battery.

Abstract: A battery monitoring system includes a plurality of battery cells connected in series and including a first battery cell at a highest potential; a discharge circuit connected to a high potential side of the first battery cell through a first line; a circuit connected to the high potential side of the first battery cell through a second line; and a plurality of electro-static protection circuits each including one end portion connected to at least one of a high potential side and a low potential side of each of the battery cells, and another end portion connected to the first line.

Abstract: An electric leakage detecting apparatus, in an electric leakage detecting apparatus which is insulated from a chassis ground and detects electric leakages of a battery, is provided with: a voltage dividing circuit that divides an output voltage of the battery; an electric leakage determining circuit provided at a rear stage of the voltage dividing circuit, that determines the presence of an electric leakage based on a voltage detected by a circuit that respectively connects to a positive electrode side insulation resistance or a negative electrode side insulation resistance of the battery; and a dark current inhibit circuit in which a switch and a resistance are connected in parallel, that is inserted between at least either one of wiring that connects a positive terminal of the battery and the voltage dividing circuit, and wiring that connects a negative terminal of the battery and the voltage dividing circuit.

Abstract: An apparatus includes a voltage source, voltage measurement means and a processing means, and connects to a line to apply and monitor a voltage between the line and earth. The processing means controls the voltage source to transmit and receive communications from the line, via the voltage measurement means. The apparatus also has a first and second current measurement means. The voltage source is connectable to a wire under test to inject a predetermined test voltage on the wire. The wire extends in a first and second direction from the test location. The first current measurement means measures the leakage current from the voltage source flowing along the wire in a first direction, and the second current measurement means determines the leakage current along the wire in a second direction, and the processing means uses the current flows measured by both current measurement means to determine wire insulation properties.

Abstract: A reflectometer for allowing a test of a device, the reflectometer comprising: a source of pulsed radiation; a first photoconductive element configured to output a pulse in response to irradiation from said pulsed source; a second photoconductive element configured to receive a pulse; a transmission line arrangement configured to direct the pulse from the first photoconductive element to the device under test and to direct the pulse reflected from the device under test to the second photoconductive element; and a termination resistance provided for said transmission line configured to match the impedance of the transmission line.

Abstract: A measuring system for measuring signal characteristics on a node is disclosed. The measuring system includes a contact measuring unit including a probe for contacting the node to fetch a signal on the node, an output interface, a plurality of capacitors coupled between the probe and the output interface where a capacitance of each capacitor corresponds to a frequency range, and a protection circuit, of which one terminal coupled between the probe and the output interface and the other terminal coupled to a ground terminal, and a frequency analyzer coupled to the output interface for displaying information of amplitude vs. frequency of a signal outputted from the output interface to measure the signal characteristic on the node.

Abstract: Described herein is a method and apparatus for measuring the potential on a modern shielded high-voltage cable such as those used in medium-voltage distribution networks. A capacitive sensor arrangement (100) is constructed on a cable (110) using pre-existing structures (114, 116, 118, 120) within the cable (110). The use of implicit guarding methods is also described that allows the use of the semiconductor layer (116) present in modern cable design to be retained and to form part of the capacitive sensor arrangement (100). Performance of the sensor arrangement (100) can also be improved using temperature compensation techniques.

Abstract: A differential amplifier has an output and differential first and second inputs. A switch disposed between a sensor electrode and the second input is opened to initiate a reset phase where the sensor electrode and the differential amplifier are decoupled. A feedback capacitance disposed between the second input and the output is reset to a first level of charge. The switch is closed to initiate a measurement phase where the second input and sensor electrode are coupled. In the measurement phase: charge is balanced between the sensor electrode and the feedback capacitance such that a sensor electrode voltage equals a voltage of the first input equals a voltage of the second input, and the sensor electrode is charged; and the differential amplifier is utilized to integrate charge on the sensor electrode, such that an absolute capacitance corresponding to a coupling between the sensor electrode and an input object is measured.

Abstract: A method of using a sensor element includes: exposing a sensor element to an unknown analyte vapor; measuring a capacitance of the sensor element to obtain a measured capacitance; obtaining a true capacitance of the sensor element; exposing the semi-reflective conductive electrode to incident light and observing reflected light in order to measure a spectral change between the incident light and the reflected light; comparing the true capacitance and the measured spectral change, or at least one derivative thereof, to a reference library, the reference library comprising reference correlations between spectral change and true capacitance, or at least one derivative thereof, for a plurality of reference analyte vapors; and determining at least one of the chemical class or identity of the analyte vapor.

Abstract: A chip on glass substrate includes a substrate, first, second, and third pads that are arranged on the substrate and that are electrically connected to an IC device, and first to fourth conductive patterns. A first conductive pattern is arranged on the substrate, has one end electrically connected to the first pad, and has another end that is electrically floated. Second and third conductive patterns are arranged on the substrate, each have one end electrically connected to the second pad, and each have another end that is electrically floated. A fourth conductive pattern is arranged on the substrate, has one end electrically connected to the third pad, and has another end that is electrically floated.

Abstract: A readout apparatus and a driving method for sensor are provided. The readout apparatus includes an adjustable bias unit, a sensor unit, a signal converting unit, a checking unit and a control unit. The sensor unit senses physical energy and outputs a sensing result by using a bias voltage outputted from the adjustable bias unit. The control unit controls the adjustable bias unit according to the sensing result, so as to adjust the bias voltage. Therefore, the readout apparatus can reduce continuous power loss caused by long-term detection.

Abstract: A system and method for evaluating wafer test probe cards under real-world wafer test cell condition integrates wafer test cell components into the probe card inspection and analysis process. Disclosed embodiments may utilize existing and/or modified wafer test cell components such as, a head plate, a test head, a signal delivery system, and a manipulator to emulate wafer test cell dynamics during the probe card inspection and analysis process.

Abstract: A current sense system includes a current transformer having a primary coil and a secondary coil, wherein the secondary coil has a first and second terminal; a burden resistor connected between the first terminal of the secondary coil and ground; a monitor circuit that measures current in the primary coil by monitoring voltage across the burden resistor; and a built-in test (BIT) circuit connected to the second terminal of the secondary coil. The BIT circuit provides a virtual ground during normal operation, and either a positive voltage or a negative voltage during test operations.

Abstract: A test socket assembly, useful in association with a thermal control unit (TCU) used to maintain a set point temperature on an IC device under test, has alignment holes with bushings that are secured within the alignment holes by using retaining pins. The retaining pins can be easily screwed in and out of the socket. This provision allows the bushings to be replaced easily as they get worn out or deformed from repeated testing.

Abstract: Provided is a power cycle test apparatus that eliminates the need to measure a thermal resistance in a power cycle test and that pursues power saving in the evaluation of IGBT reliability by exactly applying a required thermal stress through the automatic adjustment of a stress current. The power cycle test apparatus performs a power cycle test for an IGBT to be tested by applying a thermal stress to the IGBT to be tested through the intermittent application of a stress current thereto. The apparatus applies the stress current to the IGBT to be tested and thereafter applies a current for measurement to the IGBT to be tested to measure a collector-emitter voltage of the IGBT to be tested. The apparatus further obtains a junction temperature of the IGBT to be tested from the measured collector-emitter voltage and a temperature coefficient of the IGBT to be tested.

Abstract: Provided are a power cycle test apparatus and a power cycle test method that can efficiently reproduce nearly a level of stress that may occur in failure mode in actual environments, the apparatus which is a test apparatus for performing a power cycle test for a power semiconductor device to be tested by applying a thermal stress to the power semiconductor device through the application of a stress current thereto in predefined ON/OFF cycles executes a thermal cycle test in temperature rise-fall cycles longer than the ON/OFF cycles by using an apparatus configured to change an external environmental temperature and further executes the power cycle test while executing the thermal cycle test in synchronization with execution phases of the thermal cycle test.

Abstract: An automatic aligning apparatus for aligning aligning components of a first object with aligning components of a second object includes first and second aligning mechanisms. The first aligning mechanism carries the first object and has a guiding groove. The second aligning mechanism has a carrying component that carries the second object, two rear holding plates, and two connecting components, each extending through a through hole in a corresponding rear holding plate and having two clamping parts that clamp a corresponding rear holding plate. The carrying component is movable between an initial position and an aligning position where a guiding stud of the carrying component extends into the guiding groove.

Abstract: A contact inspection device including contacts that contact with a test object for inspection, each contact having a base end portion, a needle tip portion having a needle tip that contacts with the test object, and an elastically deformable portion located between the base end portion and the needle tip portion, with the base end portion and the needle tip portion having axes which coincide with each other. The elastically deformable portion is deformable under a compressive force applied in the axial direction of the needle tip portion while the needle tip is pressed against the test object and converts the compressive force into a tilting motion of the needle tip portion about the needle tip through deformation. The needle tip portion is displaceable in a direction in which the needle tip portion is pivotally tilted while the needle tip is pressed against the test object.

Abstract: A storage device test system includes: a storage device mounting unit configured to mount a storage device therein; a test control unit configured to transmit and/or receive test signals to and/or from the storage device; an interface plug that is electrically connected to the test control unit and coupled to the storage device mounted in the storage device mounting unit; and a plugging driving unit that controls a relative location between the interface plug and the storage device mounting unit. By using the storage device test system, the causes of defects that may occur while using a storage device may be easily detected.

Abstract: Disclosed herein is a method for testing a semiconductor device, the method includes: preparing a first semiconductor chip having a first bump electrode and a first driver circuit that drives the first bump electrode, and a second semiconductor chip having a second bump electrode and a second driver circuit that drives the second bump electrode; staking the first and second semiconductor chips so that the first bump electrode and the second bump electrode are electrically connected to each other to form a current path including the first and second bump electrodes; and driving, in a test mode, the current path to a first potential by the first driver circuit while driving the current path to a second potential different from the first potential by the second driver circuit.

Abstract: An overcurrent detection circuit for a power switch comprises a sampling circuit and a comparing circuit. The sampling circuit is configured to perform current sampling on the power switch using a sampling Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and an amplifier, convert a sample current into a sample voltage and transmit the sample voltage to the comparing circuit, and clamp operating voltages of the comparing circuit and of an output circuit of the amplifier by a serially connected clamping MOSFET. The comparing circuit is configured to compare the sample voltage with a reference voltage and to output a result of overcurrent detection.

Abstract: It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The programmable logic regions may have input selection circuitry for selecting and providing input signals from the interconnects to the programmable logic regions. The programmable logic regions may include look-up table circuitry for processing the input signals and registers for storing output signals from the look-up table circuitry. The programmable logic regions may include output selection circuitry for selecting which output signals are provided to output circuitry of the programmable logic regions. The programmable logic regions may include bypass paths that provide direct access to the registers from the interconnects by bypassing the input and output selection circuitry.

Abstract: Nanoelectromechanical logic devices can include a plurality of flexible bridges having control and logic electrodes. Voltages applied to control electrodes can be used to control flexing of the bridges. The logic electrodes can provide logical functions of the applied voltages.

Abstract: An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.

Abstract: A method for generating a signal is provided, the method including: providing a first signal having a first signal frequency; providing a second signal having a second signal frequency or a third signal frequency, wherein the second signal frequency is higher than the third signal frequency; switching the second signal having the second signal frequency to the third signal frequency based on a predefined first signal event of the first signal; and returning the second signal having the third signal frequency to the second signal frequency in response to a predefined second signal event.

Abstract: A semiconductor device including a power-on-reset (POR) circuit. The semiconductor device includes a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope and a first POR signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time.

Abstract: A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency.

Abstract: Provided is an injection-locked-type frequency-locked oscillator capable of stable operation and exhibiting low phase noise. This injection-locked-type frequency-locked oscillator comprises: a locked loop (10) provided with a first injection-locked-type signal-controlled oscillator (14); and a second injection-locked-type signal-controlled oscillator (20). In the first injection-locked-type signal-controlled oscillator (14), an output frequency signal is made variable by an oscillation frequency control signal, and no reference clock signal is injected.

Abstract: A loop filter with noise cancellation includes first and second signal paths, an operational amplifier (op-amp), and a noise cancellation path. The first signal path provides a first transfer function (e.g., a lowpass response) for a first signal. The second signal path provides a second transfer function (e.g., an integration response) for a second signal. The second signal is a scaled version of, and smaller than, the first signal by a factor of alpha, where alpha is greater than one. A capacitor in the second signal path may be scaled smaller by a factor of alpha. The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal having op-amp noise. The noise cancellation path couples to the op-amp and provides a noise cancellation signal used to cancel the op-amp noise in the control signal.

Abstract: An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter.

Abstract: The DLL comprises a coarse delay line configured to have a plurality of unit delays and delay an reference dock to output a delayed clock, a fine delay line configured to delay the delayed clock to output a delayed output clock, a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock, a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate first to third phase detection signals based on a result of the comparison, a locking detection unit configured to output a locking signal by selecting a first locking detection signal or a second locking detection signal, and a control unit configured to control the coarse and fine delay lines in response to the locking signal and the first phase detection signal.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: A D flip-flop includes a first switch, a level shifter, and a second switch therein. The first switch includes a first input and a first output. The level shifter includes a second input coupled to the first input, and a second output. The second switch includes a third input coupled to the second output, and a third output. The first input and the third output form an input and an output of the D flip-flop.

Abstract: The present invention discloses a phase interpolating apparatus comprising: a first signal generation circuit, configured for generating a first signal having a first phase; an optional second signal generation circuit, configured for generating a second signal having the first phase; a third signal generation circuit, configured for generating a third signal having a second phase; a fourth/fifth signal generation circuit, configured for generating a fourth signal having a third phase when operating in a first mode and for generating a fifth signal having the second phase instead of the fourth signal when operating in a second mode; and a phase interpolator, configured for generating an interpolated signal without utilizing the fourth signal when operating in the first mode and for generating the interpolated signal according to the first signal, the third signal, and the fifth signal when operating in the second mode.