Abstract: In forming a frequency synthesizer by using PLL using processing of digital signals, an A/D converting unit is not required. By the integration of a digital value that depends on a set frequency, a saw-tooth wave serving as a phase signal is generated. A frequency signal output from a voltage-controlled oscillator is input via a frequency divider to an edge detecting unit, which then detects a rising edge or a falling edge of the frequency signal to generate a rectangular-wave signal that depends on a frequency of the frequency signal. Then, a latched circuit latches a value of the saw-tooth wave in response to the rectangular-wave signal, and this value is integrated in a loop filter and the resultant is used as a control voltage of the voltage-controlled oscillator.

Abstract: A control voltage generating circuit according to an aspect of the present invention includes: a reference voltage unit that includes a plurality of first transistors of the same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistor as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage.

Abstract: A frequency divider includes a phase selection circuit, control circuit and a retiming circuit. The phase selection circuit is arranged to receive a plurality of input signals with different phases, and generate an output signal by selectively outputting one of the input signals according to a plurality of retimed signals. The control circuit is arranged to receive the output signal to generate a plurality of control signals. The retiming circuit is arranged to retime the control signals to generate the retimed signals according to the input signals.

Abstract: The sawtooth wave generation circuit includes: a switch circuit configured to switch a connection state thereof between a first connection state, in which a current from a current source is flowed from a first terminal of the output capacitor to a second terminal of the output capacitor, and a second connection state, in which a current from the current source is flowed from the second terminal of the output capacitor to the first terminal of the output capacitor; a switch control circuit configured such that, in each connection state of the switch circuit, if an output voltage has reached a predetermined threshold which is set in relation to an intermediate voltage, the switch control circuit controls the switch circuit to switch the connection state to the other connection state at least during a part of a predetermined period thereafter.

Abstract: In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.

Abstract: A voltage change detection device is provided, which can reduce a deviation of a detection potential and can detect a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node.

Abstract: A semiconductor device includes a control voltage generating block configured to generate a control voltage corresponding to a phase difference between a reference clock signal and an internal clock signal, a control voltage restoring block configured to store the control voltage as a restoring voltage when entering into a low power mode and to supply the restoring voltage to a control voltage node when exiting from the low power mode, and an internal clock signal generating block configured to generate the internal clock signal corresponding to a voltage level of the control voltage.

Abstract: A pulse modulated neural integrator circuit is comprised of discrete analog electronic components and has a plurality of discrete stable states. In some embodiments, the pulse modulated neural integrator circuit is fabricated in whole or in part on an integrated circuit substrate using analog VLSI techniques. A phase locked loop circuit can use the pulse modulated neural integrator circuit in place of some conventional phase locked loop circuits.

Abstract: In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal.

Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

Abstract: A PWM-signal-output circuit includes a first output unit to output a PWM signal with a first duty cycle, in a first period in which a motor starts rotating, a second output unit to output the PWM signal whose duty cycle increases toward a second duty cycle and decreases from the second duty cycle in a period from a logic level change in speed signal until its subsequent logic level change, in a second period following the first, the speed signal having a period corresponding to a motor-rotation speed and a logic level changing alternately, and a third output unit to output the PWM signal whose duty cycle increases toward that of the input signal and thereafter decreases from that of the input signal in a period from a logic level change in the speed signal until its subsequent logic level change, after the second period elapses.

Abstract: A counter circuit includes two pairs of registers configured to swap contents based on a timer overflow or underflow condition. The counter circuit also includes a waveform generator that generates a composite pulse width modulated signal with a period and duty cycle specified by values stored in the registers. A demultiplexing circuit generates first and second signals from the composite signal.

Abstract: The present invention discloses a reset circuit that has a reset IC 12 having a terminal 2 connected to a reset terminal of the microcomputer 30 that is driven by a constant voltage (3.3V) generated by regulating a rectified voltage (V+) by a regulator 24, and a terminal 4 that inputs the constant voltage (3.3V) thorough a register R1, and outputs a reset signal to the microcomputer 30 when an input voltage input to the terminal 4 is lower than a first threshold value; and a transistor Q1 in which a collector is connected to the terminal 4 through a resistor 2 and an emitter is connected to the ground and the transistor is turned on when an output voltage of the switching transformer 21 is lower than a predetermined level, wherein the voltage lower than the first threshold value is input to the terminal 4 when the transistor Q1 is turned on.

Abstract: One embodiment provides a system for generating a reference waveform. The system can include a first pulse-width modulation (PWM) channel configured to provide a first PWM waveform having a first duty cycle and a first frequency. A second PWM channel is configured to provide a second PWM waveform having a second duty cycle and the first frequency. Combinational logic is configured to combine the first PWM waveform and the second PWM waveform to generate a phase-shifted reference PWM waveform having the first frequency and a phase shift that is based on the first duty cycle and the second duty cycle.

Abstract: A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies.

Abstract: Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure.

Abstract: The present invention provides a clamp circuit including, a switching section including first and second switching elements connected parallel between a current supply source and a clamp capacitor; a first control section that controls the first switching element to connect the current supply source and the clamp capacitor, when the voltage of an input signal input through the clamp capacitor is lower than a first reference voltage; and a second control section that stores voltage information based on the input signal when the voltage of the input signal is lower than a second reference voltage, and that controls the second switching element to connect the current supply source and the clamp capacitor for a period predetermined based on the voltage information, when the input signal is equal to or higher than the first reference voltage.

Abstract: A current mirror modified level shifter includes a pair of PMOS including a PMOS (MPL) and a PMOS (MPR), wherein a Vot node connected to a drain of the PMOS (MPR); a pair of NMOS including NMOS (MNL) and a NMOS (MNR), wherein sources of the PMOS (MPL) and the PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of the PMOS (MPL) and the PMOS (MPR) coupled together through a Vm node which located between the gates of the PMOS (MPL) and the PMOS (MPR); and a suspended PMOS (MPM) coupled to drain of the PMOS (MPL), the Vm node being coupled to a Va node between drain of the suspend PMOS (MPM) and drain of the NMOS (MNL).

Abstract: A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.

Abstract: A level shifter for converting an input pulse signal of low-voltage amplitude to high-voltage amplitude includes a low voltage circuit configured to generate complementary-pulse signals of low-voltage amplitude from the input pulse signal, and a high voltage circuit configured to generate a pulse signal of high-voltage amplitude based on the complementary-pulse signals. The low voltage circuit, including high-threshold voltage transistors, includes a plurality of inverter circuits connected in cascade and at least one resistive-switch circuit connected between an input and an output of at least one of the plurality of inverter circuits configured to operate as a resistor when in a conductive state.

Abstract: A switch circuit includes: first, second, and third input-output terminals; a first switching element connected between the first and second input-output terminals; a second switching element connected between the third input-output terminal and a grounding point; a third switching element connected between the first and third input-output terminals; a fourth switching element connected between the second input-output terminal and the grounding point; a first control voltage applying terminal connected to control terminals of the first and second switching elements; a second control voltage applying terminal connected to control terminals of the third and fourth switching elements; first and second resistors connected between the control terminals of the first and second switching elements and the first control voltage applying terminal, respectively; and first and second diodes connected in parallel with the first and second resistors, respectively, and having cathodes connected to the first control voltage

Abstract: A circuit includes a high-side switch, a low-side switch, a diode, a transformer having a primary winding and a secondary windowing, and an input connected to a first terminal of the primary winding. The high-side switch has a source, a gate connected to a drive source and a drain connected to a second terminal of the primary winding. The low-side switch has a source connected to ground, a gate connected to a drive source and a drain connected to the source of the high-side switch. The diode is connected between the gate of the high-side switch and the first terminal of the primary winding. The diode forms a current loop with the primary winding and the high-side switch to circulate current when low side switch is off until the high side switch turns off.

Abstract: A charge pump driver circuit has a first charge switch that couples a first node of a flying capacitor to a first power supply node, and a second charge switch that couples a second node of the capacitor to a second power supply node. Control circuitry is coupled to open the second charge switch and discharge the second node of the capacitor, in response to a control signal. Other embodiments are also described and claimed.

Abstract: A voltage doubler and an oscillating control signal generator controlling a charge pump (powered by a first voltage to provide a second voltage) of the voltage doubler are disclosed. The oscillating control signal generator includes a first input terminal receiving a fundamental oscillation signal, a second input terminal receiving a comparison result showing whether the second voltage is greater than a target value, a third input terminal operative to obtain an electric current consumption status at an output terminal of the charge pump, and an output terminal outputting an oscillating control signal for the control of the charge pump. Further, the oscillating control signal generator includes a logic circuit. The logic circuit generates the oscillating control signal by selectively blocking status changes of the fundamental oscillation signal according to the comparison result and the electric current consumption status.

Abstract: A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V1<VR1, the microcomputer turns off the first switch, and turns on/off the second switch to gradually increase a voltage V3 of the power supply node. Thus, the operation of a clock generation circuit driven by V3 can be stable even when V3 is changed from V1 to V2.

Abstract: The device for generating a reference current proportional to absolute temperature comprises processing means connected to the terminals of a core and designed to equalize the voltages across the terminals of the core, the core being designed to then be traversed by an internal current proportional to absolute temperature, and an output module designed to deliver to an output terminal the said reference current on the basis of the said internal current; the processing means comprise a self-biased amplifier possessing at least one first stage arranged according to a folded setup and comprising first PMOS transistors arranged in a setup of the common-gate type, and a feedback stage whose input is connected to the output of the amplifier and whose output is connected to the input of the first stage as well as to at least one terminal of the core.

Abstract: The invention is based on the fact that the current output from a DDB controlled amplifier in backoff, i.e. for low amplitudes, is reduced more or less linearly with the amplitude of the signal to be amplified. Therefore, it is enough to use smaller amplifiers which are able to output the necessary RF current. Hence, according to the present invention, the total DDB amplifier is divided into smaller parts that are coupled to the output only when needed.

Abstract: The present invention relates to an amplifier circuit where a load modulation is applied to a segmented amplifier. This will reduce the shunt loss since the loss of a segmented amplifier is reduced by allowing each amplifier segment or combination of segments to operate to their full output power capacity, rather than limited to a lower output power which results in a higher shunt loss. Hence, operation to full capacity before adding more segments is made possible by dynamically modulating the load.

Abstract: A high-frequency signal amplifier includes an amplifier having an input terminal and an output terminal, and amplifying a high-frequency signal; a signal line connected between the output terminal of the amplifier and an antenna; coupled lines arranged in parallel and coupled to the signal line and having different line lengths or differently terminated ends; and phase shifters shifting phase of high-frequency signals applied via the signal line and the coupled lines, supplying the high-frequency signals to the input terminal of the amplifier, and having different amounts of phase change.

Abstract: A Doherty amplifier having a main amplifier branch and one or more peak amplifier branches, where the functionality and structure of the cascade of the main output matching network, the main offset line, and the quarter-wave transformer of the main amplifier branch of a conventional Doherty amplifier are subsumed into the main output matching network of the main amplifier branch, and the functionality and structure of each cascade of the peak output matching network and the peak offset line of each peak amplifier branch of a conventional Doherty amplifier are subsumed into the peak output matching network of the corresponding peak amplifier branch. Furthermore, the output quarter-wave transformer can be replaced by a wideband node matching network that does not have to perform frequency inversion.

Abstract: A system and method of calibrating an amplifier are presented. The amplifier has a first amplification path and a second amplification path. An attenuation of the first amplification path is set to a first attenuation value and an attenuation of the second amplification path is set to the first attenuation value. A first phase shift of the first amplification path and a second phase shift of the second amplification path that meets a first performance criteria is determined. A phase shift of the first amplification path is set to the first phase shift and a phase shift of the second amplification path is set to the second phase shift. A first attenuation of the first amplification path and a second attenuation of the second amplification path that meets a second performance criteria is determined.

Abstract: Embodiments of power amplification devices are described that include a power amplification circuit, a first voltage regulation circuit, and a second voltage regulation circuit. The voltage regulation circuits are configured to provide regulated voltages to the power amplification circuit. The power amplification device also includes a threshold detection circuit to get better maximum output power performance while preserving power efficiency. The threshold detection circuit is configured to increase a voltage adjustment gain of the first voltage regulation circuit when a regulated voltage level of regulated voltage from the second voltage regulation circuit reaches a threshold voltage level. In this manner, the voltage adjustment gain can be increased when the second voltage regulation circuit is close to or has railed.

Abstract: Systematic IM2 calibration for a differential LNA is disclosed. In an aspect, an apparatus includes an amplifier configured to output an amplified signal having a level of systematic pre-mixer IM2 distortion, a detector configured to detect the level of the systematic pre-mixer IM2 distortion in the amplified signal, and a bias signal generator configured to generate at least one bias signal configured to adjust the amplifier to reduce the level of the systematic pre-mixer IM2 distortion.

Abstract: An output circuit includes a differential input stage, an output amplifier stage, a current control circuit; an input terminal, an output terminal.

Abstract: A push-pull amplifier is provided for amplifying an input signal, having first and second amplifier elements. Each of the amplifier elements has a current-emitting electrode, a current-collecting electrode, and a current-controlling electrode. The input signal is supplied to the current-controlling electrodes of the amplifier elements via a respective input connection and a respective input inductor arranged between the respective input connection and the respective current-controlling electrode. The current-collecting electrodes are connected via a respective supply inductor having a common supply voltage. The current-emitting electrode of each amplifier element is connected to the current-collecting electrode of the other amplifier element via a respective capacitor. The current-emitting electrodes are connected to output connections on which the output signal can be picked up, and to a reference potential via a respective output inductor.

Abstract: A circuit has a reference source (12) for supplying a bias signal to set a small signal transconductance of an amplifier transistor in an amplifier (10) to a predetermined value. The reference source has at least one reference transistor (120a-b, 30). A feedback circuit (128, 129, 38) has an input coupled to the main current channel of the reference transistor or reference transistors (120a-b, 30) and an output coupled to the control electrode of the reference transistor or reference transistors (120a-b, 30). The feedback circuit controls a control voltage at the control electrode, so as to equalize an offset current and a difference between main currents flowing through the current channel of the reference transistor or reference transistors (120a-b, 30), obtained with and without a small voltage offset added to the control voltage.

Abstract: A class-AB power amplifier according to the present embodiment includes an amplifying element whose power supply voltage is expressed as Vdc and whose maximum current is expressed as Imax, a conduction angle ?o of the amplifying element being more than ?(rad) and less than 2·?(rad), and load impedance of a fundamental wave being expressed as Z1=R1+j·X1, load impedance of a 2nd harmonic being expressed as Z2=R2+j·X2, and load impedance of a 3rd harmonic being expressed as Z3=R3+j?X3 which are observed from a dependent current source of an equivalent circuit of the amplifying element, and a relationship between variables X1 and R1 is set to ?0.5·R1<=X1<=0.5·R1, variable R1 is set to R1=Vdc/Imax·{1?cos(?o/2)}·?/{?o/2?sin(?o)/2}, variable X2/X1 is set to X2/X1=?2·{?o?sin(?o)}/{sin(?o/2)?sin(1.5·?o)/3}, and variable X3/X1 is set to X3/X1={?o?sin(?o)}/{sin(?o)/3?sin(2·?o)/6}, or each of the variables is set thereto so as to become equal substantially.

Abstract: A thermoelectric device transfers heat away from or toward an object using the Peltier effect. In some embodiments, the length of at least one thermoelectric element is at least ten times greater than a combined average cross-sectional dimension, orthogonal to the length, of two thermoelectric elements.

Abstract: An embodiment of a crystal oscillator circuit includes leakage-current compensation, transconductance enhancement, or both leakage-current compensation and transconductance enhancement. Such an oscillator circuit may draw a reduced operating current relative to a conventional oscillator circuit, and thus may be suitable for battery or other low-power applications.

Abstract: A piezoelectric vibrator, an oscillator, an electronic device and a ratio timepiece are provided which are capable of increasing a capacitance C0 while achieving miniaturization and cost reduction. The piezoelectric vibrator includes a base substrate, a lid substrate, a piezoelectric vibrating reed on which an excitation electrode is formed, and external electrodes. An electrode pattern for capacitance adjustment, which extends along a routing electrode, is provided extending from a routing electrode.

Abstract: There is provided an oscillator using a high-frequency crystal resonator which can satisfy the drive level needed for the crystal resonator and expand a variable frequency range. An oscillator having an oscillation circuit CC for oscillating the resonator SS is provided with a limiter circuit LM1 as a load of the resonator SS which is inductive and is a load circuit for limiting an oscillation amplitude. According to this configuration, the action of the limiter circuit LM1 allows satisfaction of the drive level needed for the crystal resonator and expansion of the variable frequency range.

Abstract: An oscillator and a control circuit thereof are provided. The control circuit is configured to control an oscillator to adjust the amplitude and the level of an oscillation signal. The control circuit includes a peak amplitude detector, an average voltage detector, and an oscillation controller. The peak amplitude detector is configured to detect the amplitude of the oscillation signal, so as to generate an amplitude value. The average voltage detector is configured to detect the direct current (DC) level of the oscillation signal, so as to generate an average value. The oscillation controller is configured to generate two power signals according to the amplitude value and the average value. The two power signals are provided to the oscillator, so that the oscillator adjusts the amplitude and DC level of the oscillation signal.

Abstract: Provided is a transmission circuit that operates highly efficiently by avoiding deterioration of the linearity of an output signal and suppressing occurrence of distortion of the output signal, when using the envelope tracking method. In this transmission circuit, offset control section (160) sets voltage that makes the corrected envelope signal level equal to or higher than the delayed envelope signal level, as offset voltage. By this means, the corrected envelope signal level becomes equal to or higher than the delayed envelope signal level, so that it is possible to prevent the power supply voltage from being lower than the optimal power supply voltage, making it possible to prevent the linearity of an output signal from deteriorating in power amplifier (130).

Abstract: A passive amplifier for use with enhanced power supplies, signal preamplifiers and power amplifiers in communications systems particularly in mobile phones, laptop computers and other battery-powered and battery-limited devices. The passive amplifier can be used as an attachment to electric appliances or other power consuming equipment to significantly reduce the electric power requirements of such equipment. These passive amplifiers do not require an outside source of power and can be used to elevate battery power outputs and serve as either low noise signal preamplifiers or transmit power amplifiers for higher performance and extended battery life. Passive amplifier technology is either electromagnetic or dielectric in nature with component parts limited to inductive, capacitive and resistive components. Dielectric amplifier prototypes have gain values in the range of the 10 dB level so as to be useful in communications applications and power amplification.

Abstract: A thin film balun of the present invention comprises: an unbalanced transmission line UL including a first line portion L1 and a second line portion L2; a balanced transmission line BL including a third line portion L3 and a fourth line portion L4 that are positioned facing the first line portion L1 and the second line portion L2 and electromagnetically coupled to the first line portion L1 and the second line portion L2, respectively; an unbalanced terminal UT connected to an end of the first line portion L1; a first balanced terminal BT1 connected to the third line portion L3; a second balanced terminal BT2 connected to the fourth line portion L4; and a ground terminal G connected to the third line portion L3 and the fourth line portion L4, wherein the ground terminal G has an extension that extends from the ground terminal G to an area at the unbalanced terminal UT side.

Abstract: Provided is a high voltage wideband pulse attenuator having an attenuation value self-correction function. The high voltage wideband pulse attenuator includes an input unit for receiving a pulse signal, a T-shaped attenuator circuit for attenuating the pulse signal, an output unit for outputting the pulse signal attenuated by the attenuator circuit, and a capacitive divider circuit for dividing a voltage of the pulse signal input through the input unit or the pulse signal attenuated by the attenuator circuit. Using the capacitive divider circuit, the high voltage wideband pulse attenuator can easily measure an error of an attenuation value caused by a change in the resistance of T-shaped array resistor units in a process of attenuating an input pulse signal of tens of kV or more. In particular, the pulse attenuator can measure its performance by itself without test assisting devices, and check a state of an attenuated pulse in real-time.

Abstract: An ortho-mode transducer may include a common waveguide terminating in a common port. A horizontal branch waveguide may terminate in a horizontal port. The horizontal branch waveguide may couple a first linearly polarized mode from the horizontal port to the common waveguide. The horizontal branch waveguide may comprise one or more ridged waveguide segments. A vertical branch waveguide may terminate in a vertical port opposed to the horizontal port. The vertical branch waveguide may couple a second linearly polarized mode from the vertical port to the common waveguide, the second linearly polarized mode orthogonal to the first linearly polarized mode.

Abstract: The present invention relates to microwave circuits, and more particularly to bypass circuits for bias connections. The bypass circuit comprises a capacitor in series with an inductor, the series combination being connected between the bias conductor and ground. This series combination provides low return loss at the operating frequency. A de-queueing circuit may be included in the bypass circuit to provide loss at other frequencies.

Abstract: A piezoelectric thin film resonator of the present has a substrate 1, an intermediate layer 7 disposed on the substrate 1 and is formed of an insulator, a lower electrode 3 disposed on the intermediate layer 7, a piezoelectric film 4 disposed on the lower electrode 3, and an upper electrode 5 disposed on a position facing the lower electrode 3 with the piezoelectric film 4 interposed therebetween, in which, in a resonant region 8 where the lower electrode 3 and the upper electrode 5 face each other, a space 6 is formed in the substrate 1 and the intermediate layer 7 or between the lower electrode 3 and the intermediate layer 7 and the region of the space 6 is included in the resonant region 8. With the structure, the dissipation of the vibrational energy to the substrate from the resonance portion can be suppressed, thereby improving the quality factor.

Abstract: An apparatus for wireless power transmission is disclosed. According to an exemplary aspect, the wireless power transmission apparatus includes a high Q low frequency near magnetic field resonator having characteristics of a metamaterial. Accordingly, manufacturing of a compact power supply capable of wirelessly supplying power to mobile communication terminals or multimedia terminals is possible. By using a zeroth-order resonator with a DNG or ENG structure, a small-sized power supply with a simple configuration may be manufactured.