Abstract: Power switching circuitry has a heat absorbing structure, and a heat conductive substrate having power switching components on a first surface and a second surface adjacent to the heat absorbing structure. Electrically conductive members, comprising first and second members, are on the first surface and extend along a first axis orthogonal to the heat conductive substrate. The second portion is more remote from the heat conductive substrate, and has a smaller cross-sectional area than, the first portion to define a shoulder region orthogonal to the first axis. A circuit board is located on the shoulder regions, with the second portions extending through the circuit board. An urging mechanism urges the circuit board against the shoulder regions, whereby the electrically conductive members provide a current path between the heat conductive substrate and the circuit board, and urge the heat conductive substrate into thermal contact with the heat absorbing structure.

Abstract: A tube includes a tube body and a heat-dissipating member. A light-emitting module and a first electronic component connected electrically to the light-emitting module are disposed in the tube body. At least one opening is formed on the tube body in correspondence to the first electronic component. The heat-dissipating member is placed over the opening. The heat-dissipating member provides a first heat-dissipating path for the first electronic component.

Abstract: An substantially planar information device is provided comprising: a memory module including a memory device and an electrical interface to connect the memory device to a complementary interface of a computing device; and a housing including a recess in which the memory module can be removably received, a receptacle to receive the electrical interface when the memory module is received in the recess, wherein the memory module and the housing are substantially planar such that the information device can be affixed to a planar substrate without substantially changing the profile of the planar substrate.

Abstract: A portable external power-supplying device is disclosed. The portable external power-supplying device implements a unique mechanism to detachably assemble battery units whose number can be adjusted according to user needs, which means the overall aggregate capacity of the portable external power-supplying device is adjustable. The portable external power-supplying device is adaptive to connect and charge a portable electronic device.

Abstract: A feed circuit for connecting adjacent components includes: a printed circuit board having a first portion and an axis of symmetry extending along a longitudinal direction of the first portion, second portions extending in substantially opposite directions from one end of the first portion, and third portions extending in substantially opposite directions from another end of the first portion; at least two circuits electrically connecting respective ones of the second portions with corresponding ones of the third portions; and connection areas at each of the second portions configured to be connected to one of the adjacent components, and at each of the third portions configured to be connected to another one of the adjacent components.

Abstract: The present invention pertains to a hard disk drive form factor compatible solid-state storage device enclosure assembly that protects circuit boards contained within the enclosure from environmental disruption, such as mechanical stress, vibration, external electronic disruption, or any combination of these, while allowing for a variable number of circuit boards in the SSD enclosure. In another embodiment, the solid-state storage device enclosure assembly, or a similar circuit board assembly, includes an alignment guide that precludes a circuit board from being misaligned within the enclosure.

Abstract: A bus bar device 1 includes a bus bar 2 connected to a battery post 52 provided in a battery 50, an insulative housing 3 that covers the bus bar 2, a circuit board 5 attached to the housing 3 and an electronic parts 4 mounted on the circuit board 5. The bus bar 2 includes a first flat plate part 9 having a battery attaching part 13 to which the battery post 52 is attached, a second flat plate part 11 having a first parallel part 16 parallel to the first flat plate part 9 and an electric wire connecting part 21 extended from the first parallel part 16 to connect a terminal fitting of an electric wire connected to a load and a third flat plate part 10 provided between the second flat plate part 11 and the first flat plate part 9 and arranged in parallel with the circuit board 5. The third flat plate part 10 is provided in a direction intersecting the first flat plate part 9.

Abstract: A housing for electrical components is provided. The housing may include a mouth portion to cooperate with a circuit board in an assembled condition wherein said circuit board is applied against said mouth portion of the housing. The housing may include at least one spring formation located at said mouth portion to cooperate with said circuit board to elastically urge said circuit board away from said mouth portion, and at least one hook-like formation extending from said mouth portion distally of said housing, said hook-like formation adapted to cooperate with said circuit board to retain said circuit board assembled to said housing against the force exerted by said spring formation.

Abstract: A substrate structure and a package structure using the same are provided. The substrate structure includes a number of traces, a substrate core and a number of first metal tiles. The substrate core has a first surface and a second surface opposite to the first surface. The first metal tiles are disposed on one of the first surface and the second surface, the minimum pitch between adjacent two of the first metal tiles is the minimum process pitch.

Abstract: An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites.

Abstract: An anti-eavesdropping device is described. The device comprises a receiving compartment for receiving an electronic device, a noise generator, and an EMI filter. The receiving compartment is sealable to minimize signal emissions from the interior to the exterior and from the exterior to the interior, and the noise generator is coupled with the receiving compartment and the EMI filter. The EMI filter is operatively coupled with the noise generator.

Abstract: The circuit board packaging structure capable of inserting and extracting an interface part of a circuit board into and from a connector part of the processing equipment in a direction different from a direction of attaching and detaching the circuit board to and from the processing equipment includes: an operating part which turns on receiving force; a plate part which is fixed to the circuit board to be rotatable in a direction reverse to a turning direction of the operating part, and converts the force received by the operating part to force in a direction different from the attaching and detaching direction to move the circuit board in that direction; a link part which connects the operating part with the plate part to transmit the force received by the operating part to the plate part; and a fastener which fastens the circuit board and the operating part with play.

Abstract: A key device includes: a chassis which has an opening divided by one of a vertical rib and a horizontal rib; a plurality of keys which are arranged along the opening; and a substrate which is housed in the chassis, wherein the rib is engaged with the substrate.

Abstract: The present invention, a modified zero voltage transition (ZVT) full bridge converter, is an isolated dc/dc converter which can operate with high efficiency and high reliability in applications requiring a low input voltage and high output voltage.

Abstract: In accordance with an embodiment, a switch controller for a switched-mode power supply includes an oscillator, an advance timing generator, and a dead zone generator. The advance timing generator generates an advance timing output pulse having a first pulse width that is asserted when the oscillator reaches a first phase. The dead zone generator produces a dead zone output having a second pulse width when the advance timing output pulse is de-asserted. This dead zone output pulse is coupled to a freeze input of the oscillator that freezes the phase accumulation of the oscillator when asserted. The controller also has a primary switch logic circuit that produces primary switch drive signals having a dead zone coincident with the dead zone output, and a secondary switch logic circuit that generates a secondary switch drive signal that is de-asserted when the advance timing output pulse becomes asserted.

Abstract: A constant current controller for a constant current power module, including: a demagnetization sensing unit, used for detecting the voltage variation of a detection signal to generate a discharging time signal having an active period corresponding to a secondary side discharging time, wherein the detection signal is derived from an auxiliary coil; a secondary side current sensing unit, used for detecting a peak value of a current sensing signal, and providing an output current according to the peak value of the current sensing signal under the control of the discharging time signal, wherein the current sensing signal is corresponding to a primary side current; and an error current generator, used for generating an error current according to the difference between the output current and a reference current, wherein the error current is converted to a threshold voltage by a first capacitor.

Abstract: The invention relates to a switched mode power converter and a method of operating such a converter A switched mode power converter according to the invention includes a transformer (2) having a primary winding (2a) and at least one secondary winding (2b) and a secondary side rectifier circuit including an output filter (6, 10) coupled to the at least one secondary winding (2b), and a secondary side active switch device (S3) coupled between the at least one secondary winding and the output filter. The converter further includes primary side and secondary side control means (12, 16, 18) for regulating the switching of the primary side and secondary side switches, respectively, and configured so as to reduce the duty cycle of the primary side switch device (S1) during a lower power mode of operation of the converter, the reduction of the duty cycle of the primary side switch being determined with reference to the duty cycle of the secondary side switch (S3).

Abstract: A control device for controlling a switching power supply adapted to convert an input voltage into an output voltage according to a switching rate of a switching element. The control device includes first control means for switching the switching element in a first working mode at a constant frequency and second control means for switching the switching element in a second working mode at a variable frequency, under a maximum frequency, in response to the detection of a predefined operative condition of the switching power supply. The control device further includes means for selecting the first working mode or the second working mode.

Abstract: One controller for a power supply includes an oscillator, a first circuit, a counter, and a pause circuit. The first circuit generates a drive signal to control switching of a switch to regulate an output of the power supply. The first circuit initiates an on time period of the switch in response to both a clock signal of the oscillator and an enable signal that is generated in response to a feedback signal of the power supply. The counter receives the enable signal and generates an output signal when the counter reaches a count value indicating that the enable signal has been idle for an amount of time. The pause circuit generates a pause signal in response to the output signal of the counter. The oscillator is paused in response to the pause signal and a maximum on time period of the switch is extended while the oscillator is paused.

Abstract: The present invention relates to a near zero current-ripple inversion circuit including top and bottom cells, a transformer (T1) comprising primary windings (P1, P2) and a secondary winding (S1), and at least one middle cell connected in series between the top and bottom cells. The top cell comprises two capacitors (C1, C2) and a switch (Q1) each connecting to the middle cell, and an inductor (Lr1) and the primary winding (P1) connected in series between the capacitor (C1) and switch (Q1), wherein the switch (Q1) is connected to the capacitors (C1, C2) respectively. The bottom cell comprises a capacitor (C3) and a switch (Q2) each connecting to the middle cell, and an inductor (Lr2) and the primary winding (P2) connected in series between the capacitor (C3) and switch (Q2), wherein the primary winding (P2) is connected to the middle cell, and the capacitor (C3) and switch (Q2) are connected.

Abstract: A plant for transmitting electric power includes a direct voltage network (100) and at least one three-phase alternating voltage network (101) connected thereto through a station (102). This station includes a Voltage Source Converter (103). A unit (104) is configured to control the converter according to a PWM pattern for generating an alternating voltage having a third harmonic voltage part added to a fundamental voltage part. No transformer is arranged between phase outputs (106) of the converter and the alternating voltage network (101). An arrangement (107) is configured to block the third harmonic voltage part and prevent it from reaching the alternating voltage network.

Abstract: A harmonic input current reduction and power factor correction circuit for three phase, power supplies. The circuit includes passive elements including a series inductance and capacitor connected between each AC line of a three phase voltage source, and each input phase of the uncorrected power supply. The inductance and capacitor are designed and chosen to meet linearity and volt ampere requirements to achieve total harmonic current levels of less than 10%, and power factors greater than 0.98. This is achieved with less than 1% loss in line operating input voltage range and overall efficiency of greater than 99.5%. Further, the dynamic response of a circuit to power supply load transient demands is limited in voltage overshoot or undershoot effects.

Abstract: This invention relates to a T-type three-level inverter circuit. The circuit includes an absorption unit.

Abstract: A timing circuit of a controller generates a clock signal having a switching period for use by a pulse width modulation (PWM) circuit to control a switch of a power supply. The switching period of the clock signal is based on a charging time plus a discharging time of a capacitor included in the timing circuit. A first current source charges the capacitor while the timing circuit is in a normal charging mode. A second current source charges the capacitor while the timing circuit is in an alternative charging mode that is when the on time of the switch exceeds a threshold time. The current provided by the second current source is less than the current provided by the first current source such that the switching period of the clock signal is increased in response to the timing circuit entering the alternative charging mode.

Abstract: The power supply according to the present invention comprises a transformer, a power switch, a signal generating circuit, an on-time detection circuit, and a delay circuit. The transformer receives an input voltage and generates an output voltage. The power switch switches the transformer for regulating the output voltage. The signal generating circuit generates a switching signal for controlling switching of the power switch. The on-time detection circuit detects an on-time of the power switch and generates a short-circuit signal. The delay circuit counts to a first delay time or to a second delay time in response to a feedback signal of the power supply and the short-circuit signal to generate a turn off signal for controlling the signal generating circuit to latch the switching signal.

Abstract: There is provided a power supply unit supplying a standby power by sharing a switch of a main converter. The power supply unit includes: a main converter, and a standby converter. The main converter controls a current flowing in a primary side winding of a main transformer and supplies a main power through a secondary side winding of the main transformer. The standby converter controls a current flowing in a primary side winding of a standby transformer and supplies a standby power through a secondary side winding of the standby transformer, and a portion of a plurality of switches of the main converter is included in switches of the standby converter.

Abstract: A power converter equipped with a plurality of semiconductor modules, a cooling device, a control circuit board, a smoothing capacitor, and a discharging resistor. The discharging resistor mounted on the control circuit board in parallel connection to the smoothing capacitor. The control circuit board has fabricated thereon a timing controller working to control timings of on/off operations of the semiconductor modules, a driver coupled to control terminals of the semiconductor modules to control voltage applied to the control terminals, and a power supply circuit working to transform a voltage input to the control circuit board into operating voltages for the timing controller and the driver. The driver is disposed between at least one of the timing controller and the power supply circuit and the discharging resistor, thereby protecting the timing controller and/or the power supply circuit mounted on the control circuit board from thermal energy radiating from the discharging resistor.

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

Abstract: A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; and a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers.

Abstract: A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value indicated by the internal fuse circuit.

Abstract: An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly.

Abstract: A ferroelectric memory device has word, bit, plate lines; memory cells having access gate and ferroelectric capacitor; latch amplifier for latching stored data; and write amplifier for driving bit lines according to write data. The bit lines are precharged to a reference potential before an active period. In active period, at a first time, selected word line and plate line are driven to a high-level potential so that ferroelectric capacitor output electric charge to selected bit line, and at a second time, selected bit line is brought to reference potential regardless of write data so that first data is written to selected memory cell, and at a third time, plate line is driven to reference potential and is maintained; and in a precharge period, the write amplifier drives selected bit line to high-level potential according to write data so that second data is written to selected memory cell.

Abstract: An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.

Abstract: Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

Abstract: The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell.

Abstract: A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage<the second voltage), and (4) in the third state, makes a transition to the first state on application of a fourth voltage of the first polarity (the fourth voltage<the first voltage).

Abstract: A method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step, thereby setting the variable resistance element through the low resistance state to the high resistance state.

Abstract: A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.

Abstract: Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value.

Abstract: According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A based on a third clock, and data is exchanged between a bit line of the port A and the port A based on a first clock and data is exchanged between the bit line of the port A and the port B based on a second clock.

Abstract: A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch.

Abstract: Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer with a perpendicular and variable magnetization, a second magnetic layer with a perpendicular and invariable magnetization, and a first nonmagnetic layer between the first and second magnetic layer. The first magnetic layer has a laminated structure of first and second ferromagnetic materials. A magnetization direction of the first magnetic layer is changed by a current which pass through the first magnetic layer, the first nonmagnetic layer and the second magnetic layer. A perpendicular magnetic anisotropy of the second ferromagnetic material is smaller than that of the first ferromagnetic material. A film thickness of the first ferromagnetic material is thinner than that of the second ferromagnetic material.

Abstract: A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell.

Abstract: A memory cell changes a potential of a bit line to a discharge potential from a precharge potential in correspondence with held data. A sense amplifier precharges a bit line by a precharge circuit, compares potential at a decision point linked with the potential of the bit line with a decision threshold and outputs a comparison result by an output circuit, and sets the potential at the decision point at a time of precharging in correspondence with the decision threshold. A capacitor element connects between the bit line and an input end of the output circuit. A potential setting circuit enables setting of an input end of the output circuit forming a decision point, to a prescribed potential between a precharge voltage of the bit line and the decision threshold at a time of precharging the bit line. Operating range of memory function is enlarged.

Abstract: A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.

Abstract: Disclosed is a non-volatile memory device which includes a memory cell array having memory cells arranged in rows and columns, a page buffer circuit configured to read data from the memory cell array, and a control logic and input/output interface block including a normal read scheduler controlling a normal read operation and a data recover read scheduler controlling a data recover read operation and configured to control the page buffer circuit at a read request. One of the normal read scheduler and the data recover read scheduler is selected according to selection information provided from an external device.

Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

Abstract: A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds to a control parameter of the cells, is measured, and the value of the reference voltage is adjusted accordingly. Examples of environmental parameters include program-erase cycle count, data retention time and temperature. Examples of reference voltages include read reference voltages and program verify reference voltages. Examples of statistics include the fraction of cells whose threshold voltages exceed initial lower bounds or initial medians.

Abstract: Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled.