Abstract: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

Abstract: A flash memory device includes a memory cell array, a seed selector circuit, and a randomizing and de-randomizing circuit. The memory cell array includes memory cells forming multiple pages. The seed selector circuit stores seeds corresponding to the multiple pages, respectively. The randomizing and de-randomizing circuit randomizes data to be stored in a selected page. Each page has a corresponding seed and includes multiple sectors having corresponding sector offset values and seed values generated from the seed corresponding to the page. The seed selector circuit selects a seed value from the seed values of the selected page based on a sector offset value indicating a sector of the selected page to which a column offset value, input with an access request, belongs. The randomizing and de-randomizing circuit randomizes data to be stored in the selected page based on the seed value selected by the seed selector circuit.

Abstract: A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition.

Abstract: Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector.

Abstract: The present invention discloses a reference cell circuit which is applied to a non-volatile memory. The reference cell circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit. The reference cell array includes at least one row of floating gate transistors. The first current mirror circuit is arranged to generate a mirror current according to a reference current generated by the reference cell array. The second current mirror circuit is arranged to receive the mirror current and generate an adjusted reference current according to the mirror current and a selected one of a plurality of enable signals, wherein the plurality of enable signals correspond to a plurality operations of the non-volatile memory and the adjusted reference current is arranged to determine logical state of a plurality of memory cells of the non-volatile memory.

Abstract: A method for erasing a memory array is provided. The memory array comprises a plurality of memory cell strings, and each of the memory cell strings comprises a plurality of memory cells connected to a plurality of word lines. The method for erasing the memory array includes the following steps. A first voltage is applied to a substrate of the memory array. A second voltage is applied to a word line of a selected memory cell, and a plurality of passing voltages are applied to other word lines. And, a third voltage and a fourth voltage are respectively applied to a first source/drain region and a second source/drain region of the selected memory cell, so that a band to band (BTB) hot hole injecting method is induced to erase the specific memory cell, wherein the third voltage is not equal to the fourth voltage.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.

Abstract: A non-volatile memory device is disclosed, which performs a sensing operation using a current. The non-volatile memory device includes a cell array including one or more unit cells, configured to read or write data, a current-voltage converter configured to convert a sensing current corresponding to data stored in the unit cell into a sensing voltage, and perform a precharge operation of the sensing voltage upon receiving the sensing current in response to a current driving signal at an activation time point of a word line of the cell array, and a sense-amp configured to compare the sensing voltage with a predetermined reference voltage, and amplify the compared result.

Abstract: A semiconductor memory apparatus includes: a skew monitoring unit configured to receive a reference voltage and monitor a voltage characteristic of a corresponding MOS transistor; a voltage sensing unit configured to provide a sensing voltage corresponding to the monitoring result of the voltage characteristic; a coding unit configured to multiplex an output signal of the voltage sensing unit and provide a skew control signal; and an internal voltage regulation unit configured to provide an internal voltage by regulating an internal bias voltage in response to the skew control signal.

Abstract: A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.

Abstract: A semiconductor memory includes a memory array having at least one bit line, a tracking bit line, and a global tracking circuit. The tracking bit line is configured to emulate a voltage transition of the at least one bit line. The global tracking circuit is configured to generate a timing signal for generating a negative voltage with respect to ground on the at least one bit line of the memory array.

Abstract: A data transmission circuit includes an enable signal generation unit configured to receive a first enable signal and generate a second enable signal having a pulse width controlled according to a swing width of data inputted through a first data line, and a sense amplification unit configured to sense and amplify the data inputted through the first data line in response to the second enable signal, and transmit the amplified data to a second data line.

Abstract: A clock handoff circuit outputting data in synchronism with a first clock input thereto as output data in synchronism with a second clock, includes: a dual port RAM capable of performing writing and reading independently of each other; a write address control section controlling write addresses of the dual port RAM in which the input data is written; a blank address detecting section detecting blank addresses among the write addresses in which the input data is not written; and a read address conversion section converting the write addresses of the dual port RAM excluding the blank address into read addresses from which the output data are read out.

Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Abstract: A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.

Abstract: A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.

Abstract: An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal.

Abstract: An acoustic sensor apparatus includes a housing, a fastener structured to fasten together the housing and an electrical power conductor, an acoustic sensor structured to detect acoustic noise from the electrical power conductor and output a signal, and a circuit structured to detect an electrical conductivity fault from the signal.

Abstract: A computer-implemented method includes providing a first velocity model obtained from a vertical seismic profile survey representative of an upper region of a subterranean formation. Wavefields from the first velocity model are datumed using wave equations to a datum line between the upper region and a target area beneath the upper region to obtain datumed wavefields. The method further includes obtaining interferometric common shot data and interferometric common midpoint data from the datumed wavefield using wave equations at the datum line. The first velocity model, the datumed wavefield, wavefield equations, and the interferometric common midpoint data are then used to generate a second velocity model representative of velocities in the target area.

Abstract: Technologies are generally described for an integrated circuit that is designed to serve as the basis of SONAR sensors that provide high sensitivity, low noise, low cost, and electronically adjustable gain in a small package may incorporate transducer drivers and signal sensing functions. Electronically programmable gain of the circuit may provide flexibility in system designs for gain management, and eliminate a need for manual gain adjustments in production. Power may be supplied to the sensor(s) over a power line of the circuit from a direct current source through a resistor. The same line may also be used for communicating with the sensor(s). Data from the microcontroller may be transmitted to the sensor(s) using an open-drain driver transistor and received through another transistor isolating the micro-controller's input from potentially high voltages present on the power line.

Abstract: Disclosed is an acoustic signal detector for detecting a target with moving in water. The acoustic signal detector may include a body having a front portion, the front portion having a cross section which becomes gradually narrow and an end formed to have a plane. The plane may be perpendicular to a moving direction of the acoustic signal detector. The acoustic signal detector may further include a plurality of sensor arrays configured to generate sound and detect sound returned by being reflected by a target. The plurality of sensor arrays may be mounted on a side surface of the front portion and on the plane.

Abstract: A method of deterring mammals comprising configuring an acoustic deterrent system to emit an acoustic signal having characteristics which repel the mammals by eliciting an acoustic startle response reflex in said mammals.

Abstract: A sensor device (100) is adapted to be installed at a land-air interface. The sensor device (100) comprises a fluid-filled housing (101) and a sensor arrangement (102, 103) supported within the housing (101) and coupled directly to the fluid so as to detect movement thereof. A seismic sensor installation comprises a sensor device (100) installed at a land-air boundary, wherein the sensor device comprises a fluid-filled housing (101) and a sensor arrangement (102, 103) supported within the housing (101) and coupled directly to the fluid as to detect movement thereof.

Abstract: A process for producing a capacitive electromechanical conversion device by bonding together a substrate and a membrane member to form a cavity sealed between the substrate and the membrane member, the process for producing a capacitive electromechanical conversion device comprises the steps of: providing a gas release path penetrating from a bonded interface between the substrate and the membrane member to the outside, and forming the cavity by bonding the membrane member with the substrate with the gas release path provided; the gas release path being provided at a location where the path does not communicate with the cavity.

Abstract: A clock shower head includes a hollow body, a hydroelectric generator, a storage battery, a clock processor, a clock displayer and a main control circuit; the hydroelectric generator, the storage battery, the clock processor and the main control circuit are disposed inside the sealing zone of the hollow body. The clock shower head has both illuminating and time display function. People can see the time when enjoying the shower using the clock shower head.

Abstract: Disclosed is a time code discrimination apparatus that discriminates a time code including one-minute digit and ten-minute digit codes. The time code discrimination apparatus includes: a first code acquiring section to acquire a plurality of sets of one-minute digit codes at a time interval in which the plurality of sets of one-minute digit codes are equal in value of one-minute digit; and a first code discrimination section to execute a process of reducing erroneous discrimination on the plurality of sets of one-minute digit codes acquired by the first code acquiring section, and to discriminate the one-minute digit codes.

Abstract: A timepiece with a wireless function comprises a movement that displays time; a conductive case that holds the movement; a crystal that is disposed on a face side of the case and covers a face side of the movement; a conductive plate that is disposed between the movement and the crystal and reflects radio waves; and an antenna that has a substantially annular, conductive antenna electrode and is disposed along an outside edge of the conductive plate between the conductive plate and the crystal as seen in a lateral view. The antenna electrode is configured to receive the radio waves reflected by the conductive plate.

Abstract: The acoustic radiating membrane (1) is for assembly in a music box or a striking watch. The membrane is made with at least one area of asymmetrical shape, formed in the material of the membrane or with at least one area of asymmetrical shape having a different thickness from the general thickness of the membrane. It preferably includes two asymmetrical areas of elliptical shape (2, 3) which are partly superposed and have a different thickness from each other. The two ellipses (2, 3), preferably hollowed out of the membrane, are off-centre in relation to each other.

Abstract: A disk drive read head includes a slider. The slider has an air bearing surface, a trailing face, and a mounting face opposite the air bearing surface. The mounting face includes a mounting face recession. An interior surface of the mounting face recession includes an electrically conductive terminal. The read head also includes a magnetic transducer disposed on the trailing face of the slider. The read head also includes a laser device affixed to the electrically conductive terminal by a solder material. The laser device is at least partially recessed into the mounting face recession.

Abstract: A reproduction device, contains a rotatable operation disk part for performing an input related to reading of data stored in a memory and a capacitance sensor section for outputting a sensor value expressing a change of a capacitance according to depression of the rotatable operation disk part. The device also contains a storage part for storing a reference value corresponding to the sensor value obtained while the rotatable operation disk part is not depressed, and a control part for judging presence/absence of pressing on the rotatable operation disk part based on a vector quantity being a relative value obtained from a difference between the sensor value output from the capacitance sensor section and the reference value stored in the storage part.

Abstract: In one embodiment, the optical read/write apparatus includes a plurality of optical pickups arranged to cross tracks of an optical storage medium and a control section. On finding the data that has been written by any of those optical pickups inaccurate or on detecting any defect at a location where data is going to be written by any of the optical pickups, the control section instructs another one of the optical pickups to write that data on a different track from a track on which the data should have been written.

Abstract: A recording/reproducing apparatus, for producing a virtual disc independent upon a host PC, and for managing virtual discs with an easy operation, comprises a CPU 100, a memory 101, a storage I/F 102, an external I/F 103, a device portion (DP) controller portion 201, a virtual device portion (VDP) controller portion 202, a virtual serial ATA 601, a virtual ATAIP 602, and at least two (2) or more numbers of recording/reproducing apparatuses, wherein it is notices to a HOST PC that a device is connected to the device portion when a virtual disc is produced, and the virtual disc is cut off and also information corresponding thereto is deleted when taking out or an order of taking out is made from the HOST PC.

Abstract: There is provided an optical disc drive comprises an optical pick-up including a laser diode (LD) and a laser diode driver (LDD) for driving the laser diode, a digital signal processor (DSP) including a write strategy circuit and low voltage differential signaling (LVDS) drivers for transmitting a produced write strategy signal, a circuit board having the DSP mounted thereon and including a line for transmitting the write strategy signal, a transmission line connecting the circuit board and the LDD and transmitting a write strategy signal, and differential resistors connected between differential lines of outputs of the LVDS drivers. Especially, a resistor having a resistance value in a range of 80 to 500? is inserted between the differential lines of outputs of the LVDS driver inside the DSP.

Abstract: A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

Abstract: A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

Abstract: A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

Abstract: A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

Abstract: A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

Abstract: A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

Abstract: An optical device, a method of manufacturing the optical device, a replica substrate for manufacturing the optical device, and a method of producing the replica substrate are disclosed. The optical device includes a base, and a plurality of structures arranged at a fine pitch equal to or shorter than a wavelength of visible light on a surface of the base. Each of the structures is composed of protuberance. The structures have a depth distribution.

Abstract: [Problem] In a conventional multilayer optical disc, management information needs to be retrieved from the control area of its reference layer to find how many information layers there are in the optical disc. [Means for Solving the Problem] A multilayer optical disc according to the present invention has multiple information layers that are stacked one upon the other. The information layers include at least one layer on which layer number information, indicating its own place in the multiple information layers, and information about the total number of information layers included are both stored.

Abstract: A system for providing energy assisted magnetic recording (EAMR) heads using a substrate is described. The substrate has front and back sides and apertures therein. The apertures are through-holes between the front and back sides of the substrate. The system includes providing a transmission medium in the apertures and fabricating EAMR transducers on the front side of the substrate. The EAMR transducers correspond to the apertures and the EAMR heads. The system also includes electrically insulating the back side of the substrate. The back side of the substrate is also prepared for mounting of the lasers. The lasers then are coupled the back side of the substrate. The lasers correspond to the EAMR heads and are configured to provide light through the apertures to the EAMR transducers. The system also includes separating the substrate into the EAMR heads.

Abstract: The present invention relates to a transmitting apparatus for transmitting signals in a multi carrier system on the basis of a frame structure, each frame comprising at least one signalling pattern and one or more data patterns, said transmitting apparatus comprising frame forming means adapted to arrange first signalling data in said at least one signalling pattern in a frame, and adapted to arrange data in said one or more data patterns in a frame, whereby the data of said one or more data patterns comprise content data and sorting information enabling a sorting of the content data in the correct temporal order, transforming means adapted to transform said at least one signalling pattern and said one or more data patterns from the frequency domain into the time domain in order to generate a time domain transmission signal, and transmitting means adapted to transmit said time domain transmission signal.

Abstract: A method includes receiving signaling from a base station, where the signaling includes information descriptive of a muted resource element pattern configuration when operating in a cell that is associated with at least one multi-cell cooperation area. The method further includes making at least one measurement according to the received information for at least one of the cooperation areas for making an interference estimate and transmitting measurement results to the base station. Another method includes transmitting signaling that contains information descriptive of a muted resource element pattern configuration to a user equipment operating in a cell that is associated with at least one multi-cell cooperation area.

Abstract: A system and method are provided for Soft Interference Cancellation (SIC) in receiving Single Carrier Frequency Division Multiple Access (SC-FDMA) Multiple-Input Multiple Output (MIMO) signals. A receiver with Mr antennas accepts multicarrier signals transmitted simultaneously, with N overlapping carrier frequencies. The receiver removes a cyclic prefix (CP), and fast Fourier transforms (FFT) the multicarrier signal from each antenna, supplying Mr number of N-tone signals y. Using either parallel SIC (P-SIC) or successive SIC (S-SIC), interference is canceled in each of the Mr signals, and soft symbols are supplied for each of U layers. Interference is canceled using the P-SIC process by parallel processing the U layers in an i-th iteration, in response to feedback from an (i?1)th iteration. Alternatively, interference is canceled using the S-SIC process by sequentially processing the U layers in an i-th iteration, in the order of u0,u1, . . . , uU?1, using feedback generated from previously processed layers.

Abstract: Systems and methods are provided for transmitting information between an intended source and a receiver to minimize co-channel interference from at least one interfering source. Pilot subcarriers and data subcarriers may be broadcast from an intended source arid at least one interfering source. The pilot subcarriers may be shared across base stations or distributed among base stations in frequency, in time, or both. In addition, the frequency reuse factor of the pilot subcarriers may be different than the frequency reuse factor of the data subcarriers. A receiver receives a composite signal that corresponds with an intended signal from an intended source and an interfering signal from at least one interfering source. The portion of the received signal that corresponds to the intended signal may be recovered by the receiver based on the broadcast of the pilot subcarriers.

Abstract: A communications apparatus is provided. A receiving module receives a signal with a predetermined signal bandwidth. A low pass filter filters the signal to obtain a filtered signal. A filter bandwidth of the low pass filter is wide enough to pass the regular sub-carrier frequency components and at least half of the guard sub-carrier frequency components of the signal. An analog to digital converter samples the filtered signal with a sampling rate exceeding a standard sampling rate defined in accordance with the predetermined signal bandwidth of the signal to obtain a plurality of digital samples. A Fast Fourier Transform module performs a fast Fourier transform on a predetermined number of points of the digital samples to obtain a plurality of transformed samples. The predetermined number exceeds a standard number defined in accordance with the predetermined carrier bandwidth. A sub-carrier collector collects the data from the transformed samples.

Abstract: An OFDM system uses a normal mode which has a symbol length T, a guard time TG and a set of N sub-carriers, which are orthogonal over the time T, and one or more fallback modes which have symbol lengths KT and guard times KTG where K is an integer greater than unity. The same set of N sub-carriers is used for the fallback modes as for the normal mode. Since the same set of sub-carriers is used, the overall bandwidth is substantially constant, so alias filtering does not need to be adaptive. The Fourier transform operations are the same as for the normal mode. Thus fallback modes are provided with little hardware cost. In the fallback modes the increased guard time provides better delay spread tolerance and the increased symbol length provides improved signal to noise performance, and thus increased range, at the cost of reduced data rate.