Abstract: An isolated DC-DC converter includes a transformer, a main switch, an active clamp circuit and a control unit. The transformer has a primary winding. The main switch and the active clamp circuit are connected to the primary winding. The active clamp circuit has an auxiliary switch and a clamp capacitor connected in series. The control unit is provided for controlling the main switch and the auxiliary switch. The control unit performs a soft start operation of the converter before a normal operation. The control unit performs anti-saturation control before starting the soft start operation. The anti-saturation control includes an act of controlling the main switch and the auxiliary switch so that the auxiliary switch performs ON-OFF operation with the main switch kept OFF until voltage of the clamp capacitor drops below a level at which the transformer is to be magnetically saturated after starting the soft start operation.

Abstract: This invention provides a primary-side controlled power converter comprising: an RC network coupled to an auxiliary winding of a transformer of the primary-side controlled power converter to detect a reflected voltage of the transformer for generating a reflected signal, and a controller coupled to the RC network to receive the reflected signal for generating a switching signal; wherein the RC network develops a zero to provide a high-frequency path for shortening a rising time and a settling time of the reflected signal.

Abstract: Provided is a maximum power point (MPP) tracker for a PV cell inverter, and a PV cell inverter. The MPP tracker decouples output power oscillations from the input power generation and extracts maximum available power from the PV cell. The PV cell inverter uses the MPP tracker and generates a sinusoidal output current from the MPP tracker output. The sinusoidal output current may be fed to a power distribution grid. The PV cell inverter may use a pulse width modulation technique to cancel harmonics in the sinusoidal output current. The circuits use a minimum number of components and avoid use of large electrolytic capacitors.

Abstract: An embodiment common mode noise reduction apparatus comprises a common mode choke, a balance inductor, a first capacitor and a second capacitor. The common mode choke is placed between an input dc source and a primary side network of an isolated power converter. The balance inductor is coupled between an upper terminal of a primary winding of the isolated power converter and a negative terminal of the input dc source. The first capacitor is coupled between the upper terminal of a primary side of a transformer and an upper terminal of a secondary side of the transformer of the isolated power converter. The second capacitor is coupled between a lower terminal of the primary side of the transformer and a lower terminal of the secondary side of the transformer of the isolated power converter.

Abstract: A regulating apparatus with soft-start and fast-shutdown function is applied to a voltage-supplying apparatus. The regulating apparatus includes a soft-start and fast-shutdown circuit, a regulating circuit, and a ground circuit. When voltages are supplied from the voltage-supplying apparatus to the soft-start and fast-shutdown circuit, the regulating circuit, and the ground circuit, the ground circuit is connected to ground, so that the starting time of the regulating circuit is delayed by the soft-start and fast-shutdown circuit. When voltages are not supplied from the voltage-supplying apparatus to the soft-start and fast-shutdown circuit, the regulating circuit, and the ground circuit, the ground circuit is not connected to ground, so that the regulating circuit is shut down fast by the soft-start and fast-shutdown circuit.

Abstract: Disclosed are a switch controller, a switch control method, a converter using the same, and a driving method thereof. A first voltage is generated by using a voltage that is input to an input terminal, and a soft start signal is generated by using the first voltage during a soft start duration. A switching operation is controlled by using the soft start signal during the soft start duration.

Abstract: A converter includes a converter bridge (101) adapted to transfer electrical energy between the AC terminal (102) and the DC terminal (103) of the converter. The converter also includes electrical paths bypassing the converter bridge for conducting overvoltage transients occurring in the AC terminal around the converter bridge to the DC terminal. Each electrical path includes a unidirectionally conductive semiconductor component (104a, 104b, 104c), such as a diode, and a voltage-limiting component (105) for which the ratio of voltage change to current change is small when the voltage of the voltage-limiting component is greater than a predetermined threshold voltage. Because of the overvoltage protection thus achieved, AC chokes can be omitted from the AC terminal or at least they can be designed smaller, reducing the load-dependent voltage drop of the DC terminal.

Abstract: Circuit topologies and control methods for a power converter and are described.

Abstract: An embodiment of the invention relates to a power converter including an inductor coupled in series with a power switch and a resistor coupled to a winding of the inductor. Input and output power converter voltages including an input brownout condition or an output overvoltage condition are estimated, and the output voltage may be regulated, by sensing a current in the resistor. An input current waveform can thereby be controlled to replicate substantially the input voltage waveform. The controller adjusts an on time and terminates an off time of the power switch by sensing respectively a current and a change of current in the resistor. The controller may sense a current flowing in the resistor to select a line voltage range of the input voltage to the power converter. The controller may estimate an input current to the power converter employing the current flowing in the resistor.

Abstract: The present invention provides an apparatus for controlling a multiphase multilevel voltage source inverter. The apparatus includes a signal-generating unit and a converter. The signal-generating unit responds to an input signal to produce a switching strategy control signal and a duration timing control signal corresponding to the switching strategy control signal. The converting unit responds to the switching strategy control signal and the duration timing control signal to produce a switching signal. The voltage source inverter responds to the switching signal to generate a multiphase-and-multilevel AC voltage output.

Abstract: A power conversion apparatus includes a power converter, a voltage detector, a current detector, a detection voltage adjustor, and a controller. The power converter is configured to convert power from a power source into alternating-current power and is configured to output the alternating-current power to a power system. The voltage detector is configured to detect a voltage of the power system. The current detector is configured to detect a direct-current component of a current between the power converter and the power system. The detection voltage adjustor is configured to add a bias corresponding to the direct-current component to the voltage detected by the voltage detector, so as to generate a voltage detection signal, and is configured to output the voltage detection signal. The controller is configured to control the power converter to output an alternating-current voltage corresponding to the voltage detection signal.

Abstract: A power supply device includes a failure determination means that detects, based on a current detected by a current detector, a failure of the switching elements of each of the chopper sections, and the failure determination means obtains values of the current detected by the current detector at the timing of falling edges of control signals to the switching elements of each of the chopper sections, determines the failure when the obtained current values differ from each other, and transmits a failure signal to a generation control means. When receiving the failure signal, the generation control means limits an output current from a generator in a way such that the withstanding current of a non-failed chopper section out of the chopper sections of the phases is not exceeded.

Abstract: An example of the current source power conversion circuit is provided with a plurality of half-bridge rectifier circuits which are connected in parallel, each including a serial connection of a first switch circuit having a first self-turn-off element and a first diode which are connected in series to each other, and a second switch circuit having a second self-turn-off element and a second diode which are connected in series to each other. A first current electrode of said first self-turn-off element in one of said half-bridge rectifier circuits and a first current electrode of said first self-turn-off element in other one of said half-bridge rectifier circuits are short-circuited and connected.

Abstract: A multiple inverter and an active power filter system are disclosed in the invention, said multiple inverter can decrease the volume and harmonics, increase the efficiency and decrease the cost, and can be applied to various occasions. The technical scheme is: the filter assembly in the multiple inverter is installed at the output inductor of the multiple inverter for filtering the harmonics.

Abstract: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.

Abstract: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.

Abstract: A data holding device according to the present invention includes a loop structure portion LOOP for holding data using a plurality of logic gates (NAND3 and NAND4) connected in a loop, a nonvolatile storage portion (NVM) for storing in a nonvolatile manner the data held in the loop structure portion (LOOP) by using the hysteresis characteristics of ferroelectric elements, a circuit separating portion (SEP) for electrically separating the loop structure portion (LOOP) and the nonvolatile storage portion (NVM), and a set/reset controller (SRC) for generating a set signal (SNL) and reset signal (RNL) based on data stored in the nonvolatile storage portion (NVM), wherein the plurality of logic gates are each set and reset to an arbitrary output logic level in accordance with the set signal (SNL) and reset signal (RNL).

Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

Abstract: An embodiment of the invention provides a method for decreasing power in a static random access memory (SRAM). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle. A second voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are not column addressed during a read cycle. Because the second voltage is less than the first voltage, power in the SRAM is reduced. In this embodiment, a memory cell in the SRAM includes at least one read buffer and a latch connected between the latch sourcing and latch sinking supply lines.

Abstract: A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.

Abstract: A data storage method includes writing data to a ferromagnetic shape-memory material in its ferromagnetic state, the material exhibiting more than two stable states. A data storage device includes a non-volatile memory element containing a ferromagnetic shape-memory alloy in a martensite state, the shape-memory alloy being ferromagnetic in a plurality of stable states of the memory element.

Abstract: According to one embodiment, a magnetoresistive element includes first and second magnetic layers and a first nonmagnetic layer. The first magnetic layer has an axis of easy magnetization perpendicular to a film plane, and a variable magnetization. The second magnetic layer has an axis of easy magnetization perpendicular to a film plane, and an invariable magnetization. The first nonmagnetic layer is provided between the first and second magnetic layers. The second magnetic layer includes third and fourth magnetic layers, and a second nonmagnetic layer formed between the third and fourth magnetic layers. The third magnetic layer is in contact with the first nonmagnetic layer and includes Co and at least one of Zr, Nb, Mo, Hf, Ta, and W.

Abstract: A method of writing data in a resistive memory device includes performing a test operation to distinguish normal memory cells from weak memory cells, during a write operation directed to normal memory cells using a write current and during a weak write operation directed to weak memory cells using a higher write current.

Abstract: One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.

Abstract: A magnetic tunnel junction having a ferromagnetic free layer and a ferromagnetic pinned reference layer, each having an out-of-plane magnetic anisotropy and an out-of-plane magnetization orientation, the ferromagnetic free layer switchable by spin torque. The magnetic tunnel junction includes a ferromagnetic assist layer proximate the free layer, the assist layer having a low magnetic anisotropy less than 700 Oe and positioned to apply a magnetic field on the free layer.

Abstract: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.

Abstract: A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell.

Abstract: A method for data storage includes storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing a storage value into the target memory cell. The storage value written into the target memory cell is verified while biasing the other memory cells in the group with respective first pass voltages. After writing and verifying the storage value, the storage value is read from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cells. The data is reconstructed responsively to the read storage value.

Abstract: The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The memory array may comprise a plurality of sub-blocks including a first sub-block and a second sub-block. Each sub-block may comprise a memory cell portion of the plurality of memory cells associated with a corresponding word line portion of the plurality of word lines. The memory cell portions in the first and second sub-blocks may be independently addressable with respect to each other such that a second operation can be performed on at least one memory cell of the memory cell portion of the second sub-block responsive to suspending a first operation directed to at least one memory cell of the memory cell portion of the first sub-block.

Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.

Abstract: A memory includes a memory cell including a first terminal, a second terminal and a channel extending between the first terminal and the second terminal. The memory further includes an energy storage element configured to support a programming of the memory cell, the energy storage element being coupled to the first terminal, an energy supply coupled to the energy storage element, and a controller. The controller is configured to activate the energy supply and to bring the channel of the memory cell into a non-conductive state for energizing the energy storage element, and to subsequently bring the channel of the memory cell into a conductive state for programming the memory cell based on the energy stored in the energy storage element.

Abstract: Disclosed herein are a method and apparatus for extending the lifetime of a non-volatile trapped-charge memory. A method includes setting limits of a memory sense window between an intrinsic threshold voltage of a non-volatile trapped-charge memory device and one of an end-of-life (EOL) value of a threshold voltage of a programmed state of the memory device and an EOL value of a threshold voltage of an erased state of the memory device. The data state of the memory device is then sensed.

Abstract: A method for programming a non-volatile memory device including a plurality of memory cells includes verifying whether the memory cells are programmed or not by applying a program verification bias voltage, which is calculated and stored during an initialization operation preformed before the programming of the memory cells, after a program voltage is applied to word lines of the memory cells.

Abstract: Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage current which flows through a leakage path of the intermediate node concerned. A charge pump circuit includes a step-up capacitor configured by a first capacitance and a second capacitance coupled in series, a capacitance driver, and a protection circuit. The protection circuit is set at a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated. Accordingly, relaxation of the withstand voltage of the step-up capacitor is achieved, and reduction of the pump efficiency is avoided.

Abstract: An apparatus and method for combating the effects of bias temperature instability (BTI) and other variability in a memory cell. Bit lines connecting to a memory cell contain two alternate paths that criss-cross to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit line. In this fashion, the memory cell may be read through the bit lines to a sense amplifier where the bit values are latched. While the bit values remain latched in the sense amplifier, the transistors on the bit lines are deactivated and the transistors on the alternate paths are activated.

Abstract: A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.

Abstract: A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

Abstract: Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.

Abstract: A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl.

Abstract: Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed are determined from external memory addresses and the row decoder for the portions of the memory array to be accessed are selectively provided with electrical power. The section of memory is then accessed. One such array includes memory section voltage supply rails having decoder circuits coupled to receive electrical power, and further includes memory section power control logic. The control logic selectively couples the memory section voltage supply rail to a primary voltage supply to provide electrical power to the memory section voltage supply rail in response to being selected based on memory addresses.

Abstract: A storage unit (106) stores pieces of information regarding intensities of ultrasound waves detected by multiple oscillators (101) in time series. The multiple oscillators (101) receives an ultrasound wave reflected on an object (107), to which a second ultrasound wave (108) generated by an ultrasound probe (102) is focused, in order from an oscillator closest to the object (107). The second ultrasound wave (108) is transmitted in a direction different from that of a first ultrasound wave (103). Information regarding an intensity of the ultrasound wave reflected on the object (107), which is obtained by storing in the storage unit (106) in order from the oscillator closest to the object (107), is obtained. This information is subtracted from the pieces of information stored in the storage unit (106). Thus, a received signal from a side lobe is extracted to be subtracted from a whole received signal.

Abstract: Systems and methods create a velocity model for well time-depth conversion. In one implementation, a system optimizes a time-depth relationship applied to data points from a single well to estimate coefficients for a velocity function that models the data points. The system optimizes by reducing the influence of outlier data points, for example, by weighting each data point to decrease the influence of those far from the velocity function. The system also reduces the influence of top and bottom horizons of geological layers by applying data driven techniques that estimate the velocity function without undue dependence on the boundary conditions. The system can optimize estimation of a rate of increase in velocity to enable the velocity function to go through a data point on each top horizon. The system may also estimate each base horizon from trends in the data points and adjust the velocity function to go through a data point on each base horizon.

Abstract: A distance sensor has an ultrasound transceiver for transmitting ultrasound pulses and for receiving reflected ultrasound pulses from an object. A discriminator unit is configured for determining a center of distribution of the received reflected ultrasound pulse on the basis of the received reflected ultrasound pulse exceeding a first threshold value and subsequently dropping below a second threshold value. A propagation time analyzer device, is designed for determining, based on the determined center of distribution, the distance to the object.

Abstract: The invention relates to a method for determining the location of an impact on a surface of an object based on the analysis of an acoustic signal generated by the impact. This method further comprises a signal treatment step of weighting the acoustic signal to take into account spurious contributions in particular due to reflections at the border of the object.

Abstract: A termination for an end of a braid formed as a flat closed loop of braided strands expandable to an annular cylinder having a selected wall thickness includes a sleeve having a selected internal diameter. Spacers are configured to be applied on the braid such that when in contact with each other form an annular cylinder having an external diameter selected to fit inside the sleeve. The spacers have a bevel at one longitudinal end. A substantially cylindrical insert has a bevel at one longitudinal end at substantially a same bevel angle as on the spacers. A diameter of the insert combined with twice the wall thickness of the braid is larger than an internal diameter the spacers. When axial tension is applied to the braid, the bevel on the insert with braid thereon laterally urges the spacers outward. The sleeve limits lateral outward movement of the spacers.

Abstract: Disclosed are electromagnetic linear actuators used in acoustic vibratory sources for marine seismic surveying. An embodiment discloses a linear actuator for acoustic sources, comprising: magnetic circuitry comprising a gap; and a coil assembly comprising: a drive coil, wherein at least a first portion of the drive coil is configured to be moved in a linear path in the gap; a pair of ferromagnetic coil guides positioned on either side of the linear path; a first ferromagnetic extension extending laterally from the first portion of the drive coil; and a transmission element coupled to a top side of the first portion of the drive coil. Embodiments also disclose acoustic vibratory sources, marine seismic survey systems, and methods of marine seismic surveying.

Abstract: The systems described include a light-weight, low frequency (200 Hz-1000 Hz), broadband underwater sound sources that comprise an inner resonator tube with thin walls tuned to a certain frequency surrounded by a shorter, larger-diameter, lower frequency tuned outer resonator tube that has an acoustic source suspended off-center inside the inner resonator tube.

Abstract: Systems and methods for increasing media absorption efficiency using interferometric waveguides in information storage devices are described. One such system for an interferometric waveguide assembly includes a light source, a first waveguide arm and a second waveguide arm, a splitter configured to receive light from the light source and to split the light into the first waveguide arm and the second waveguide arm, and a near field transducer (NFT) configured to receive the light from the first waveguide arm and the second waveguide arm, where the first waveguide arm and the second waveguide arm converge to form a preselected angle at a junction about opposite the splitter, and where the first waveguide arm and the second waveguide arm are configured to induce a preselected phase difference in the light arriving at the NFT.

Abstract: A method and system for providing an energy assisted magnetic recording (EAMR) transducer coupled with a laser. The EAMR transducer has an air-bearing surface (ABS) configured to reside in proximity to a media during use. The EAMR transducer includes a write pole, at least one coil, a waveguide and an output device. The write pole is configured to write to a region of the media. The at least one coil is for energizing the write pole. The waveguide has an input optically coupled to the laser and configured to direct energy from the laser toward the ABS for heating the region of the media. The output device is optically coupled to the waveguide. The output device coupling out a portion of the energy not coupled to the media.

Abstract: An optical information recording medium includes: a recording layer 12 comprising a multi-photon absorption compound and a one-photon absorption compound; and a supporting member (base layer 11) configured to support the recording layer 12. In this optical information recording medium, absorption of multiple photons by the multi-photon absorption compound and absorption of one photon by the one-photon absorption compound cause a void to be generated in the recording layer, whereby information is recordable by modulation based on a presence or absence of a void.