Patents Issued in March 11, 2014
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Patent number: 8671252Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.Type: GrantFiled: February 26, 2013Date of Patent: March 11, 2014Assignee: Mosaid Technologies IncorporatedInventors: Jin-ki Kim, Hakjune Oh, Hong Beom Pyeon, Steven Przybylski
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Patent number: 8671253Abstract: Various embodiments for storage initialization and data destage in a computing storage environment are provided. At least a portion of data on a storage device is initialized using a background process, while one of simultaneously and subsequently destaging the at least the portion of the data to the storage device using a foreground process is performed. A persistent metadata bitmap, adapted to indicate whether the at least the portion of the data has been initialized, is staged to cache, the cache operable in the computing storage environment. The background process maintains a volatile bitmap indicating a status of the initialization of the at least the portion of the data in direct correspondence to the metadata bitmap. As the background process initializes the at least the portion of the data, an applicable bit on the persistent metadata bitmap is cleared and a corresponding bit is set on the volatile bitmap.Type: GrantFiled: January 2, 2013Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Ellen J. Grusy, Matthew J. Kalos, Kurt A. Lovrien, Matthew Sanchez
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Patent number: 8671254Abstract: A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.Type: GrantFiled: September 1, 2011Date of Patent: March 11, 2014Assignee: Texas Instruments IncorporatedInventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
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Patent number: 8671255Abstract: In accordance with one example, a method for comparing data units is disclosed comprising generating a first digest representing a first data unit stored in a first memory. A first encoded value is generated based, at least in part, on the first digest and a predetermined value. A second digest representing a second data unit stored in a second memory different from the first memory, is generated. A second encoded value is derived based, at least in part, on the second digest and the predetermined value. It is determined whether the first data unit and the second data unit are the same based, at least in part, on the first digest, the first predetermined value, the first encoded value, and the second digest, by first processor. If the second data unit is not the same as the first data unit, the first data unit is stored in the second memory.Type: GrantFiled: March 26, 2012Date of Patent: March 11, 2014Assignee: Falconstor, Inc.Inventors: Wai Lam, Ronald S. Niles, Xiaowei Li
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Patent number: 8671256Abstract: A system and computer program product for migrating contents of a memory on a virtual machine. The system includes a source virtual machine executing on a host system, the source virtual machine including a memory. The system also includes a hypervisor executing on the host system. The hypervisor is in communication with the source virtual machine and includes instructions. The instructions facilitate establishing communication from the source virtual machine to a target virtual machine, the source virtual machine including a memory. The contents of the memory on the source virtual machine are transmitted to the target virtual machine. The contents of the memory on the source virtual machine include a plurality of pages. It is determined if all or a subset of the pages have been modified on the source virtual machine subsequent to being transmitted to the target virtual machine.Type: GrantFiled: August 27, 2007Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventor: Eli M. Dow
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Patent number: 8671257Abstract: According to one embodiment, a valid-cluster search module searches valid clusters included in first blocks, in each of channels, for compaction. A read command generator generates read commands used to read, in parallel, valid clusters to be migrated to a second block. The valid clusters searched in each of the channels comprise the valid clusters to be migrated. The valid clusters to be migrated correspond to a number of clusters simultaneously written to the second block and to a second number of channels in a first number of channels. A determination module determines the second number of channels corresponding to read commands to be generated next based on a situation of issuance of the read commands.Type: GrantFiled: March 16, 2012Date of Patent: March 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoko Masuo, Wataru Okamoto, Hironobu Miyamoto
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Patent number: 8671258Abstract: Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge.Type: GrantFiled: March 27, 2010Date of Patent: March 11, 2014Assignee: LSI CorporationInventor: Ross Stenfort
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Patent number: 8671259Abstract: A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening comprises writing data in volatile memory to non-volatile memory. The data that is hardened comprises user data and protected data. The data hardening command optionally comprises one or more of a flush cache command, a sleep command, and a standby immediate command.Type: GrantFiled: December 31, 2012Date of Patent: March 11, 2014Assignee: LSI CorporationInventor: Ross John Stenfort
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Patent number: 8671260Abstract: According to one embodiment, a memory system includes a memory that includes a plurality of parallel operation elements, each of which stores therein write data from a host device and on each of which read/write is individually performed, a control unit that performs the read/write to the parallel operation elements simultaneously, and a required-performance measuring unit that measures a required performance from the host device are included. The control unit changes the number of simultaneous executions of the read/write of the parallel operation elements based on the required performance measured by the required-performance measuring unit.Type: GrantFiled: September 20, 2010Date of Patent: March 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Abe, Kouhei Fujishige
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Patent number: 8671261Abstract: In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.Type: GrantFiled: April 14, 2011Date of Patent: March 11, 2014Assignee: Microsoft CorporationInventors: Gregory J. Colombo, Hari Pulapaka, Arun U. Kishan, Stephen L. Hufnagel, Garrett Trent Leischner, Evan Lincoln Tice, Matthew R. Miller
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Patent number: 8671262Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocks of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.Type: GrantFiled: August 30, 2011Date of Patent: March 11, 2014Assignee: STMicroelectronics (Crolles 2) SASInventor: Cedric Minne
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Patent number: 8671263Abstract: A method for Dynamic Storage Tiering (DST) may include identifying a first storage tier with a performance characteristic. The method may include monitoring the utilization of the first storage tier to detect the placement of a hot spot. The method may include logically dividing a continuous range of a plurality of logical addresses into at least a first segment and a second segment so the first segment includes a proportionally larger amount of the hot spot. The method may include moving the first segment into a second storage tier or moving the second segment into the second storage tier. The method may include determining an amount of utilization of the first storage tier by hot spots. The method may include recommending a change in an amount of storage space in the first storage tier based upon the amount of utilization of the first storage tier by the hot spots.Type: GrantFiled: February 3, 2011Date of Patent: March 11, 2014Assignee: LSI CorporationInventor: Martin Jess
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Patent number: 8671264Abstract: A storage control device for controlling the storage device including a medium for storing data, logical address information, and address translation information and a memory for storing the address translation information read from the medium includes a first receiver for receiving a write request including logical address information, a first sending module for sending a read request including the logical address information of the write request to the storage device, a second receiver for receiving data and logical address information stored in the medium in accordance with the read request from the storage device, and a second sending module for sending an instruction to cause the storage device to write the address translation information stored in the medium into the memory when the logical address information received by the second receiver is different from logical address information included in the write request.Type: GrantFiled: August 30, 2010Date of Patent: March 11, 2014Assignee: Fujitsu LimitedInventors: Eisaku Takahashi, Teiji Yoshida
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Patent number: 8671265Abstract: An access request including a client address for data is received. A metadata server determines a mapping between the client address and storage unit identifiers for the data. Each of the one or more storage unit identifiers uniquely identifies content of a storage unit and the metadata server stores mappings on storage unit identifiers that are referenced by client addresses. The one or more storage unit identifiers are sent to one or more block servers. The one or more block servers service the request using the one or more storage unit identifiers where the one or more block servers store information on where a storage unit is stored on a block server for a storage unit identifier. Also, multiple client addresses associated with a storage unit with a same storage unit identifier are mapped to a single storage unit stored in a storage medium for a block server.Type: GrantFiled: March 4, 2011Date of Patent: March 11, 2014Assignee: SolidFire, Inc.Inventor: David D. Wright
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Patent number: 8671266Abstract: Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.Type: GrantFiled: May 18, 2011Date of Patent: March 11, 2014Assignee: Altera CorporationInventors: Gerald George Pechanek, Stamatis Vassiliadis
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Patent number: 8671267Abstract: A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.Type: GrantFiled: June 24, 2010Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Christine C. Jones, Arthur J. O'Neill, Jr., Diana Lynn Orf, Robert J. Sonnelitter, III
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Patent number: 8671268Abstract: A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more dynamically configurable operator modules, the or each module being connectable to receive input operands indicated in an instruction, and a programmable lookup table connectable to receive dynamic configuration information determined from an opcode portion of the instruction and capable of generating operator configuration settings defining an aspect of the function or behavior of a configurable operator module, responsive to the dynamic configuration information in the instruction.Type: GrantFiled: March 11, 2011Date of Patent: March 11, 2014Assignee: ICERA, Inc.Inventor: Simon Knowles
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Patent number: 8671269Abstract: A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the instruction being speculatively executed a second rime. The first instance of the branch prediction value may be subsequently revised after the instruction associated with the first instance of the branch prediction value is retired. Information regarding whether that branch instruction was accurately predicted may then be used to update the branch prediction table and the second instance of the branch prediction value.Type: GrantFiled: November 16, 2010Date of Patent: March 11, 2014Assignee: Advanced Micro Devices, Inc.Inventors: James David Dundas, Nikhil Gupta, Marvin Denman
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Patent number: 8671270Abstract: A computer system including no basic input/output system (BIOS) for operating bootstrap used in initial activation of a legacy operation system is allowed to perform booting of legacy operation system therefor and includes a central processing unit (CPU) and a memory, in which extended firmware and bootstrap program are stored. The extended firmware includes BIOS emulator and a plurality of device drivers. The extended firmware uses the device driver to make the BIOS emulator perform emulation of BIOS operation in response to a BIOS call issued by the bootstrap program.Type: GrantFiled: January 9, 2009Date of Patent: March 11, 2014Assignee: Hitachi, Ltd.Inventors: Harumi Oigawa, Takashi Shimojo, Akira Takeshita, Takao Totsuka
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Patent number: 8671271Abstract: A system and method for a contextual control of resources of a computer. A plurality of detection modules may inform a configuration module of context changes and events. A database may store a plurality of configuration parameters and policies. A configuration module may configure a BIOS of a computer according to events, context and configuration policies. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2008Date of Patent: March 11, 2014Assignee: Safend Ltd.Inventors: Gil Sever, Pavel Berengoltz, Hay Hazama
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Patent number: 8671272Abstract: A touch control method for setting the basic input output system (BIOS) is provided. The setting method includes the following steps. The BIOS transmits an initial configuration data to a memory. An application program reads the initial configuration data from the memory and evocates an input interface displaying on a touch panel. The input interface includes a plurality of selecting items corresponding to the initial configuration data. The application program receives a setting signal from the touch panel and executes the selecting item according to the setting signal. The application program produces a renewal configuration data and the application program stores the renewal configuration data in the memory. The application program rewrites the renew configuration data back to the BIOS.Type: GrantFiled: June 29, 2011Date of Patent: March 11, 2014Assignee: Gigabyte Technology Co. LtdInventors: Huang Chen Chang, Ke Chih Hua, Wang Wan Chen
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Patent number: 8671273Abstract: A method and apparatus utilizes Layered IPSEC (LES) protocol as an alternative to IPSEC for network-layer security including a modification to the Internet Key Exchange protocol. For application-level security of web browsing with acceptable end-to-end delay, the Dual-mode SSL protocol (DSSL) is used instead of SSL. The LES and DSSL protocols achieve desired end-to-end communication security while allowing the TCP and HTTP proxy servers to function correctly.Type: GrantFiled: April 15, 2011Date of Patent: March 11, 2014Assignee: The University of MarylandInventors: Ayan Roy-Chowdhury, John S. Baras
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Patent number: 8671274Abstract: Systems and methods for authenticating a media device or other information handling system so as to be able to receive content from one or more media content providers. Authenticating the device includes determining what authentication information the media content providers require for access and then to generating and providing to the media device an authentication token that includes the required information. In some embodiments this may be accomplished by a service center, which removes the need for additional authentication steps to be performed by the media device or the media content providers. In addition, the service center may also determine when changes are made to the authentication information and may then ensure that the authentication token is changed or updated to reflect these changes. This ensures that the media device is at least partially immune to changes to authentication.Type: GrantFiled: October 28, 2008Date of Patent: March 11, 2014Assignee: Dell Products L.P.Inventors: Mark Andrew Ross, Timothy Bucher
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Patent number: 8671275Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.Type: GrantFiled: August 26, 2010Date of Patent: March 11, 2014Assignee: Intel CorporationInventors: Francis X. McKeen, Lawrence O. Smith, Benjamin Crawford Chaffin, Michael P. Cornaby, Bryant Bigbee
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Patent number: 8671276Abstract: The present invention provides a computer implemented method, system, and computer program product for selective encryption of a data transmission. A data transmission is received. When the data transmission is received, the data transmission is unmarshaled. When the transmission is unmarshaled, objects and a set of sensitive fields within the data transmission are identified by referencing a metadata database. Only the set of sensitive fields within the data transmission are encrypted to form a partially encrypted data transmission. The partially encrypted data transmission is marshaled to form a marshaled data transmission. The marshaled data transmission is transmitted to a recipient.Type: GrantFiled: June 9, 2008Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Kulvir Singh Bhogal, Johnston Jewell Clark, Jonathan G. Hall, Rick Allen Hamilton, II, John Dale Perkins, Alexandre Polozoff, Gioacchino J. Pullara, Hadi S. Qadri, Ryan Patrick Zombo, Peggy Catherine Zych
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Patent number: 8671277Abstract: A method for securely communicating a message from a source node to a destination node over a network can comprise the steps of converting the message into an initial bit sequence, pre-processing the initial bit sequence by a modulo adding the initial bit sequence with an auxiliary key message, constructing a reduced network, determining a multitude of paths from the source node to the destination node over the reduced network, constructing an expanded bit sequence comprising the initial bit sequence and the auxiliary key message, splitting the expanded bit sequence into two or more parts, transmitting the two or more parts of the expanded bit sequence over two or more paths of the multitude of paths, re-assembling the two or more parts of the expanded bit sequence at the destination node, and recovering the initial bit sequence by modulo adding the expanded bit sequence with the auxiliary key message.Type: GrantFiled: June 9, 2010Date of Patent: March 11, 2014Assignee: Syracuse UniversityInventors: Jin Xu, Biao Chen
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Patent number: 8671278Abstract: A method for authenticating a transmission between a first and a second circuit transiting through at least one third circuit, wherein: data are transmitted from the first to the third circuit, and from the third to the second circuit; a first signature of the data is calculated by the first circuit; at least a second signature of the data is calculated by the third circuit; at least one first portion of the first signature is transmitted by the first circuit to the third one; and the second signature is transmitted by the third circuit to the second one, a portion of this signature being distorted in case of a failure of authentication of the first portion of the first signature by the third circuit.Type: GrantFiled: July 25, 2011Date of Patent: March 11, 2014Assignee: STMicroelectronics (Rousset) SASInventors: Gilles Bas, Hervé Chalopin, François Tailliet
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Patent number: 8671279Abstract: Methods and apparatuses for performing secure incremental backup and restore operations are disclosed.Type: GrantFiled: June 19, 2012Date of Patent: March 11, 2014Assignee: Apple Inc.Inventors: Michael Lambertus Hubertus Brouwer, Mitchell D. Adler, Gordon J. Freedman
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Patent number: 8671280Abstract: An electronic document management program, an electronic document management method and an electronic document management apparatus acquire a plurality of pieces of part identification information respectively identifiably expressing a plurality of parts of document information and a digital signature corresponding to the document information, acquire the preparation type, the preparer's name and the time and date of preparation of the document information as tracing information of the document information, manage the part identification information, the digital signature and the tracing information in association with each other and present information relating to the tracing information to the user in response to a request from the user. Additionally, they acquire new document information and tracing information according to a directive from the user.Type: GrantFiled: January 15, 2009Date of Patent: March 11, 2014Assignee: Fujitsu LimitedInventor: Takashi Yoshioka
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Patent number: 8671281Abstract: A system and method for integrating the Internet front end-sign on processes of the various systems of a financial institution which allows a customer to view and access its various financial accounts with the institution. During the initial sign up for the online access to its accounts, a customer creates his/her User ID and password online during the same session. Once the customer has signed on (password) and verified ownership of at least one account, the system displays all of the customer's accounts that are available for access via the Internet website. The online ownership verification uses only a single account of the customer and the ownership verification criteria associated with the account. The account used for verifying a customer is first determined based on the accounts selected by the customer for accessing online. From the selected accounts, the system of the present invention creates a verification hierarchy with respect to the accounts.Type: GrantFiled: June 7, 2011Date of Patent: March 11, 2014Assignee: JPMorgan Chase Bank, N.A.Inventor: Kimberly Ellmore
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Patent number: 8671282Abstract: The present invention includes a system and process for monitoring the transmission of secured, marked digital files. A cryptographic token inertly embedded in markup language tags of digital files is sought at a transmission gateway.Type: GrantFiled: March 24, 2012Date of Patent: March 11, 2014Assignee: Mach 1 Development, Inc.Inventors: Paul L. Greene, Charles M. Tellechea, Jr.
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Patent number: 8671283Abstract: An information processing apparatus includes: a data processing unit that acquires content codes including a data processing program recorded in an information recording medium and executes data processing according to the content codes; and a memory that stores an apparatus certificate including an apparatus identifier of the information processing apparatus. The data processing unit is configured to execute an apparatus checking process applying the apparatus certificate stored in the memory on the basis of a code for apparatus checking process included in the content codes, acquire the apparatus identifier recorded in the apparatus certificate after the apparatus checking process, and execute data processing applying content codes corresponding to the acquired apparatus identifier.Type: GrantFiled: April 9, 2012Date of Patent: March 11, 2014Assignee: Sony CorporationInventor: Yoshikazu Takashima
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Patent number: 8671284Abstract: An application includes: a programming model including a service provider, first components, second components, and sinks communicating via messages. Each of the second components is assigned a unique capability. A given one of the first components routes a message from the given first component to second component(s) and then to a sink. Each of the second component(s) sends the message to the service provider. The service provider creates a token corresponding at least to a received message and a unique capability assigned to an associated one of the second component(s) and sends the token to the associated one of the second component(s). The selected sink receives the message and a token corresponding to each of the second component(s), verifies each received token, and either accepts the message if each of the received tokens is verified or ignores the message if at least one of the received tokens is not verified.Type: GrantFiled: September 12, 2012Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Bard Bloom, John H. Field, Salvatore Guarnieri, Marco Pistoia
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Patent number: 8671285Abstract: A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key.Type: GrantFiled: April 21, 2011Date of Patent: March 11, 2014Assignee: VIA Technologies, Inc.Inventors: G. Glenn Henry, Terry Parks, Brent Bean, Thomas A. Crispin
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Patent number: 8671286Abstract: In one embodiment, a power supply switching circuit may automatically provide power to a clock circuit from one of an auxiliary power supply and a main power supply, based on a voltage of the main power supply. To provide automatic switching, a switch circuit coupled between the power supplies and the clock circuit may be controlled by a voltage detector, in some embodiments.Type: GrantFiled: March 27, 2008Date of Patent: March 11, 2014Assignee: Silicon Laboratories Inc.Inventors: Wenjung Sheng, Shyam S. Somayajula, Xue-Mei Gong
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Patent number: 8671287Abstract: A redundant power supply configuration for a data center is provided. A method includes receiving instructions to operate power supplies at a high current mode. An individual current for each of the power supplies is calculated to total a high current at the high current mode. The power supplies are operated at the high current mode to provide the high current at the high current mode. In response to operation at the high current mode being complete, the power supplies are operated at a normal mode to provide a normal current at the normal current mode.Type: GrantFiled: June 23, 2010Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Casimer M. DeCusatis, Rajaram B. Krishnamurthy, Michael Onghena, Anuradha Rao
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Patent number: 8671288Abstract: Methods and apparatuses are provided for controlling power consumption in a processor (or computational unit thereof). The method comprises monitoring power consumption in a processor (or computational unit) and determining that the power consumption of the processor (or computational unit) exceeds a threshold. Thereafter, instruction issuance if modified (such as by slowing or ceasing instruction issuance) within the processor (or computational unit) until the power consumption is below the threshold. The apparatus comprises a power consumption monitor for determining when power consumption within the processor exceeds a threshold. Upon that determination, a scheduler begins modify instruction issuance to one or more execution units until the power consumption is below the threshold. The modification of instruction issuance can be to slow instruction issuance or cease instruction issuance for a time period or until the power consumption is below the threshold.Type: GrantFiled: December 21, 2010Date of Patent: March 11, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Jay Fleischman, Michael Estlick, Kevin Hurd
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Patent number: 8671289Abstract: In one aspect, a multi-port interface circuit applied to a playback apparatus which is able to switch among a plurality of input ports coupled to a plurality of source devices for playing back. Each input port has a receiver, the receiver including a front-end for receiving and processing a data stream from the source device and providing a data enable signal, and further including a content protection circuit for performing content protection according to the data enable signal. Each receiver records data enable information associated with the data enable signal of the data stream in an initial status. When one input port is selected, receivers of the other input ports operate in a power saving mode, the front-end circuits stop receiving the data stream, and the content protection circuit maintains operation according to a regenerated enable signal, which is regenerated according to the data enable information.Type: GrantFiled: June 2, 2011Date of Patent: March 11, 2014Assignee: MStar Semiconductor, Inc.Inventors: Jin-Chyuan Fuh, Pin-Chieh Huang, Shu-Rung Li
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Patent number: 8671290Abstract: A heat dissipating device is provided. The heat dissipating device includes at least one fan, a temperature detecting unit, a fan control unit, and a power consumption control unit. The temperature detecting unit detects a temperature inside the host. The fan control unit controls the rotating speed of the fan. The power consumption control unit calculates the total power consumption of the host, and outputs a control signal to the fan control unit according to the temperature inside the host and the total power consumption of the host, so as to adjust the rotating speed of the fan.Type: GrantFiled: June 14, 2011Date of Patent: March 11, 2014Assignee: Inventec CorporationInventor: Hsin-Jung Hsu
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Patent number: 8671291Abstract: Disclosed is a method (200) for charging energy storage devices. The method (200) can include a battery charging method in a power supply client connected by a data bus to a power supply host. The method (200) includes the steps of: detecting (210) a state of the power supply host; determining (220) a limit of current from the host to the client; allocating (230) a portion of the limit to a battery charging current; and charging (240) a battery of the client at the battery charging current such that the current from the host is greater than a recommended limit and less than or equal to the determined amount. Thus a client device can confidently charge at a rate which causes the port current to exceed a recommended limit, such as a USB port limit of 500 mA, when allowed by conditions of the host device.Type: GrantFiled: June 15, 2011Date of Patent: March 11, 2014Assignee: Motorola Mobility LLCInventors: Wayne W. Ballantyne, Gregory R. Black, Robert M. Johnson, Russell L. Simpson
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Patent number: 8671292Abstract: Apparatus and systems provide processing capabilities while utilizing power received via an Ethernet. A computing device has an Ethernet connector for receiving power and data, internal power supply circuitry for extracting power from the Ethernet connector, and a Central Processing Unit (CPU) for receiving the power. A housing may encompass the components of the computing device and be configured for installation in an electrical wall box. The housing may include a display or connectors for peripherals. A system includes at least two computing devices. Each device has an Ethernet connector for receiving power and communicating with other devices and are installed within a housing within an electrical wall box. One device has a display for receiving user input instructions for transmittal to another device, while another device has a peripheral connector for controlling a peripheral according to the instructions.Type: GrantFiled: July 13, 2011Date of Patent: March 11, 2014Assignee: American Megatrends, Inc.Inventor: Clas Gerhard Sivertsen
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Patent number: 8671293Abstract: Techniques described herein generally relate to optimizing energy consumption in a computer system. In some examples an energy usage benchmark can be determined for a system component of the computer system by measuring performance levels and energy usages of the system component under a range of energy settings and utilization rates of the system component. A utilization rate of the system component can be determined based on prediction factors including the execution of a first set of instructions on the computer system. The system component can be configured to execute a second set of instructions after the first set of instructions by selecting an energy setting from the range of energy settings for operating the system component. The energy setting can be selected based on the energy usage benchmark and the determined utilization rate.Type: GrantFiled: September 21, 2011Date of Patent: March 11, 2014Assignee: Empire Technology Development LLCInventors: Yong Qi, Yuehua Dai
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Patent number: 8671294Abstract: A method for environmentally cognizant power management that gathers server, application and environmental information from different devices to compute an aggregate behavior model.Type: GrantFiled: March 7, 2008Date of Patent: March 11, 2014Assignee: Raritan Americas, Inc.Inventors: Naim R. Malik, Vsevolod Onyshkevych, Christian Paetz, Siva Somasundaram, Neil Weinstock, Allen Yang
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Patent number: 8671295Abstract: A signal suitable for signaling a computer system to reduce power consumption is generated from a plurality of power supplies. The signal is asserted when at least one of the power supplies of the plurality of power supplies signals impairment, and at least one of the power supplies of the plurality of power supplies signals that the power supply is supplying current above a threshold level.Type: GrantFiled: July 30, 2009Date of Patent: March 11, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Stephen Ejner Horvath, Kevin Edward Boyum, Martin Goldstein
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Patent number: 8671296Abstract: A storage control apparatus includes a controller for receiving an access command from a host computer and controlling an access to a storage device and a monitoring period obtaining section for obtaining a monitoring period corresponding to the access command. The storage device is capable of operating in one of a power saving state and a normal state. The controller causes the storage device to return from the power-saving state to the normal state if the storage device corresponding to the access command is in the power saving state, and sends the host computer a response for preventing a timeout corresponding to the access command if the storage device have not yet returned to the normal state when the monitoring period elapses from receiving the access command.Type: GrantFiled: June 22, 2010Date of Patent: March 11, 2014Assignee: Fujitsu LimitedInventors: Masahiro Yoshida, Tadashi Matsumura
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Patent number: 8671297Abstract: In a multifunctional device, a packet analysis unit determines whether a received packet contributes to inhibition of a power saving mode, stores the time at which a packet is received and information indicating whether a packet is received during the power saving mode as information about the packet determined as contributing to the inhibition thereof, and calculates a period of access by a plurality of packets based on the stored information about the packet and a factor analysis unit classifies the access of which the calculated period is shorter than the waiting time of the power saving mode into an access inhibiting a shift to the power saving mode and classifies the access of which the period is not shorter than the waiting time of the power saving mode and which is made by the packet received during the power saving mode, into an access returning from the power saving mode.Type: GrantFiled: January 14, 2011Date of Patent: March 11, 2014Assignee: Canon Kabushiki KaishaInventor: Tadashi Hagiuda
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Patent number: 8671298Abstract: A method may include: calculating approximate power requirements of components, the components supplied with electrical energy from a plurality of power supplies, each of one or more of the plurality of power supplies capable of being enabled and disabled from supplying electrical energy to the components; determining a set of possible configurations of the plurality of power supplies such that for each possible configuration, enabled power supplies of the possible configuration have adequate aggregate capacity to deliver the approximate power requirements and switching to the possible configuration from a then-present configuration would require no more than one of then-disabled power supplies be enabled and no more than one of then-enabled power supplies be disabled; and determining which of the set of possible configurations has the highest expected power efficiency.Type: GrantFiled: February 17, 2011Date of Patent: March 11, 2014Assignee: Dell Products L.P.Inventors: Christopher C. Dumas, Ashish Munjal
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Patent number: 8671299Abstract: According to one general aspect, a method may include operating a computing device in a first power mode. The method may also include executing, by a processor of the computing device, at least one non-interactive task. The method may also include detecting, by a processor of the computing device, a request to place the computing device in a second power mode, wherein the second power mode consumes less system resources than the first power mode. The method may further include delaying the transition of the computing device to the second power mode until either the completion of the non-interactive task or an overriding triggering event.Type: GrantFiled: May 26, 2011Date of Patent: March 11, 2014Assignee: Google Inc.Inventors: Sameer Nanda, Ryan Cairns, Ryan Tabone
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Patent number: 8671300Abstract: A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.Type: GrantFiled: November 3, 2010Date of Patent: March 11, 2014Assignee: Hitachi, Ltd.Inventors: Noritaka Matsumoto, Tsutomu Yamada, Eiji Kobayashi, Akihiro Ohashi, Shin Kokura
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Patent number: 8671301Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.Type: GrantFiled: October 26, 2007Date of Patent: March 11, 2014Assignee: LG Electronics Inc.Inventors: Hyung Sun Kim, Kang Soo Seo, Byung Jin Kim, Soung Hyun Um