Abstract: Disclosed is a small-size, high-efficiency, isolated, bidirectional DC-DC converter. The bidirectional DC-DC converter includes a transformer in which windings are magnetically coupled, switching circuits, a diode which is connected in parallel with a switch, smoothing capacitors, and a control section. First and second DC power supplies, which are connected in parallel with the smoothing capacitors, respectively, provide bidirectional electrical power transfer. When electrical power is to be transferred from the first DC power supply to the second DC power supply, the switch is maintained in the ON state. When, on the other hand, electrical power is to be transferred from the second DC power supply to the first DC power supply, the switch is maintained in the OFF state to prevent a reverse electrical power flow from the first DC power supply.

Abstract: A PFC (Power Factor Correction) circuit improves the power factor of rectified power. Upon receiving output of the PFC circuit, a first DC-DC converter generates a voltage to be supplied to a load. Upon receiving output of the PFC circuit, a second DC-DC converter and a third DC-DC converter generate a control voltage. The second DC-DC converter and the third DC-DC converter are cascade-connected. An input terminal of the third DC-DC converter is connected to both an output terminal of the second DC-DC converter and an output terminal of the first DC-DC converter.

Abstract: A synchronous rectifying buck-boost converter includes a controller, first and second transistors, an inductor and a capacitor. The controller is connected to the gates of the first and second transistors for controlling ON/OFF of the first and second transistors, and further controls the current of the inductor and charge/discharge of the capacitor. The first and second transistors connected in series are connected to the controller and the inductor. The inductor is connected to a first external power unit or a first external loading device. The drain of the first transistor is connected to a second external power unit or a second external loading device such that a low-voltage input power of the first external power unit is converted to a high-voltage output power or a high-voltage input power of the second external power unit is converted to a low-voltage output power.

Abstract: The present invention includes: a converter configured to convert the direct-current voltage of the rectifier to another direct-current voltage and supply to a load; a peak hold unit configured to hold a peak value of a current detected by a current detecting unit configured to detect a current flowing in the switching element; an averaging unit configured to convert, to a current, an output of an n/2 output unit, and then integrate and output the converted current, the n/2 output unit configured to output n/2 (n is an integer of 1 or more) of the held peak value only in a regeneration current period of the reactor; a control unit configured to turn the switching element on and off based on an output signal of the averaging unit in such a way that an average current value of a current flowing in the reactor is equal to a predetermined value.

Abstract: An electronic converter may include transformer with a primary winding and a secondary winding, wherein the primary winding is coupled to an input for receiving a power signal, and wherein the secondary winding is coupled to an output including a positive terminal and a negative terminal for providing a power signal. The converter moreover may include an electronic switch arranged between the input and the primary winding, wherein the electronic switch is configured to control the current flow through the primary winding. Specifically, the converter may include a snubber circuit arranged between the secondary winding and the output.

Abstract: A switching power supply device includes a rectifying circuit configured to rectify an AC voltage and to output a rectified voltage, a smoothing capacitor configured to smooth the rectified voltage and to output a smoothed voltage, a first DC-DC converter configured to convert the smoothed voltage into an intermediate voltage and to output the intermediate voltage, and a second DC-DC converter configured to convert the intermediate voltage into an output voltage and to output the output voltage substantially free of ripple. The first DC-DC converter is configured to perform a step-up operation, a step-up/down operation, and a step-down operation according to the smoothed voltage, and to output the intermediate voltage including a ripple or the intermediate voltage substantially free of ripple.

Abstract: A control circuit of a power converter is provided. It comprises a signal generation circuit generating an oscillation signal in accordance with an output load. A PWM circuit generates a switching signal according to a voltage-loop signal, a current-loop signal and the oscillation signal for regulating an output of the power converter. A regulation circuit receives a compensation signal for an output cable compensation and a wake-up. The compensation signal is coupled to increase a switching frequency of the switching signal once the output of the power converter is lower than a low-voltage threshold. The control circuit reduces the voltage drop of the output when the output load is changed.

Abstract: A switching circuit including a transformer having a primary and a secondary side; a first MOSFET switch coupled with the primary side; a primary current sensing device; a second MOSFET switch coupled with the secondary side; a secondary current sensing device; and a control circuit for driving the first and second MOSFET switches, wherein first and second switch are complementarily driven and wherein switching of the first and second MOSFET switches is controlled by the primary and secondary current sensing devices

Abstract: A flyback converter includes a transformer and a controller operable for controlling a switch coupled in series with a primary winding of the transformer. The controller is configured to operate in multiple modes including a burst mode and a standby mode. In the burst mode, the controller generates a first plurality of discrete pulse groups to turn on the switch and a duration of each pulse in the first plurality of discrete pulse groups is determined by a first reference signal having a first predetermined voltage. In the standby mode, the controller generates a second plurality of discrete pulse groups to turn on the switch and a duration of each pulse in the second plurality of discrete pulse groups is determined by a second reference signal having a second predetermined voltage which is greater than the first predetermined voltage of the first reference signal.

Abstract: The present invention discloses a switch-mode power supply control apparatus comprising a PWM controller for outputting a driving signal and a short-circuit protection module coupled to a detection terminal. The detection terminal receives a zero-crossing detection voltage. If the time that the detection voltage input to the detection terminal is lower than a first reference voltage exceeds a predetermined time period, the short-circuit protection module determines that a short-circuit abnormal situation occurs, the short-circuit protection module outputs a short-circuit signal to the PWM controller, and the driving signal output by the PWM controller becomes a turn-off signal. If the short-circuit protection module does not detect the short-circuit abnormal situation, the PWM controller operates normally. The present invention further discloses a flyback switch-mode power supply comprising the switch-mode power supply control apparatus.

Abstract: A contactless inductively coupled power transfer system includes a power supply device and a power receiving device. The power supply device includes a primary winding for generating an electromagnetic field (EMF) in response to an AC current flow having an operating frequency. The power receiving device includes a resonant circuit outputting an output voltage to a load and including a secondary winding and a reactance element. The reactance element is capable of forming a parallel resonant LC circuit with the secondary winding that resonates at the operating frequency, and forming a series resonant LC circuit that resonates at the operating frequency, and that is to be connected in series to the load.

Abstract: An offshore wind farm includes a plurality of wind turbines connected to an onshore converter station by means of a distributed power transmission system. The power transmission system includes a series of offshore converter platforms distributed within the wind farm. Each converter platform includes a busbar carrying an ac voltage for the converter platform and to which the wind turbines are connected. Each converter platform also includes one or more converter transformers connected to the busbar and a series of one or more converter modules. The power transmission system includes dc transmission lines which deliver generated power back to the onshore converter station.

Abstract: The invention concerns an electrical module for adapting a first signal of a first system to a second signal of a second system, including: an input arranged so that a power source can be connected thereto, said power source delivering a first signal, said first signal being a direct signal, a converter module arranged to convert the supply voltage into an intermediate rectified signal formed of a direct component and a sinusoidal component; an inverter module arranged to output a signal compatible with a second signal of a second system.

Abstract: A power supply device includes: a first switching element and a flywheel semiconductor element which are connected in series to a first DC power source in this order; and a reactor and a second DC power source which are connected in series in this order to a node between the first switching element and the flywheel semiconductor element. A second switching element and a charge circuit for charging a line between the first switching element and the second switching element are interposed between the reactor and the second DC power source. Abnormality of each element is determined from a voltage of each portion of the power supply device measured when the first and second switching elements and the flywheel semiconductor element are driven and controlled.

Abstract: In an electronic circuit, a first circuit region is electrically connected to an input circuit region of an isolated switching power source, and a second circuit region is electrically connected to an output circuit region thereof. A driver of an IC is located in the second circuit region and drives a target device based on output power supplied to the second circuit region via the output circuit region from the isolated switching power source. A transferring module of the IC transfers a value of a parameter indicative of the output power from the second circuit region to the first circuit region while maintaining electrical isolation between the first and second circuit regions. An operating module of the IC performs on-off operations of a switching element to perform feedback control of the value of the parameter indicative of the output power to a target value.

Abstract: The invention relates to a method for operating an inverter (1), in particular a pulse-controlled inverter, comprising multiple phase systems (2, 3, 4), each of which has an outer conductor (7, 8, 9) and at least one semiconductor component (12, 13), and a temperature monitoring device (15) that has multiple temperature sensors (16, 17, 18) which sense the temperature of at least one part of at least one of the phase systems (2, 3, 4). In said method, a temperature gradient is determined from each of the sensed temperatures, the difference of the determined temperature gradients from each other is ascertained, and if the difference exceeds at least one threshold value, a fault of a cooling device of the inverter (1) is identified. The invention further relates to an inverter (1).

Abstract: A power converter includes an inverter unit that includes a plurality of semiconductor switching elements constituting upper and lower arms and converts DC power into AC power; a gate driving unit that outputs, to the inverter unit, a gate signal used to drive gates of the plurality of semiconductor switching elements; a driving control unit that supplies the gate driving unit with a switching control signal used for the gate driving unit to output the gate signal; a first abnormality detection unit that performs over voltage detection of the DC power and over current detection of the AC power and temperature detection of the upper and lower arms; and a second abnormality detection unit that detects abnormality of the plurality of semiconductor switching elements of the upper arm and lower arms, wherein the driving control unit includes a first protection circuit and a second protection circuit.

Abstract: A power supply circuit is intended to suppress power consumption when a load is not driven and to shorten a required time to be taken until a boosted voltage to be supplied to a high-side MOS transistor is stabilized when the load is changed from a deactivated state to an activated state. The power supply circuit (power supply circuit 3) supplying power to a load driving circuit (motor driving circuit 2) that drives a load by controlling a high-side MOS transistor M1 on the basis of an input load control signal includes a booster circuit (charge pump 23) configured to boost a voltage of input power and supplies the power of which the voltage is boosted as power for driving the high-side MOS transistor. The booster circuit has power supply capability which varies depending on the load control signal.

Abstract: An operation control apparatus includes a criterion calculator that obtains an operation criterion for the power converter, based on the voltage detected by the above voltage detector on the side of the alternating-current power system, a direct-current voltage detector that detects a direct-current output voltage of the solar battery, and an operation determination device that compares the direct-current output voltage detected by the direct-current voltage detector with the operation criterion obtained by the criterion calculator, and supplies the power converter with an operation command if the direct-current output voltage is greater than the operation criterion.

Abstract: A power conversion apparatus includes a power converter and a PWM controller. A first switching element is coupled to a positive pole of a DC power source and one terminal of a load. A second switching element is coupled to a negative pole of the DC power source and another terminal of the load. A third switching element is coupled to the positive pole and the other terminal. A fourth switching element is coupled to the negative pole and the one terminal. The PWM controller PWM-controls the power conversion apparatus to repeat an on-period during which the DC power source outputs a voltage to the load and an off-period during which no voltage is output. The PWM controller alternately controls the first and second switching elements based on a signal set at a high or low level any time during a carrier wave period.

Abstract: A wireless power transmission device includes a power transmitter, a first transmission unit, a power receiver, a feedback regulator, a receive controller, and a second transmission unit. The power transmitter is for generating power, and the first transmission unit is for wirelessly transmitting power generated by the power transmitter. The power receiver is for receiving and rectifying the power from the first transmission unit. The feedback regulator is for receiving a feedback signal from the power receiver to generate an AC control signal. The receive controller is for receiving the control signal to generate a driving signal. The second transmission unit is for wirelessly transmitting the control signal to the receive controller.

Abstract: A power converter includes at least one leg with a first string including a plurality of controllable semiconductor switches, a first connecting node, and a second connecting node, wherein the first string is operatively coupled across a first bus and a second bus. The at least one leg also includes a second string operatively coupled to the first string via the first connecting node and the second connecting node, wherein the second string includes a plurality of switching units. The first string includes a first branch and a second branch, wherein the second branch is operatively coupled to the first branch via a third connecting node and the third connecting node is coupled to a ground connection.

Abstract: A power converter is presented. The power converter includes at least one leg, the at least one leg includes a first string, where the first string includes a plurality of controllable semiconductor switches, a first connecting node, and a second connecting node, and where the first string is operatively coupled across a first bus and a second bus. Furthermore, the at least one leg includes a second string operatively coupled to the first string via the first connecting node and the second connecting node, where the second string includes a plurality of switching units. A method for power conversion is also presented.

Abstract: A DC to AC conversion circuit including an inverter, a first inductor, a first capacitor, a second inductor and a second capacitor is provided. The inverter has two input contact points and two output contact points. The input contact points receive a DC signal, and the output contact points output an AC signal. The first terminal of the first inductor is coupled to one of the two output contact points. The first capacitor is coupled to the first inductor in parallel. The first terminal of the second capacitor is coupled to the second terminal of the first inductor, and the second terminal of the second capacitor is coupled to another one of two output contact points. The first terminal of the second inductor is coupled to the first terminal of the second capacitor, and the second terminal of the second inductor is coupled to a load.

Abstract: An electric power converter includes a stacked body in which a plurality of semiconductor modules and a plurality of coolers are stacked. Each of the semiconductor modules is provided with a main body that has semiconductor elements therein, a plurality of power terminals, and control terminals. Among the plurality of the power terminals respectively included in the two semiconductor modules adjoining in a stacking direction of the stacked body, at least parts of the power terminals are configured so as not to overlap each other when viewed from the stacking direction.

Abstract: An embodiment of the invention includes an analog associative memory, which includes an array of coupled voltage or current controlled oscillators, that matches patterns based on shifting frequencies away from a center frequency of the oscillators. The test and memorized patterns are programmed into the oscillators by varying the voltage or current that controls the oscillators. Matching patterns result in smaller shifts of frequencies and enable synchronization of oscillators. Non-matching patterns result in larger shifts and preclude synchronization of oscillators. In one embodiment the patterns each include binary data and the pattern matching is based on discrete shifts. In one embodiment the patterns each include grayscale data and the pattern matching is based on continuously-varied shifts. Other embodiments are described herein.

Abstract: A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates.

Abstract: Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.

Abstract: A method of storing data in a memory array with less than half of memory elements in any row and column in a low-resistance state. The data are arranged in a first portion of an encoding array. High-resistance values are entered in a second portion. A codeword is selected from a covering code for each row in which too many entries have low-resistance values. The selected codeword is used to reduce the number of low-resistance values in that row. A codeword is selected for each column in which too many entries have low-resistance values and the codeword is used to reduce the number of such values in that column. The process is repeated until no row and no column has too many low-resistance values. The array entries are stored in corresponding memory elements.

Abstract: A resistive switching device includes a first material layer between a first electrode and a second electrode. The first material layer has a first region and a second region parallel to the first region. The first region corresponds to a conducting path formed in the first material layer, and is configured to switch from a low-resistance state to a high-resistance state in response to an applied voltage that is greater than or equal to a first voltage. The second region is configured to switch to a first resistance value that is less than a resistance value of the first region in the high-resistance state when the applied voltage is greater than or equal to a second voltage. The first region remains constant or substantially constant when the second region has the first resistance value.

Abstract: A non-volatile variable resistive element according to an embodiment comprises a first electrode including a first metal, a second electrode including a second metal, a third electrode placed opposite to the first and second electrodes, and a variable resistive layer placed between the first and second electrodes and the third electrode, a resistance of the variable resistive layer reducing when at least either one of the first metal and the second metal is diffused into the variable resistive layer and the resistance of the variable resistive layer rising when at least either one of the first metal and the second metal diffused into the variable resistive layer is collected by the first electrode or the second electrode.

Abstract: The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.

Abstract: A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a reference voltage generation circuit which comprises at least the current steering element; a differential amplifier circuit which performs current amplification on an output voltage in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which sets the low voltage side reference voltage to increase with an output of the differential amplifier circuit; and a sense amplifier circuit which determines a resistance state of a selected memory cell according to an amount of current flowing through the selected memory cell.

Abstract: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.

Abstract: This invention relates generally to a memory cell. The embodiments of the present invention provide a SRAM cell and a SRAM cell array comprising such SRAM cell. The SRAM cell according to the embodiments of the present invention includes a pull-up transistor and a pull-down transistor, such that it is unnecessary to pre-charge a pre-read bit line at the time of performing read operation. By adopting the method of the present invention, generation of leakage current can be suppressed and hence power consumption of SRAM chip can be reduced.

Abstract: Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power.

Abstract: A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.

Abstract: Memory bandwidth management. In a two-level memory (2LM) system far memory bandwidth utilization at least a far memory is monitored and the available far memory bandwidth availability is dynamically modified based on monitored far memory bandwidth utilization. The operational state of at least one processing core is dynamically modified in response to modification of available far memory bandwidth.

Abstract: A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.

Abstract: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.

Abstract: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.

Abstract: The invention is to provide a method for programming and reading a flash memory, storing the last programming page in a block while programming the flash memory, judging the programming times in the cell of the block by means of the last programming page and the order and distribution of the page in the predefined page distribution list of the block while reading the flash memory, and selecting the predefined voltage based on the judged programming times to implement the reading process for raising reading performance.

Abstract: A method facilitates controlling a read time (tREAD) of an electronic memory device. The method includes implementing a first read time indicative of an array time for a read process for a memory array of the electronic memory device. The first read time relates to the time allocated to make data available at an I/O buffer of the electronic memory device for access by a controller. The method also includes implementing a second read time for the electronic memory device. The second read time has a total duration which is different from the first read time. In this way, different read times can be implemented for read operations at the same electronic memory device. The read times may be changed automatically based on one or more performance parameters (e.g., RBER, P/E count, etc.) of the electronic memory device.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Abstract: A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.

Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.