Abstract: A NAND flash memory includes a plurality of NAND flash memory structures separated by an insulating layer. In one embodiment of the present disclosure, the NAND flash memory structure includes a first bitline extending along a first direction, a first charge-trapping region positioned over the first bitline, a wordline positioned over the first charge-trapping region and extending along a second direction, a second charge-trapping region positioned over the wordline, and a second bitline positioned over the second charge-trapping region, wherein the first charge-trapping region and the second charge-trapping region are stacked along a third direction substantially perpendicular to the first direction and the second direction.

Abstract: A limiter circuit compares a voltage of a control gate line and a set voltage, thereby switching the logic of a flag signal. A booster circuit starts or stops its operation according to the logic of the flag signal. A leak reference circuit has a function of leaking a leak reference current from the control gate line. A counter generates a first count value by counting the number of times the flag signal logic changes in a condition that a word-line transfer transistor is rendered non-conductive and a leak reference circuit is driven, while the counter generates a second count value by counting the number of times the flag signal logic changes in a condition that the word-line transfer transistor is rendered conductive and the leak reference circuit is undriven. A comparator compares the first count value and the second count value.

Abstract: A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device has source/drain diffusion layers spaced from each other in a surface portion of a semiconductor substrate, a laminated insulating film formed on a channel between the source/drain diffusion layers and including a charge storage layer, and a gate electrode formed on the laminated insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the charge storage layer. The method includes, before injecting charges to change the data memory state into the charge storage layer: injecting charges having a polarity identical to that of the charges to be injected; and further injecting charges having a polarity opposite to that of the injected charges.

Abstract: A non-volatile memory device integrated in a chip of semiconductor material. An embodiment of a memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate.

Abstract: Approaches for operating a memory device comprising memory cells are disclosed. Optimal values for one or more of programming voltages used to program memory cells of the memory device and read reference voltages used to read the memory cells are determined using a mutual information function, I(X; Y), where X represents data values programmed to the memory cells and Y represents data values read from the memory cells. The read reference and/or programming voltages used for reading and/or programming the memory cells are adjusted using the optimal values.

Abstract: A flash memory controller, a computer readable medium and a method for generating reliability information using a hard information interface, the method may include performing multiple read attempts, while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and generating, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell.

Abstract: A method and system for performing wordline-to-wordline stress routines on a storage device is disclosed. Stress routines may be performed to reduce state widening in multi-level memory cells in the storage device. However, data retention problems may result if the stress routines are performed too often. In order to perform the stress routines at the proper times, a stress control variable is used. The stress control variable may be indicative of age of the storage device (such as the number of erase cycles performed on a memory block in the storage device). The stress control variable is input to a look-up table (or other logical construct), with the output of the look-up table indicating whether to perform the wordline-to-wordline stress routine. In this way, the stress routines may be performed to reduce state widening while reducing the ill effects of data retention.

Abstract: An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data lines in the plurality of data lines, and adapted to prevent voltage on the respective bit lines from overshooting a target level during a precharge interval. A bias circuit is coupled to the clamp transistors on the plurality of bit lines, and arranged to apply the bias voltage in at least two phases within a precharge interval, and to prevent overshoot of the target level on the bit line.

Abstract: The present invention provides circuits, systems, and methods for programming a floating gate. As described herein, a floating gate tunneling device is used with an analog comparison device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate or multiple floating gates.

Abstract: A memory column redundancy mechanism includes a memory having a number of data output ports each configured to output one data bit of a data element. The memory also includes a number of memory columns each connected to a corresponding respective data port. Each memory column includes a plurality of bit cells that are coupled to a corresponding sense amplifier that may differentially output a respective data bit from the plurality of bit cells on an output signal and a complemented output signal. The memory further includes an output selection unit that may select as the output data bit for a given data output port, one of the output signal of the sense amplifier associated with the given data output port or the complemented output signal of the sense amplifier associated with an adjacent data output port dependent upon a respective shift signal for each memory column.

Abstract: A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.

Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to bitlines associated with respective columns of the memory cells of the memory array. The sensing circuitry comprises, for at least a given one of the bitlines of the memory array, a sense amplifier configured to sense data on the given bitline, with the sense amplifier having at least one internal node and at least one output node. The sensing circuitry further comprises a latch circuit having a data input coupled to the output node and a control input coupled to the internal node, with the latch circuit being configured to latch sensed data from the output node responsive to a signal at the internal node.

Abstract: A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.

Abstract: A method of trimming a reference cell in a semiconductor memory device comprises the steps of: generating a reference current based on a bias voltage applied to the reference cell; generating a first current and a second current based on the value of a control voltage and the resistance of a precision resistor disposed outside the semiconductor memory device; comparing the reference current with the first current; comparing the reference current with the second current; programming the reference cell if the value of the reference current is greater than that of the first current; and erasing the reference cell if the value of the reference current is less than that of the second current. The value of the second current is less than that of the first current.

Abstract: A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.

Abstract: A semiconductor device includes a charge pump circuit that generates a first voltage during a first period and a second voltage during a second period following the first period by a boosting operation, a load current application circuit that includes a first memory cell, and that applies the first voltage to the first memory cell, a memory circuit that includes a second memory cell, and that applies the second voltage to the second memory cell; and a voltage detection circuit that monitors a value of the first voltage to determine whether or not the first voltage is increased to the predetermined voltage, wherein the charge pump circuit stops the boosting operation if the first voltage is less than the predetermined voltage at an end of the first period.

Abstract: A method of performing write operations in a memory device including a plurality of bank is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

Abstract: A semiconductor apparatus includes a memory block configured to have a normal cell array and a redundancy cell array; a column address buffer configured to compare a plurality of input column addresses with a fail column address signal-stored in a fuse array, and generate a column enable signal or a fail column enable signal; a column decoder configured to decode the column enable signal, and output a column selection signal to the normal cell array; and a column redundancy controller configured to generate a redundancy control signal in response to the fail column enable signal, generate a redundancy enable signal so as to reuse a redundancy bit line which has been substituted before according to the generated redundancy control signal, and output the generated redundancy enable signal to the redundancy cell array.

Abstract: A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.

Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier.

Abstract: A sense amplifier comprising a reference current developed from a programmed and a non-programmed reference cell is used to read a signal from a magnetic random access memory (MRAM) comprising magnetic tunnel junction (MTJ) cells. The average current is determined from reference cells in as few as one sense amplifier and as many as n sense amplifiers, and is an average current between the programmed reference cell and the non-programmed reference cell that approximates the mid point between the two states. The sense amplifier can be fully differential or a non differential sense amplifier.

Abstract: Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.

Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.

Abstract: The present invention discloses a power supply. The power supply may comprise an input power terminal, a capacitor module, a first converter module and a second converter module. The first converter module may have a first terminal and a second terminal, wherein the first terminal is coupled to the input power terminal and the second terminal is coupled to the capacitor module. The second converter module may comprise an input and an output, wherein the input of the second converter module is coupled to the input power terminal, and the output of the second converter module is configured to supply a load.

Abstract: Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected one or ones of the memory banks is brought into an active state in response to the active signal. Each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state. The first chip activates a bank active signal when at least one of the local bank active signals is activated.

Abstract: Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines.

Abstract: A system includes a memory block and a controller. The controller is adapted to skew a pre-charge signal for a bit line of the memory block. The controller can skew the pre-charge signal during a read operation or a write operation. The system can also include a sense amplifier in communication with a bit line of the memory block, and the sense amplifier can automatically shut off after indicating a sensed data state for the bit line. The controller may be a global controller or a local controller.

Abstract: An ultrasonic diagnostic apparatus provided with an ultrasonic image measuring unit configured to measure an ultrasonic image of an object to be examined, a display unit configured to display the ultrasonic image, an input unit configured to input parameters for controlling the ultrasonic image measuring unit and the display unit, and a control unit configured to control the ultrasonic image measuring unit and the display unit by means of the parameters. The control unit is characterized by generating first switch information for inputting relating to a first control parameter included in the parameters, controlling the display unit to display the first switch information, selecting the first control parameter from the first switch information and inputting thereof, generating second switch information relating to a second control parameter which is the item next to the first control parameter, and controlling the display unit to display the second switch information.

Abstract: An elongate body for parenteral injection at low velocity from a device is described. The body has at least one pointed end and comprises at least one active material. In addition, the body has a compressive strength of greater than or equal to 5 Newton and the pointed end has an included angle of between about 10-50°. A solid vaccine formulation for needle-free parenteral delivery, methods for making the body, packaging of the body and use of the body, packaging and suitable delivery device are also described.

Abstract: A technique includes receiving seismic data acquired by seismic sensors; and processing the seismic data on a machine to deghost the data. The processing includes deghosting the seismic data using a first deghosting technique that relies on a ghost model; deghosting the seismic data using a second deghosting technique that is independent from any modeling of the ghost; and selectively combining the results of the deghosting using the first and second deghosting techniques.

Abstract: The invention is a method of calculating seismic time shifts ?{right arrow over (t)}(t), comprising: conducting a number (n) of three or more seismic surveys with large time differences such as months or years, producing a number (n) of three or more vintages of seismic data d1(t), d2(t), . . .

Abstract: An apparatus for creating pressure pulses in the fluid of a bore hole is described. The preferred embodiment takes the form of a mud pulser apparatus having a signalling valve controlled by a variable pilot valve. The forces on the signalling valve are balanced and controlled by the flow of mud through the variable orifice of the pilot valve. The arrangement is such as to act like a hydraulic amplifier, and results in the signalling valve being compensated for variable flow rates. In the preferred embodiment, the pilot valve has rotary vanes that allow it to be self-cleaning.

Abstract: Disclosed are a sound generation system, an ultrasonic wave emitting device, and an ultrasonic wave emitting method which utilize the principle of parametric speakers (which uses the difference between frequencies of two ultrasonic waves) and which are capable of allowing target persons in a prescribed area to hear a sound only when a mobile body approaches said prescribed area. An alert system (10) has an ultrasonic wave emitting device (100) mounted on a mobile body (200), and an ultrasonic wave emitting device (300) permanently installed near an area (A101). The ultrasonic wave emitting device (300) emits a first ultrasonic wave towards an area at least including the aforementioned area (A101), and meanwhile, the ultrasonic wave emitting device (100) emits a second ultrasonic wave. The ultrasonic emitting device (100) forms the second ultrasonic wave by means of modulating the ultrasonic wave of frequency f1 with an audible signal.

Abstract: A position measurement apparatus and methodology is provided. Embodiments include a probe including an acoustic signal source, an optical signal source, and a probe processor for driving the signal sources such that the signals of the acoustic source and the optical source have a known temporal relationship to each other. A receiver receives the optical and acoustic signals, and a processor communicates with and controls the probe and the receiver, and processes data from the receiver. The acoustic signal source is a sinusoidally varying acoustic energy source, and the acoustic signal received by the receiver comprises a sinusoidal signal. The processor correlates the received sinusoidal signal to a mathematical reference sinusoidal signal, and determines a specific cycle and a specific phase as a time of flight measurement point based on the correlation.

Abstract: A sound direction estimation apparatus includes a sound source model storage unit that stores likelihood of a sound source class in correspondence with a sound feature quantity, a sound signal input unit that receives a sound signal, a sound source identification unit that identifies a sound source class of the sound signal input from the sound signal input unit with reference to the sound source model storage unit based on the sound feature quantity of the sound signal, and a first sound source localization unit that estimates a sound direction of the sound signal of the sound source class identified by the sound source identification unit.

Abstract: A method is provided for characterizing data sets containing data points. The method can characterize the data sets as random or as non-random. In the method, a convex hull envelope is constructed which contains the data points and passes through at least four non-coplanar data points. The convex hull envelope is partitioned into cells. The method classifies the data set as a sized sample. Based on the classification, a predetermined set of tests is selected for operating on the data set.

Abstract: A timepiece device with multiple-hand includes: one or more hands driven to rotate by one or more driving motors; one or more gear train mechanisms include gears which transmit a rotation movement of the driving motors to the hands; and a support plate which supports the gears; wherein the gears include: a first gear which includes a pair of gear members provided on front and rear sides of the support plate; a second gear which meshes with a gear member provided on the rear side to transmit a rotation movement of one of the driving motors to the first gear; and a third gear which meshes with a gear member provided on the front side to transmit a rotation movement of one of the driving motors to the hands.

Abstract: A wristwatch is provided with hand(s) and a disk-shaped indicating member disposed between a first dial and a second dial. The disk-shaped indicating member is structured such that a part of the disk-shaped indicating member is exposed from an opening portion of the first dial and that the disk-shaped indicating member indicates, at a region corresponding to the opening portion, one of a plurality of function display portions SPL, STP and RUN provided on the second dial. The hand(s) and the disk-shaped indicating member rotate about a common driving shaft.

Abstract: In the conventional clock, it is difficult to instantly grasp the additional information upon looking at the time and the information is not efficiently utilized. The clock is not popular among people of all ages.

Abstract: The electronic timepiece has an external case; a time indicating section that indicates the time; a solar panel; and a battery housing section that is provided in a main plate, a positive side contact terminal that is electrically connected to a positive supply terminal of the indication controlling section and configured such that the positive side contact terminal can be brought into contact with a positive terminal of a battery housed in the battery housing section; a negative side contact terminal that is electrically connected to a negative supply terminal of the indication controlling section and configured such that the negative side contact terminal can be brought into contact with a negative terminal of a battery housed in the battery housing section; and a contact section is positioned such that the contact section is not in contact with a battery housed in the battery housing section.

Abstract: A watch for providing a digital time display comprises a movement mechanism disposed in a case that includes a number of continuous belts. The belts each have a numerical indicia consistent with hours, minutes and optionally second. The belts mounted over opposed drums, and the drums are rotated through gear engagement motors to move the belts. The arrangement of belts and drums are mounted on a frame separate from the case. The motors are operated to move the belts to cause the numerical indicia of the combined belts to register with one or more windows visible through a transparent cover to provide a time display. The belts may be oriented to overlap one another. The watch includes a microcontroller for controlling the operation of the motors, an optical sensor to determining the position of the belts, and a wirelessly rechargeable battery pack for powering the motors.

Abstract: A vibratory alarm assembly includes a cover that may be positioned on a mattress. A vibrator pocket is coupled to the cover. A controller pocket coupled to the cover. A vibrating member is positionable within the vibrator pocket. A controller is positionable within the controller pocket. The controller has a housing. The controller is operationally coupled to the vibrating member. A processor is coupled to the housing. An alarm is coupled to the housing. The alarm is operationally coupled to the processor. A microphone is coupled to the housing. The microphone is operationally coupled to the processor. A power supply is coupled to the housing.

Abstract: When using an optical disc medium that includes pit trains having their widths narrower than a diffraction limit, it is difficult to detect a tracking error signal and take a tracking-servo control while increasing pit density in a direction orthogonal to a pit-train extension direction. Information pit trains are arranged spirally or concentrically and formed in a structure in which their depths are changed periodically at a pitch radially along the optical disc medium, so that the tracking error signal can be obtained by push-pull detection of diffraction light from the structure.

Abstract: A digital loop filter receives a phase error output from a phase comparator to generate a digital frequency value. This digital frequency value is converted into an analog voltage by a D/A converter, and VCO outputs a synchronizing dock of frequency corresponding to the voltage output from the D/A converter. The phase error output from a phase comparator is gain-corrected by a product of an output from the digital loop filter and a specific coefficient “A”, and delivered to digital loop filter. The phase error input to the digital loop filter is changed in proportion to the output clock frequency, whereby the PLL loop as whole linearly controls the loop characteristic depending on the output clock frequency.

Abstract: Noise generation in transferring data is suppressed or prevented by transferring data at a data transfer rate according to the amount of data to be transferred to a memory. In a reproducing apparatus, when a read unit or both reads data from a storage medium or both, a determination unit determines the type of the storage medium from which the data is read, then, according to the determined type of the storage medium, a transfer rate change unit orders a data transfer unit to use a preset transfer rate corresponding to the type of the storage medium. The data transfer unit transfers the read data to the temporary storage unit at the ordered transfer rate. This allows data to be transferred without a significant change in the amount of data transfer, which suppresses or prevents noise.

Abstract: A recording apparatus includes: a light illumination and light sensing unit configured to illuminate an optical disc recording medium including a reference surface having address information recorded and a recording layer, with recording light and light for position control; a recording unit which performs recording on the recording layer; and a control unit which controls, when data instructed to be recorded is to be recorded from an instructed recording start address, the recording unit to perform recording of dummy data on an area adjacent to a front side at least from the recording start address over a range of equal to or greater than the maximum spot deviation amount between an illumination spot of the light for position control and an illumination spot of the recording light and to perform recording of the data instructed to be recorded in succession to a recorded area of the dummy data.

Abstract: A media processing system that produces discs with assured quality suited to long-term data storage. A data write unit writes data on a recording surface of a disc. A label print unit prints on the label side of the disc. An error rate measurement unit measures the error rate of the disc D after writing data is completed. An error rate evaluation unit determines if the media error rate measured by the error rate measurement unit is less than or equal to a preset threshold value. When the error rate evaluation unit determines that the media error rate is less than or equal to the threshold value, the label print unit prints a label image on the label side.

Abstract: A system includes a position detection module configured to detect at least a first position indicator and a second position indicator corresponding to a label side of an optical disc. A write clock adjustment module is configured to determine a number of cycles of a write clock that occur between the first position indicator and the second position indicator, determine a difference between the number of cycles of the write clock and a desired number of cycles of the write clock, and adjust a frequency of the write clock based on the difference.

Abstract: A high data density optical recording medium, a method and an apparatus for reading such an optical recording medium, and a method for mastering such an optical recording medium are proposed. For achieving a high data density the optical recording medium has marks that have a tip and are covered by a material that generates a detectable effect under the influence of high electric fields.

Abstract: The present invention relates to a format of a recordable optical recording medium, which is designed in such a way that it can be read by any standard player and recorder. The optical recording medium has a recording layer with a structure of lands and grooves, which generates a strong push-pull signal in an area of the recording layer without recorded marks and a small push-pull signal in an area of the recording layer with recorded marks.