Patents Issued in April 8, 2014
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Patent number: 8693203Abstract: A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.Type: GrantFiled: January 14, 2011Date of Patent: April 8, 2014Assignee: Harris CorporationInventors: Louis Joseph Rendek, Jr., Michael Weatherspoon, Casey Philip Rodriguez, David Nicol
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Patent number: 8693204Abstract: Multi-purpose cowling structures are provided to minimize spacing impact within an electronic device, while maximizing functional utility. In one embodiment, an electromagnetic interference shield may provide one or more anchors for enabling a logic board cowling to apply sufficient downward force to one or more board connectors to prevent inadvertent disconnects. In another embodiment, a cowling can electrically connect the ground plane of a logic board to the ground plane of a housing member and provide a pre-load force to a conductor connection existing on logic board. A compass mounted on a flexible printed circuit board is also provided. Mounting the compass on a flexible printed circuit board enables the compass to be mounted remote from ferrous object that may affect the compass's performance.Type: GrantFiled: January 10, 2011Date of Patent: April 8, 2014Assignee: Apple Inc.Inventors: Shayan Malek, Jared Kole, Nikko Lubinski
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Patent number: 8693205Abstract: A control unit is provided and a method for assembling such a control unit for a personal protection device for a vehicle. A circuit board is installed between a plastic cover and a plastic floor. An interface is positioned on the circuit board, for an electrical connection to at least one additional vehicle component. At least one opening is provided in the plastic cover for the electrical connection.Type: GrantFiled: May 4, 2009Date of Patent: April 8, 2014Assignee: Robert Bosch GmbHInventors: Manfred Moser, Mark Wonner, Roland Cupal
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Patent number: 8693206Abstract: Described are external storage devices including a substrate, a controller electrically coupled to the substrate, at least one memory die stack electrically coupled to the substrate, a plurality of connection fingers electrically coupled to the substrate, and a mounting bar electrically coupled to the substrate. The mounting bar may include a plurality of springs. In other examples, the external storage device may include a substrate, a controller electrically coupled to the substrate, at least one memory die stack electrically coupled to the substrate, a plurality of connection fingers electrically coupled to the substrate, and a contact bar electrically coupled to the substrate. The contact bar may include a plurality of extensions. One or more memory die stacks may be coupled to one or more surfaces of the substrate and may include a plurality of dies in each memory die stack.Type: GrantFiled: February 1, 2013Date of Patent: April 8, 2014Inventor: Martin Kuster
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Patent number: 8693207Abstract: A rotatable transfer apparatus includes a housing and a circuit board having at least two interfaces. The housing includes a top cover, a sidewall, a bottom board and an elastic module. The top cover is rotatably mounted at one side of the sidewall. The bottom board is mounted at the other side of the sidewall opposite to the top cover. The sidewall, the bottom board and the top cover define a receiving space for receiving the circuit board. The sidewall includes an opening, and at least two fasteners defined in an internal surface of the sidewall. The elastic module is received in the receiving space and fixed to the top cover. The elastic module rotates with the top cover and detachably engaged with one of the at least two fasteners to select a desired interface to be exposed to the opening.Type: GrantFiled: September 30, 2011Date of Patent: April 8, 2014Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Xin Yang, Wei Wu
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Patent number: 8693208Abstract: A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port.Type: GrantFiled: August 8, 2011Date of Patent: April 8, 2014Assignee: OCZ Technology Group, Inc.Inventors: Karl Reinke, Dokyun Kim, William Allen
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Patent number: 8693209Abstract: A wiring board includes a substrate having an opening portion, multiple electronic devices positioned in the opening portion, and an insulation layer formed on the substrate such that the insulation layer covers the electronic devices in the opening portion of the substrate. The substrate has a wall surface defining the opening portion and formed such that the opening portion is partially partitioned and the electronic devices are kept from making contact with each other.Type: GrantFiled: April 25, 2012Date of Patent: April 8, 2014Assignee: Ibiden Co., Ltd.Inventors: Yukinobu Mikado, Mitsuhiro Tomikawa, Yusuke Tanaka, Toshiki Furutani
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Patent number: 8693210Abstract: A method of fabricating packaging for a product comprises forming a plurality of conductive tracks on a sheet of material and forming a physical barrier, such as a hole, for impeding fluid flow between adjacent conductive tracks. The method may further comprise depositing first and second regions conductive fluid onto adjacent first and second conductive tracks either side of the physical barrier and mounting an electronic device having first and second terminals such that the electronic device forms a bridge over the physical barrier and the first ands second terminals contact the first and second conductive adjacent tracks.Type: GrantFiled: October 17, 2008Date of Patent: April 8, 2014Assignee: Novalia Ltd.Inventor: Kate Stone
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Patent number: 8693211Abstract: A wiring substrate 11 includes a wiring substrate main body 31 having a semiconductor element mounting area A, a wiring pattern 33 provided on an upper surface 31A of the wiring substrate main body 31 at a portion corresponding to the semiconductor element mounting area A, a solder resist 35 provided on the upper surface 31A of the wiring substrate main body 31 and having an opening portion 43 whose size is substantially equal to the semiconductor element mounting area A when viewed from a top, and a dam 37 provided on the solder resist 35 to block an underfill resin 13 provided in a clearance between the semiconductor element 12 and the wiring substrate main body 31. A distance between an inner wall of the opening portion 43 of the solder resist 35 and an inner wall of the dam 37 is partially varied.Type: GrantFiled: January 24, 2012Date of Patent: April 8, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventor: Yuka Tamadate
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Patent number: 8693212Abstract: A chassis having a cover moveable between open and closed positions and circuitry for detecting whether the cover is in the open or the closed position. The circuitry includes a transmitter of optical energy disposed at a fixed position within the chassis for transmitting pulses of optical energy at a predetermined frequency and a receiver for optical energy disposed at a fixed position within the chassis. A reflector is mounted to an inner surface of the cover and is disposed in a path to intercept and then reflect the intercepted transmitted energy to the receiver when the cover is moved to the closed position and being disposed away from the path to prevent the transmitted energy to be intercepted and then reflected to the receiver when the cover is moved to the open position.Type: GrantFiled: September 15, 2010Date of Patent: April 8, 2014Assignee: EMC CorporationInventors: Brian D. Kennedy, Antonio L. Fontes
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Patent number: 8693213Abstract: An AC-to-DC power converter configured to provide power factor correction and a single isolated low-voltage output. The power converter includes a single-stage resonant power converter including an isolation transformer, a resonant tank, a rectifier, and a bulk storage capacitor coupled to an output of the isolation transformer. In typical applications, at least one non-isolated power converter is coupled to the output of the single-stage isolated power factor correction converter.Type: GrantFiled: May 21, 2008Date of Patent: April 8, 2014Assignee: Flextronics AP, LLCInventors: Aaron Jungreis, Paul Garrity
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Patent number: 8693214Abstract: A voltage converter (1a . . . 1g), in particular a resonant converter for converting an input AC or DC voltage (UE) into an output DC voltage (UA). On the secondary side, a first secondary capacitor (CS1) is arranged between the secondary partial windings (WS1, WS2) of a transformer (TR1); furthermore, a first secondary full-bridge rectifier (GS1) provides the output direct voltage (UA), the inputs of which are connected to a secondary partial winding (WS1, WS2) each of the transformer (TR1), resulting, at the input of the first secondary full-bridge rectifier (GS1), in a series connection including the secondary partial windings (WS1, WS2) and the first secondary capacitor (CS1). Finally, the voltage converter (1a . . .Type: GrantFiled: June 28, 2011Date of Patent: April 8, 2014Assignee: BRUSA Elektronik AGInventor: Axel Krause
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Patent number: 8693215Abstract: A DC/DC converter may include a power stage circuit, a pulse generator circuit, a flux density monitor, and power control logic. The power stage circuit includes an input, an output, and a transformer with a core. The power stage circuit may be configured to operate in a power transfer phase during which power is transferred from the input to the output and a reset phase during which flux density in the core of the transformer is reduced. The pulse generator circuit may be configured to generate pulses that regulate the output of the power stage circuit. The flux density monitor circuit may be configured to generate flux density information indicative of the flux density of the core of the transformer during both the power transfer phase and the reset phase. The power stage control logic may be configured to regulate the output of the power stage circuit based on the pulses and to prevent the core of the transformer from saturating based on the flux density information.Type: GrantFiled: June 2, 2011Date of Patent: April 8, 2014Assignee: Linear Technology CorporationInventors: William Hall Coley, Charles Edward Hawkes, Kurk David Mathews
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Patent number: 8693216Abstract: The present invention relates to a switch control device, a power supply device, and a switch control method. A switch control device controls a switching operation of a power switch by using a feedback voltage of an output voltage. In detail, the switch control device generates the feedback current according to the feedback voltage and the feedback signal corresponding to the feedback voltage by using the feedback current. The switch control device compares the sensing signal corresponding to the drain current flowing to the power switch and the feedback signal, and turns off the power switch according to the comparison result. The switch control device increases the feedback gain rather than the feedback current during the gain compensation period after a predetermined gain compensation period, and the gain compensation period is longer than a soft start period in which the output voltage is gradually increased.Type: GrantFiled: February 15, 2011Date of Patent: April 8, 2014Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Sang Cheol Moon, Hyun-Chul Eom, Kwang-Il Lee
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Patent number: 8693217Abstract: An example power supply controller includes a signal separator circuit that generates a feedback signal. An error signal generator generates an error signal in response to the feedback signal. A control circuit generates a drive signal in response to the error signal. The drive signal controls switching of a switch. A multi-cycle modulation circuit is included in the control circuit and generates a skip signal in response to a start skip signal, a stop skip signal and a skip mask signal. The skip mask signal is generated in response to the skip signal. The start skip and stop skip signals cause the drive signal to start skipping or stop skipping, respectively, on-time intervals of cycles. The skip mask signal disables the start skip signal from causing the drive signal to start skipping the on-time intervals of cycles.Type: GrantFiled: September 23, 2011Date of Patent: April 8, 2014Assignee: Power Integrations, Inc.Inventor: Mingming Mao
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Patent number: 8693218Abstract: A power adapter comprises a main power circuit, a feedback circuit, an ID detection circuit and a switch controller. The feedback circuit is coupled to the main power circuit for detecting the DC output voltage and issuing a feedback signal. The ID detection circuit is coupled to the feedback circuit for detecting an ID signal from the DC-powered electronic device and issuing a control signal to the feedback circuit to disable or delay the feedback signal for a specific time period, and comparing a dropping slew rate of the DC output voltage with a preset value to issue a hiccup mode control signal. The switch controller is configured for controlling the operations of the main power circuit in response to the feedback signal and controlling the power adapter to operate in a normal operation mode or a hiccup mode in response to the hiccup mode control signal.Type: GrantFiled: September 26, 2011Date of Patent: April 8, 2014Assignee: Delta Electronics, Inc.Inventors: Hung-Wen Chueh, Teng-Ping Lin
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Patent number: 8693219Abstract: A power factor improvement circuit includes a low frequency filter unit installed between two electrodes of an output terminal of a rectifier unit for adjusting voltage and current inputted to a PWM control IC in-phase, and first and second compensation circuits installed at a current compensation terminal and a voltage compensation terminal of the PWM control IC respectively, and the first and second compensation circuits are provided for reducing the current gain of the phase adjustment unit to avoid any unnecessary action of the PWM control IC, so as to achieve the effect of controlling a power factor to a level over 0.90 when a full voltage of 90-264V is inputted.Type: GrantFiled: October 21, 2011Date of Patent: April 8, 2014Assignees: Wafly Ltd.Inventor: Jui-Chih Yen
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Patent number: 8693220Abstract: A system for improving wind turbine generator performance is disclosed. In one aspect a rotary power generation system is provided, including: a rotary power generator for generating variable-frequency alternating currents; a negative sequence current regulator that determines and uses frequency-dependent D-axis and Q-axis negative sequence gains based on an electrical frequency of the rotary power generator; and a system for controlling voltage components for balancing the variable-frequency alternating currents generated by the rotary power generator based on the selected D-axis and Q-axis negative sequence gains.Type: GrantFiled: October 26, 2011Date of Patent: April 8, 2014Assignee: General Electric CompanyInventors: Anthony Michael Klodowski, Sidney Allen Barker
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Patent number: 8693221Abstract: An electric power converter apparatus includes an inverter circuit having a plurality of upper arm elements and a plurality of lower arm elements, a feedback controlling module calculating a voltage command value in order to control an output from the inverter circuit in a feedback control manner and a compensating module compensating the voltage command value with a compensation amount and outputting a compensated voltage command value. Each of the plurality of upper arm elements and the plurality of lower arm elements is operated to switch over based on a control signal that is set according to the compensated voltage command value and a dead time. The compensation amount is set by the compensating module in order to compensate a fluctuation in the output current due to the dead time.Type: GrantFiled: November 1, 2011Date of Patent: April 8, 2014Assignees: Denso Corporation, Nippon Soken, Inc.Inventors: Kenji Ochi, Fumio Asakura, Hiroshi Yoshida
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Patent number: 8693222Abstract: A DC-DC converter includes a first winding of a first transformer to which direct current power is supplied, a switching element configured to be connected in series with the first winding of the first transformer, a first winding of a second transformer and a capacitor configured to be connected in series with each other and in parallel with the switching element, a second winding of the first transformer configured to be coupled with the first winding of the first transformer, output terminals configured to be connected to the second winding of the first transformer and to output direct current power, and a pair of second windings of the second transformer configured to be coupled with the first winding of the second transformer, the second windings of the second transformer being connected in parallel with each other with reverse polarity between the output terminals.Type: GrantFiled: November 29, 2011Date of Patent: April 8, 2014Assignee: Fujitsu LimitedInventors: Yu Yonezawa, Yoshiyasu Nakashima
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Patent number: 8693223Abstract: A power converter includes an output unit, a first transformer, a switch unit, and a processing unit. The first transformer includes a primary winding and a secondary winding. The primary winding is coupled between an input voltage and a first node. The switch unit is coupled between the first node and a second node. The processing unit is coupled between the input voltage and the first node. When the switch unit is in an OFF state, the processing unit is used to receive a first sensing voltage and store a sensing power of the first sensing voltage through a first path, isolate the first sensing voltage from feeding in through a second path different from the first path simultaneously, and then release the stored sensing power through the second path. The first sensing voltage is generated as the switch unit switches from an ON state to the OFF state.Type: GrantFiled: February 22, 2012Date of Patent: April 8, 2014Assignee: FSP Technology Inc.Inventor: Cody Lin
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Patent number: 8693224Abstract: A cascade multiplier includes a switch network having switching elements, a phase pump, and a network of pump capacitors coupled with the phase pump and to the switch network. The network of pump capacitors includes first and second capacitors, both of which have one terminal DC coupled with the phase pump, and a third capacitor coupled with the phase pump through the first capacitor.Type: GrantFiled: November 26, 2012Date of Patent: April 8, 2014Assignee: Arctic Sand Technologies Inc.Inventor: David Giuliano
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Patent number: 8693225Abstract: An electric load driving circuit for driving an electric load having a capacity component includes a plurality of power sources generating different voltages, capacitors provided parallel to the plurality of power sources, a switch control unit that switches connections between the capacitors and the electric load and thereby switching a voltage applied to the electric load, discharge paths that enable discharging electric charge stored in the capacitor, and a discharge control unit that controls a quantity of electric charge discharged from the discharge paths.Type: GrantFiled: October 26, 2009Date of Patent: April 8, 2014Assignee: Seiko Epson CorporationInventors: Hiroyuki Yoshino, Nobuaki Azami, Shinichi Miyazaki, Kunio Tabata, Atsushi Oshima, Noritaka Ide
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Patent number: 8693226Abstract: An inverter comprising: a circuit including arms connected in parallel, each of the arms including a first switch and a second switch connected in series; and a gate drive circuit configured to control, by pulse-width modulation using synchronous rectification, each of the first switch and the second switch to switch to an on-state or an off-state, wherein each of the first switch and the second switch includes: a channel region that is conductive in both a forward direction and a reverse direction in the on-state, and that is not conductive in the forward direction in the off-state; and a diode region that is combined as one with the channel region, and that is conductive only in the reverse direction, the diode region being unipolar, and the gate drive circuit synchronizes a timing at which the gate drive circuit outputs a signal for causing the first switch to switch to the on-state with a timing at which the gate drive circuit outputs a signal for causing the second switch to switch to the off-state, andType: GrantFiled: October 28, 2011Date of Patent: April 8, 2014Assignee: Panasonic CorporationInventors: Makoto Kitabatake, Shun Kazama
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Patent number: 8693227Abstract: An inverter controller comprising a current regulator unit, a voltage regulator unit coupled to the current regulator unit, an inverter unit coupled to the voltage regulator unit, and a drive unit controlled by the inverter unit.Type: GrantFiled: September 19, 2011Date of Patent: April 8, 2014Assignee: DRS Power & Control Technologies, Inc.Inventors: David J. Gritter, James Ulrich
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Patent number: 8693228Abstract: A power transfer system provides power factor conditioning of the generated power. Power is received from a local power source, converted to usable AC power, and the power factor is conditioned to a desired value. The desired value may be a power factor at or near unity, or the desired power factor may be in response to conditions of the power grid, a tariff established, and/or determinations made remotely to the local power source. Many sources and power transfer systems can be put together and controlled as a power source farm to deliver power to the grid having a specific power factor characteristic. The farm may be a grouping of multiple local customer premises. AC power can also be conditioned prior to use by an AC to DC power supply for more efficient DC power conversion.Type: GrantFiled: February 18, 2010Date of Patent: April 8, 2014Inventors: Stefan Matan, William B. Westbrock, Jr., Fred C. Horton, Joseph M. Klemm, Frank P. Marrone, Arnold F. McKinley, Kurt W. Wiseman
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Patent number: 8693229Abstract: A power regeneration apparatus includes a power conversion unit, an AC reactor, a voltage detecting unit, a phase detecting unit, a drive control unit for controlling the power conversion unit based on a phase detection value, and a reactive current component detecting unit. The phase detecting unit detects the phase of the AC power supply. The reactive current component detecting unit detects a reactive current component of a current. The drive control unit includes a phase correction section. The phase correction section corrects the phase detection value based on the reactive current component.Type: GrantFiled: April 9, 2013Date of Patent: April 8, 2014Assignee: Kabushiki Kaisha Yaskawa DenkiInventors: Takahiro Saeki, Hideaki Iura, Shoji Konakahara
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Patent number: 8693230Abstract: Disclosed herein is a device that includes a plurality of stacked core chips and an interface chip that controls the core chips. Each of the core chips includes a memory cell array, a penetration electrode, and an output circuit that outputs read data that are read from the memory cell array to the penetration electrode. The penetration electrode respectively provided in the core chips are commonly connected with each other, and the output circuits respectively provided in the core chips are activated in response to a read clock signal supplied from the interface chip.Type: GrantFiled: March 30, 2012Date of Patent: April 8, 2014Assignee: Elpida Memory, Inc.Inventor: Chikara Kondo
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Patent number: 8693231Abstract: A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.Type: GrantFiled: June 13, 2012Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: Akira Goda, Seiichi Aritome
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Patent number: 8693232Abstract: A non-volatile memory cell including a resistivity change material configured to reversibly change state between at least two stable states having different electrical resistances and conformed such that transformation from one state to another is obtained by controlling the temperature increase or decrease of the resistivity change material, wherein the resistivity change material has an ohmic component Ron-mat defined by the ratio between an increment in the programming voltage Vprog causing an increment in a programming current Iprog, wherein the resistivity change material has a non-ohmic component defined by a maintenance voltage Vh such that Vh is greater than zero when the programming voltage Iprog passes through the resistivity change material (22); and greater than an ohmic voltage equal to Ron-mat×Iprog.Type: GrantFiled: June 3, 2011Date of Patent: April 8, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Luca Perniola, Stefania Braga
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Patent number: 8693233Abstract: A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.Type: GrantFiled: January 31, 2012Date of Patent: April 8, 2014Assignee: SanDisk 3D LLCInventors: Roy E Scheuerlein, Henry Chien, Zhida Lan, Yung-Tin Chen
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Patent number: 8693234Abstract: A memory unit includes memory elements and a drive section. In executing a first operation out of the first operation for changing resistance state of the memory element from one resistance state out of low resistance state and high resistance state to the other resistance state and a second operation for changing the resistance state of the memory element from the other resistance state to the one resistance state, the drive section performs stepwise operation, in which the drive section repeatedly performs, at least one time, a step in which strong stress application step for applying a stress for performing the first operation to the memory element as the drive target relatively strongly is performed and subsequently weak stress application step for applying a stress for performing the second operation to the memory element as the drive target relatively weakly is performed, and subsequently performs the strong stress application step.Type: GrantFiled: February 1, 2012Date of Patent: April 8, 2014Assignee: Sony CorporationInventor: Motonari Honda
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Patent number: 8693235Abstract: Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.Type: GrantFiled: December 6, 2011Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon-Jhy Liaw
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Patent number: 8693236Abstract: A hierarchical sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line in hierarchy, and associated systems and methods are described. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line, and wherein the sectioned bit lines are arranged in hierarchical arrays. In other implementations, a hierarchical SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.Type: GrantFiled: February 17, 2012Date of Patent: April 8, 2014Assignee: GSI Technology, Inc.Inventors: LeeLean Shu, Chenming W. Tung, Hsin You S. Lee
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Patent number: 8693237Abstract: A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.Type: GrantFiled: July 31, 2012Date of Patent: April 8, 2014Assignee: National Chiao Tung UniversityInventors: Shyh-Jye Jou, Jhih-Yu Lin, Ching-Te Chuang, Ming-Hsien Tu, Yi-Wei Chiu
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Patent number: 8693238Abstract: An MRAM of a spin transfer type is provided with a memory cell 10 and a word driver 30. The memory cell 10 has a magnetic resistance element 1 and a selection transistor TR having one of source/drain electrodes which is connected with one end of the magnetic resistance element 1. The word driver 30 drives a word line WL connected with a gate electrode of the selection transistor TR. The word driver 30 changes a drive voltage of the word line WL according to the write data DW to be written in the magnetic resistance element 1.Type: GrantFiled: July 13, 2007Date of Patent: April 8, 2014Assignee: NEC CorporationInventors: Noboru Sakimura, Takeshi Honda, Tadahiko Sugibayashi
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Patent number: 8693239Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein the memory layer has a lamination structure of a Co—Fe—B layer and an element belonging to any one of 1A group, 2A group, 3A group, 5A group, or 6A group, an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed with respect to the memory layer, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer.Type: GrantFiled: September 7, 2011Date of Patent: April 8, 2014Assignee: Sony CorporationInventors: Masanori Hosomi, Kazuhiro Bessho, Hiroyuki Ohmori, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
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Patent number: 8693240Abstract: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current therethrough. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ therethrough for small time intervals thereby avoiding read disturbance to the MTJ.Type: GrantFiled: November 28, 2012Date of Patent: April 8, 2014Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Patent number: 8693241Abstract: A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.Type: GrantFiled: September 23, 2011Date of Patent: April 8, 2014Assignee: SK Hynix Inc.Inventors: Myoung Sub Kim, Soo Gil Kim, Nam Kyun Park, Sung Cheoul Kim, Gap Sok Do, Joon Seop Sim, Hyun Jeong Lee
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Patent number: 8693242Abstract: A nanoelectromechanical device is provided. The nanoelectromechanical device includes a nanotube, a first contact, and a first actuator. The nanotube includes a first end, the first end supported by a first structure, a second end opposite the first end, and a first portion. The first actuator is configured to apply a first force to the nanotube, the first force causing the nanotube to buckle such that the first portion couples to the first contact.Type: GrantFiled: February 16, 2012Date of Patent: April 8, 2014Assignee: Elwha LLCInventors: Howard L. Davidson, Roderick A. Hyde, Jordin T. Kare, Richard T. Lord, Robert W. Lord, Nathan P. Myhrvold, Clarence T. Tegreene, Charles Whitmer, Lowell L. Wood, Jr.
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Patent number: 8693243Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.Type: GrantFiled: October 5, 2011Date of Patent: April 8, 2014Assignee: Grace Semiconductor Manufacturing CorporationInventors: Jing Gu, Bo Zhang, Weiran Kong, Jian Hu
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Patent number: 8693244Abstract: An electronic circuit includes a floating gate transistor with a floating gate capacitor. The floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating gate capacitor. The circuit further includes a deactivation capacitor adapted to store a charge sufficient for deactivating the floating gate transistor temporarily. The deactivation capacitor is connectable in series to the floating gate capacitor. A method for deactivating a floating gate transistor temporarily is provided, wherein the floating gate transistor includes a floating gate capacitor. A deactivation capacitor is charged with a charge sufficient for changing the state of the floating gate transistor temporarily. The deactivation capacitor is connected in series to the floating gate capacitor for deactivating the floating gate transistor.Type: GrantFiled: October 12, 2011Date of Patent: April 8, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Herbert Meier, Jens Graul
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Patent number: 8693245Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.Type: GrantFiled: October 24, 2011Date of Patent: April 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Tae Park, Ki-Nam Kim, Yeong-Taek Lee
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Patent number: 8693246Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.Type: GrantFiled: January 25, 2013Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
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Patent number: 8693247Abstract: A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.Type: GrantFiled: June 17, 2013Date of Patent: April 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Chi-Weon Yoon, Dong-Hyuk Chae, Sang-Wan Nam, Sung-Won Yun
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Patent number: 8693248Abstract: Provided are methods of programming a nonvolatile data storage device including memory blocks sharing a block word line. The methods may include selecting the memory blocks, and the selected memory blocks may include a first memory block that is to be programmed and a second memory block that is to be program-inhibited. The methods may also include applying a program voltage to a selected word line of the first memory block. The methods may further include applying a bipolar prohibition voltage to word lines of the second memory block.Type: GrantFiled: December 30, 2010Date of Patent: April 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Ohsuk Kwon
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Patent number: 8693249Abstract: A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.Type: GrantFiled: January 13, 2012Date of Patent: April 8, 2014Assignee: Winbond Electronics Corp.Inventors: Masaru Yano, Lu-Ping Chiang
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Patent number: 8693250Abstract: A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that of the at least two conductive layers in the first and second blocks are disposed on the driver, and select gate lines in the first and second blocks are connected to the driver through the at least two conductive layers on the driver.Type: GrantFiled: April 30, 2012Date of Patent: April 8, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Maejima
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Patent number: 8693251Abstract: In an embodiment, a processor includes a storage device. The processor is configured to request first data from a first location of a memory device. The storage device is configured to receive and to store the first data from the memory device. The processor is configured to attempt to write second data to the first location of the memory device. The processor is configured to write the first data stored in the storage device and the second data to one or more other locations of the memory device if the attempt to write second data to the first location of the memory device fails.Type: GrantFiled: March 6, 2012Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventor: Frankie F. Roohparvar
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Patent number: 8693252Abstract: A method is provided for adjusting a read voltage in a flash memory device. The method includes storing first program count information when first pages of flash memory cells are programmed, the first program count information indicating a number of bits having a first logic value from among bits of data programmed in the first pages of the flash memory cells, and obtaining first read count information by counting a number of bits having the first logic value from among bits of data read from the first pages of the flash memory cells, while reading data from the flash memory cells using read voltages. The read voltages are adjusted based on the difference between the first read count information and the first program count information.Type: GrantFiled: July 9, 2012Date of Patent: April 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Kui-Yon Mun