Abstract: A signal detection apparatus for a serial attached SCSI (SAS) device includes an SAS female connector to be connected to a SAS device, an SAS male connector to be connected to a system, and first to fourth pairs of subminiature version A (SMA) connectors. When the first pair of SMA connectors is connected to an oscillograph to detect a pair of output signals from the SAS device, the second and third pairs of SMA connectors connect the SAS device with the system. When the second pair of SMA connector is connected to the oscillograph to detect another pair of output signals from the SAS device, the first and fourth pairs of SMA connectors connect the SAS device with the system.

Abstract: Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.

Abstract: An automatic switching mechanism is controlled by a probe card independent from a tester without limitation of the number of control signals from the tester. A probe card and an inspection apparatus include probes to be brought into contact with electrodes of inspection targets and a power supply channel electrically connecting the probes to a tester. The automatic switching mechanism divides each of the power supply channels into a plurality of power supply wiring portions, which are respectively connected to the probes; and shuts off the power supply wiring responsive to electrical fluctuation such as overcurrent. An electrical fluctuation detection mechanism detects an electrical fluctuation due to a defective product among the inspection targets. A control mechanism, responsive to detection of an electrical fluctuation, shuts off the power supply wiring portion if the electrical fluctuation is caused by the automatic switching mechanism.

Abstract: A test device for testing a printed circuit board (PCB) includes a base and a measuring device. The measuring device includes a testing pin and is capable of measuring any desired point of the PCB on condition that the pin makes contact with the point at an included angle between the pin and a back surface of the PCB which is larger than a predetermined angle. The distance between the base and the PCB satisfies: H>L tan ?, where H is the vertical distance between the PCB and the base, L is the maximum length of an orthogonal projection of the pin on the PCB when the pin is contacting the point, and ? is the predetermined angle.

Abstract: A stiffener for a probe card assembly can include decoupling mechanisms disposed within radial arms of the stiffener. The decoupling mechanisms can be compliant in a direction along a radial direction of said radial arm and rigid in a direction perpendicular to said radial arm. The decoupling mechanisms can decouple the stiffener from thermally induced differential radial contraction and expansion of the stiffener relative to the cardholder to which the stiffener is mounted. This can reduce thermally-induced vertical translation of the probe card assembly.

Abstract: A signal processing section included in a semiconductor testing circuit supplies a test signal inputted from a tester via a signal line to a plurality of DUTs and generates a test result by synthesizing response signals transmitted from the plurality of DUTs on the basis of the test signal. A test result output section included in the semiconductor testing circuit makes a voltage level of the test result differ from a voltage level of the test signal inputted and outputs the test result to the tester via the signal line.

Abstract: The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths.

Abstract: A fault signal indicates a single-pole or a double-pole fault in a three-phase electrical power grid which occurred during a present electric oscillation in the electrical power grid. The method assures that single-pole or double-pole faults occurring during oscillation can be detected with high reliability in that a symmetry signal is produced during the oscillation, which indicates whether the oscillation is symmetrical or unsymmetrical, and the phases of the electrical power grid are checked for an existing fault, wherein the symmetry signal is used for carrying out the check. The fault signal is produced if a fault was detected during the check. A protective device has an accordingly equipped control unit.

Abstract: A method for detecting and correcting for a step loss condition. A back electromagnetic force signal is measured and compared to a reference voltage. The motor continues operating and the back electromagnetic force signal is measured again and compared to the reference voltage. If the measured levels of the back emf voltages are less than the reference voltage, a step loss condition has occurred and the stator field is repositioned.

Abstract: Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. Control circuitry compares enabled security features in the device against the security requirements, and can configure the programmable integrated circuit device with the configuration data or prevent such configuration. Control circuitry may also use the security requirement data to set security features within the device.

Abstract: In one general aspect, a data collection system for a circuit under test implemented as an integrated circuit or using a programmable logic device is disclosed. It comprises a configurable selection network connected to debug nodes of the circuit. The selection network can be reconfigured after implementation of the circuit to route data from selectable debug nodes in the circuit under test to a controller to allow analysis of the circuit. The data collection system can further comprise a configurable data packer. A method of use of the system associates data from the debug nodes with individual debug nodes of the circuit based on a configuration of the configurable selection network or that of the configurable data packer or both. The method and system of the invention allows for efficient data collection from different sets of debug nodes without having to re-implement the circuit.

Abstract: A System on a Chip (SoC) has a first set of switches, each having first terminals for routing SoC signals and a second terminal, and a second set of switches. Each switch of the second set of switches has third terminals for routing signals with the first set of switches, and a fourth terminal. A SoC control module defines a switching configuration, and includes a first memory portion for storing a first switching protocol for the first set of switches. This defines, for a switch of the first set of switches, an electrical path between one of the first terminals and the second terminal. A second memory portion stores a second switching protocol for the second set of switches, and defines, for a switch of the second set of switches, an electrical path between one of the third terminals and the fourth terminal.

Abstract: A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.

Abstract: A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

Abstract: A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.

Abstract: Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed.

Abstract: In accordance with an embodiment, a transceiver includes a bidirectional data transmission circuit coupled to a direction control circuit and method for transmitting electrical signals in one or more directions. The direction control circuit generates a comparison signal in response to comparing input/output signals of the bidirectional data transmission circuit. Transmission path enable signals are generated in response to the comparison signal.

Abstract: Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Abstract: A non-overlapping clock generator circuit supplies clock signals to a stage of a pipelined ADC, which includes parallel switched capacitor circuitry. The non-overlapping clock generator circuit includes: a first trigger generation circuit that generates first and second trigger signals; a second trigger generation circuit that generates third and fourth trigger signals; a first clock generation branch that receives the first, second and fourth trigger signals and generates first sampling cycle and delayed sampling cycle clock signals; a second clock generation branch that receives the first, second and third trigger signals and generates second sampling cycle and delayed sampling cycle clock signals; a third clock generation branch that receives the second trigger signal and generates first gain cycle and delayed gain cycle clock signals; and a fourth clock generation branch that receives the first trigger signal and generates second gain cycle and delayed gain cycle clock signals.

Abstract: A comparator having first and second stages can provide component offset compensation and improved dynamic range. The first stage can receive first and second input signals and produce first and second output signals. The second stage can be coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage can provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. The comparator is operable to receive input voltages that reach the supply voltage.

Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.

Abstract: Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator.

Abstract: An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal.

Abstract: The number of power-gating transistors on an integrated circuit used for power reduction in a sleep mode is controlled during a wake state to adjust the current flow and hence voltage drop across the power-gating transistors as a function of aging of these transistors and/or a function of temperature of the integrated circuit. In this way, the supply voltage to the integrated circuit may be better tailored to minimize current leakage when the integrated circuit is young or operating at low temperatures.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: In one aspect, a current driver, includes an operational amplifier that includes a first input port configured to receive a reference signal and a second input port configured to receive a variable signal. The variable signal is a function of an output current of the current driver. The reference signal corresponds to a selected maximum output current of the current driver. The current driver also includes a feedback transistor comprising a gate coupled to the output of the operational amplifier and a summing junction coupled to a drain of the feedback transistor and configured to receive a signal from the drain to enable clamping of the output current of the current driver to the maximum output current when the variable signal exceeds the reference signal. The summing junction is coupled to a set of transistors configured to provide the output current of the current driver.

Abstract: A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.

Abstract: A multiphase clock divider includes: a reference clock generator for generating a plurality of reference clocks; and at least one output clock generator including a first multiplexer for selecting to output a selected reference clock, a second multiplexer for selecting to output a first selected input clock, a third multiplexer for selecting to output a second selected input clock, a first flip-flop for outputting a first sampling clock according to the selected reference clock and the first selected input clock, a second flip-flop for outputting a second sampling clock according to the first sampling clock and the second selected input clock, and a fourth multiplexer for selecting to output the first sampling clock or the second sampling clock to generate an output clock.

Abstract: The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.

Abstract: A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.

Abstract: A transmission/reception device includes a transmission circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals to be sent to another device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew; and a reception circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals sent from another transmission/reception device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew.

Abstract: A mobile communication device is provided that has a transceiver including a voltage controlled oscillator (VCO) and a calibration circuit for calibrating the VCO. The calibration circuit includes a logic block configured to estimate a calibration value for a tuning of the VCO to a desired frequency, and an asynchronous counter configured to execute a counting sequence to identify a frequency of the VCO after the tuning of the VCO using the calibration value, where the calibration circuit is configured to determine a tuned calibration value for producing the desired frequency from the counting sequence.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: A system for wide frequency range clock generation, includes: a phase lock loop (PLL) to generate a signal having a frequency; at least one fractional-N divider to divide the frequency of the signal; and a multiplexer to receive the signal from the PLL and an output signal from the at least one fractional-N divider, and to select the signal from the PLL or the output signal from the at least one fractional-N divider as a selected signal.

Abstract: A frequency synthesizer and a frequency synthesis method thereof are provided. The frequency synthesizer includes a phase-locked loop unit, a voltage-controlled oscillating unit, and a frequency mixing unit. The phase-locked loop unit receives a reference signal and a feedback injection signal and generates a first oscillating signal according to the reference signal and the feedback injection signal. The voltage-controlled oscillating unit receives the feedback injection signal and generates a second oscillating signal according to the feedback injection signal. The frequency mixing unit is coupled to the phase-locked loop unit and the voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal, and mixes the first oscillating signal and the second oscillating signal to generate the feedback injection signal and an output signal.

Abstract: A TDC circuit include: a first delay circuit having first inverting delay devices connected to form a loop, the first inverting delay devices outputting a inverted signal according to an input signal after a first signal delay period; a second delay circuit having second inverting delay devices connected to form a loop, the second inverting delay according to an input signal after a second signal delay period different from the first signal delay period; first flip-flop circuits that latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices based on fourth pulse signals including the second pulse signal or pulse signals; a first counter that counts the third pulse signal; a second counter that counts the fourth pulse signal; and a detection result output circuit that stores the count from the first counter and the count from the second counter.

Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.

Abstract: Systems and methods are disclosed including a duty cycle module having two timer circuits to measure pulse widths of a clock signal. Two comparators are used to generate control signals depending upon comparisons of the pulse width measurements. In response to the control signals, either the clock signal or an inverted clock signal may be programmably delayed such that combination of the clock signal and the inverted clock signal results in a corrected clock signal. Systems and methods are also disclosed for verifying operation of a duty cycle module.

Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.

Abstract: The clock circuit of an integrated circuit operates with tolerance of variation in power. A compensation circuit is powered by a supply voltage. The compensation circuit generates a compensated voltage reference, which is compensated for variation in the supply voltage. The compensated voltage reference is compared by comparison circuitry against an output of timing circuitry, to determine timing of the clock signal.

Abstract: A system and device for reducing leakage current in a sequential circuit is disclosed. In one embodiment, a system for reducing leakage current in a sequential circuit includes a combinational logic circuit, one or more reset flip-flops coupled to the combinational logic circuit, and one or more set-reset flip-flops coupled to the combinational logic circuit. The system further includes a control module coupled to the reset flip-flops and to the set flip-flops and configured to reset the reset flip-flops and to set the set-reset flip-flops when a standby mode of the sequential circuit is triggered.

Abstract: Schmitt trigger with rail-to-rail or near rail-to-rail hysteresis. In some embodiments, a method includes switching an output of a Schmitt trigger from a first logic state to a second state in response to an input meeting a threshold, where the threshold is applied to a first transistor of a first doping type and the input is applied to a second transistor of the first doping type, the first and second transistors operably coupled to each other through a current mirror of a second doping type. The first doping type may be an n-type, the second doping type may be a p-type, and the threshold may be a rising threshold having a value within 10% of a supply voltage. Alternatively, the first doping type may be a p-type, the second doping type may be an n-type, and the threshold may be a falling threshold having a value within 10% of ground.

Abstract: A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

Abstract: One object is to provide a front-end module with a shared output terminal wherein an input impedance is readily matched and an insertion loss is suppressed. In accordance with one aspect, the front-end module 10 includes an input terminal, output terminals, a first filter circuit that passes signals in a first passband, a second filter circuit that passes signals in a second passband, a switch that is disposed between the input terminal and the first and second filter circuits and selectively connects the input terminal to the first and second filter circuits, and a matching circuit. The second filter circuit includes phase shifters.

Abstract: A 0-to-90-degree phase shifter (13) includes a voltage-variable power supply (16), a transistor (17), a 90-degree divider (18), gain-variable amplifiers (19) (19-1 and 19-2), and a combiner (20). The 90-degree divider (18) divides an input signal into a signal to which a 90-degree phase is given and a signal to which no phase is given, and outputs the divided signals to the gain-variable amplifiers (19). The gain-variable amplifiers (19) (19-1 and 19-2) output signals whose amplitudes are changed according to a phase control amount to the combiner (20). The combiner (20) combines the signals input from the two gain-variable amplifiers (19) and outputs the combined signal. The impedance between the source and the drain of the transistor connected to the isolation port of the 90-degree divider (18) can be changed as appropriate.

Abstract: A clock signal capable of changing the frequency in a wide range and with high resolution is generated. An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.

Abstract: A method and circuit for providing on-chip measurement of the delay between two signals includes first and second delay chains (241, 242) having different delay values connected to sampling latches (222-227) which each include a data input coupled between adjacent delay elements of the first delay chain and a clock input coupled between adjacent delay elements of the second delay chain, thereby capturing a high precision delay measurement for the signals.

Abstract: This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.