Abstract: Disclosed is a differential clock signal generator which processes a first differential clock signal using a combination of differential and non-differential components to generate a second differential clock signal. Specifically, the first differential clock signal is converted into a single-ended clock signal, which is used either by a finite state machine to generate two single-ended control signals or by a waveform generator to generate a single-ended waveform control signal. In any case, a deskewer, which comprises a pair of single-ended latches and either multiplexer(s) or logic gates, processes the first differential clock signal, the single-ended clock signal, and the control signal(s) in order to output a second differential clock signal that is different from the first differential clock signal in terms of delay and, optionally, frequency, but synchronously linked to it.

Abstract: A semiconductor apparatus includes a first chip and a second chip mounted on the first chip. The first chip includes a first port that receives an operation clock signal, and a first circuit that operates in synchronization with the operation clock signal. The second chip includes a delay control part that generates a delay control signal indicating a delay amount based on a cycle of a reference clock signal, plural delay circuits that are connected in multiple stages and delay clock signals input to the plural delay control circuits based on the delay control signal and sequentially output the delayed clock signals to a subsequent stage, and a second port that is connected to the first port and receives the operation clock signal based on the delayed clock signals output from the plural delay circuits.

Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: Voltage controlled variable attenuators are described that are configured to be coupled to a transmission path to furnish variable attenuation of a signal, such as a radio frequency signal. In one or more implementations, the voltage controlled variable attenuator includes at least one transistor. The transistor has an open configuration for at least substantially preventing the flow of current through the transistor, and a closed configuration for at least partially allowing the flow of current through the transistor. The variable attenuator also includes a resistive component coupled to the transistor, and configured to couple to the transmission path. The resistive component is configured to at least partially mitigate non-linear effect when the transistor transitions from the open configuration to the closed configuration.

Abstract: System and method for controlling one or more switches. The system includes a first converting circuit, a second converting circuit, and a signal processing component. The first converting circuit is configured to convert a first current and generate a first converted voltage signal based on at least information associated with the first current. The second converting circuit is configured to convert a second current and generate a second converted voltage signal based on at least information associated with the second current. The signal processing component is configured to receive the first converted voltage signal and the second converted voltage signal and generate an output signal based on at least information associated with the first converted voltage signal and the second converted voltage signal.

Abstract: According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.

Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the first and second adjustable phase shifters and attenuation levels to be applied by the first and second adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the first and second adjustable phase shifters and the first and second adjustable attenuators.

Abstract: In one embodiment, the present invention includes a mixer having various stages, including a transconductance stage with a differential transistor pair, a bias circuit, and a feedback circuit. The transistor pair can include a first transistor having a first terminal to receive a first input radio frequency (RF) voltage and to output a first RF current via a second terminal of the first transistor, and a second transistor having a first terminal to receive a second input RF voltage and to output a second RF current via a second terminal of the second transistor. In turn, the bias circuit is coupled to the second terminals of the transistors to provide a bias current to these transistors. The feedback circuit is in turn coupled to the second terminals of the transistors to generate a feedback signal corresponding to a common mode voltage at the second terminals of the transistors.

Abstract: The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.

Abstract: A pressure enabling apparatus includes: a pressure sensor, a resistance wire and a pressure setting module, wherein a terminal of the resistance wire is connected to the pressure sensor and another terminal thereof is connected to an electronic apparatus. The pressure setting module is provided for receiving and converting a resistance variation of the resistance wire into a pressure value. The pressure sensor is provided for varying the resistance value thereof according to an external pressure variation, wherein the resistance variation is processed and transmitted to the pressure setting module via the resistance wire. The electronic apparatus implements an application or function according to a pressure value of the pressure setting module. An electronic apparatus is also provided for implementing different applications by pressing the electronic apparatus and for setting numbers or pages when an application of music-playing or document-reading is locked.

Abstract: A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node.

Abstract: An internal voltage generation circuit includes a pumping voltage generation unit configured to generate a pumping voltage when a first internal voltage has a lower level than a first reference voltage or a second internal voltage has a lower level than a second reference voltage, and a select transmission unit configured to selectively transmit the pumping voltage as the first internal voltage or the second internal voltage.

Abstract: System and method system for regulating voltage in a portion of an integrated circuit. An integrated circuit has a voltage input and at least a portion that is less than all of the integrated circuit, which requires a local voltage level. A voltage selector establishes a target voltage for the portion. A first comparator compares the target voltage to the local voltage and generates a pull up control signal when the local voltage is below the target voltage. A second comparator compares the target voltage to the local voltage and generates a pull down control signal when the local voltage is above the target voltage. A pull up device, responsive to the pull up control signal, increases the local voltage according to the pull up control signal. A pull down device, responsive to the pull down control signal, decreases the local voltage level according to the pull down control signal.

Abstract: An electronic device includes a bandgap reference voltage generation stage. The bandgap reference voltage generation stage comprises a device with a PN-junction, a current source feeding a first current during a first period of time and a second higher current during a second period of time through the PN-junction. The bandgap reference voltage is generated from a combination of a first voltage drop across the PN-junction during the first period of time and a second voltage drop across the PN-junction during the second period of time. This bandgap reference voltage is formed using switched capacitors.

Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.

Abstract: A multi-regulator circuit comprises a regulator configured to regulate an input voltage to generate a constant voltage, and a plurality of voltage division circuits configured to output divided voltages which are obtained by dividing the constant voltage on the basis of a plurality of voltage generation codes, respectively.

Abstract: A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor.

Abstract: A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range.

Abstract: This invention provides a signal processing technique of suppressing various kinds of noise including unknown noise without storing a number of pieces of noise information in advance. To accomplish this, noise information is modified using modification information to obtain modified noise information. The noise in the noisy signal is suppressed using the modified noise information. The modification information is adapted and updated for the result of the step of suppressing.

Abstract: Output conductance of a differential current output type circuit constituting a filter body (1) and having a variable negative resistor connected between differential output lines is automatically regulated. The output conductance automatic regulation circuit comprises a differential voltage/current conversion circuit (2) which is a replica of a differential voltage/current conversion circuit constituting the filter body (1), a variable negative resistor (3) connected between the differential output lines of the differential voltage/current conversion circuit (2), a detector (4) for detecting the DC potential difference between the differential output lines of the differential voltage/current conversion circuit (2), and a controller (5) for controlling the differential voltage/current conversion circuit (2) and the conductance of a variable negative resistor connected with the differential voltage/current conversion circuit constituting the filter body (1) based on the detection results from the detector (4).

Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.

Abstract: A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.

Abstract: A circuit for optimizing a power management system. The circuit includes a first amplifier. The first amplifier is responsive to a first reference signal and operable to supply a first load current. The circuit also includes a second amplifier coupled to the first amplifier. The second amplifier is responsive to a second reference signal and operable to supply a second load current. The second load current is lower in magnitude than the first load current, thereby enabling the first amplifier to operate during a first load condition, and the second amplifier to operate during the first load condition and a second load condition. Further, the circuit includes a resistive element coupled to the first amplifier and the second amplifier, to isolate the first amplifier from the second amplifier.

Abstract: A power amplifier is provided which is capable of performing efficient amplification in a wider transmission signal power range than conventional power amplifiers. The power amplifier for amplifying and outputting an input signal includes first to N-th amplifiers (N is an integer of two or more) which are cascaded. A Doherty amplifier is used in circuit configuration of each of the first to N-th amplifiers. At least one of the first to (N?1)-th amplifiers has a different power ratio from that of the N-th amplifier.

Abstract: A system including a power amplifier and a pre-distortion module coupled to the power amplifier. The pre-distortion module includes one or more smaller versions of the power amplifier to generate a pre-distortion signal that compensates for any memory-effect or inertia present in the power amplifier with application on frequency hopping and larger (up to 1 octave) instantaneous bandwidth communication systems.

Abstract: A digital pre-distortion system which can provide the flexibility to model the highly non-linear distortion associated with High Efficiency RF Power Amplifiers while through a novel implementation of a least squares estimation process allows an implementation well suited for an FPGA application where limited resources and in particular memory resources are available.

Abstract: A power amplifier for amplifying an electric input signal in an operational frequency range and providing an output signal, comprising switching means (22), filter means (14, 15) for generating a power output signal by low pass filtering a block wave signal, input means for receiving the electric signal and feeding it to a first input of the switching means, the power amplifier further comprising a feedback circuit (24) connecting the output signal to the first input of the switching means. The power amplifier comprises a servo amplifier (32) connected to receive an error signal appearing at the first input of the switching means and to feed a correction output signal to a second input of the switching means (22) for neutralizing an impact of the error signal on the output signal. The invention relates to a method of amplifying an electric input signal in an operational frequency range.

Abstract: Systems, methods and apparatus are disclosed for amplifiers for wireless power transfer. In one aspect a method is provided for controlling operation of an amplifier, such as a class E amplifier. The method may include monitoring an output of the amplifier. The method may further include adjusting a timing of an enabling switch of the amplifier based on the output of the amplifier.

Abstract: An electronic circuit has a differential amplifier with a differential transistor pair having two transistors. The electronic circuit also has two digital-to-analog converters, a respective one of the two digital-to-analog converters coupled to each respective one of the two transistors. Control bits adjust the DACs to provide an offset voltage adjustment of the differential amplifier.

Abstract: A variable gain amplifier circuit is disclosed. The variable gain amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first gain switching circuit, and a second gain switching circuit. The first and the second transistors are respectively coupled to the first and the second nodes for receiving a differential input signal pair. The third transistor is coupled between the first node and a third node. The fourth transistor is coupled between the second node and a fourth node. The first gain switching circuit is coupled between the first node and the third node and further cross-coupled to the fourth node. The second gain switching circuit is coupled between the second node and the fourth node and further cross-coupled to the third node.

Abstract: To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used.

Abstract: An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result.

Abstract: An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a ground voltage (AGND). The comparator compares an input voltage and an output voltage and outputs a control signal to the bias current source according to the compared result to control a bias current outputted by the bias current source to enhance the slew rate of the output buffer.

Abstract: An amplifier includes a first switch and a second switch each having a first terminal and a second terminal. The first terminals of the first and second switches respectively communicate with a first tank circuit and a second tank circuit. The second terminal of the second switch communicates with the second terminal of the first switch. A first capacitance having a first terminal connected directly to (i) the second terminal of the first switch and (ii) the second terminal of the second switch. A second terminal of the first capacitance is connected directly to a first input voltage of the amplifier. A first load is connected across (i) the first terminal of the first switch and (ii) the first terminal of the second switch. The amplifier generates a first output across the first load.

Abstract: A Doherty amplifier has a distributor for branching an input signal into two signals, a carrier amplifier to which one of the signals is inputted from the distributor, a peak amplifier to which another signal of the signals is inputted from the distributor, and a synthesizer for synthesizing output signals from the carrier amplifier and the peak amplifier. The carrier amplifier has a compound semiconductor device with at least two terminals. The peak amplifier has a single element semiconductor device. Bias voltages having the same polarity are applied to the two terminals of the compound semiconductor device.

Abstract: There is provided a power amplifier module having a bias circuit, in which a bias power is supplied to an amplifier by differently setting an impedance between an input signal terminal and a reference power terminal and an impedance between the input signal terminal and a ground. The power amplifier module includes: an amplifier unit receiving a bias power to amplify an input signal; and a bias unit supplying the bias power to the amplifier, by differently setting an impedance between an input signal terminal transmitting the input signal therethrough and a reference power terminal transmitting a reference power having a predetermined voltage level and an impedance between the input signal terminal and a ground.

Abstract: A radio frequency (RF) generation module includes a power control module that receives first and second desired amplitudes of an output of the RF generation module in first and second respective states, and that outputs, based on the first and second desired amplitudes, input power setpoints corresponding to a transition from the first state to the second state. A frequency control module receives the input power setpoints and outputs frequency setpoints corresponding to the input power setpoints. A pulse shaping module receives the input power setpoints, the frequency setpoints, and an indication of when to transition from the first state to the second state, and transitions the output of the RF generation module from the first state to the second state based on the input power setpoints, the frequency setpoints, and the indication.

Abstract: An output matching network comprising a plurality of impedance matching circuits. The inputs of each of the plurality of impedance matching circuits are connected to a first input of the output matching network. The outputs of each of the plurality of impedance matching circuits are connected to a plurality of first outputs of the output matching network. One of the plurality of impedance matching circuits is active at a given time. The active impedance matching circuit of the plurality of impedance matching circuits exhibits a first input impendence at a first frequency band. Each inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a second input impedance at the first frequency band. The second input impendence is at least 10 times greater than the first input impendence.

Abstract: A power circuit includes a RF transistor and an input match network coupled to an input to the RF transistor and to an input to the power circuit. The input match network includes a resistor, an inductor and a capacitor that are coupled together in series between the input to the RF transistor and a ground. The values of the resistor and the inductor are selected to match an input impedance of the RF transistor to a source impedance at the input to the power circuit over at least a portion of a high frequency range, wherein the value of the capacitor has a substantially negligible contribution to the match at the high frequency range. The value of the capacitor is selected so that the series combination of the resistor, the inductor and the capacitor substantially reduce the magnitude of the impedance presented to the input of the RF transistor in a low frequency range relative to the source impedance at the input to the power circuit.

Abstract: An amplifier for use in a buoyant cable antenna operable to receive signals within a frequency band includes: a first amplifier operable to provide amplified signals based on the received signals; a bandpass filter arranged to pass filtered signals within a first portion of the frequency band, the filtered signals being based on the amplified signals; an attenuator arranged in parallel with said bandpass filter and operable to attenuate signals within a second portion of the frequency band, the attenuated signals being based on the amplified signals; and a second amplifier operable to provide an amplified output including first amplified signals within the first portion of the frequency band and to provide second amplified signals within the second portion of the frequency band. The first amplified signals have a first gain, the second amplified signals have a second gain, and the first gain is more than the second gain.

Abstract: The invention concerns a detection device including a photodiode (Ph) designed to capture a luminous signal to transform it into a current (Iph) and including first and second terminals, a transimpedance amplifier circuit connected between the first terminal and the second terminal of the photodiode (Ph) and designed to amplify the current (Iph) coming from the photodiode (Ph). The transimpedance amplifier circuit includes a plurality of operational amplifiers (AOP1, AOP2, AOP3) connected in parallel and a gain resistor (Rgain) common to all the connected amplifiers.

Abstract: In one embodiment, an apparatus includes a first amplification block configured to receive a signal and a second amplification block configured to output the signal. The outputted signal is an amplified version of the signal. A circuit allows reuse of a second current flowing through the second amplification block by coupling the second current to pass through the first amplification block to increase a first current that flows through the first amplification block. Amplification of the signal is based on the increased first current that flows through the first amplification block.

Abstract: A power amplifier circuit uses an output transistor and a cascode transistor. First and second drive circuits apply gate control signals to the two transistors, which rise and fall in synchronism, and this is such that the voltage drop across the cascode transistor is reduced (compared to a constant gate voltage being applied to the output transistor).

Abstract: In some embodiments, provided are calibration techniques for measuring mismatches between TDL delay stage elements, and in some cases, then compensating for the mismatches to minimize performance degradation.

Abstract: The embodiments described herein provide a voltage controlled oscillator (VCO). The VCO may include, but is not limited to a voltage-to-current converter configured to receive a control voltage and to convert the control voltage to a current, a current bias circuit coupled to the voltage-to-current converter and configured to receive frequency band select digital inputs and to bias the current generated by the voltage-to-current converter based upon the band select inputs, and a ring oscillator coupled to receive the biased current and to output an oscillating signal based upon the biased current.

Abstract: A gas cell unit includes a gas cell in which a gaseous alkali metal atom is sealed, a first heater to heat the gas cell, and a second heater which is provide to face the first heater across the gas cell and heats the gas cell. The first heater includes a first heating resistor which generates heat by energization, and the second heater includes a second heating resistor through which a current flows in the same direction as the direction of a current flowing through the first heating resistor and which generates heat by energization. Between the first heating resistor and the second heating resistor, a magnetic field generated by the energization to the first heating resistor and a magnetic field generated by the energization to the second heating resistor are mutually cancelled or weakened.

Abstract: A reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuit are described. In one embodiment, the reference circuit includes a voltage reference generator configured to generate a reference voltage and a current reference generator configured to generate a reference current based on the reference voltage. The current reference generator includes a level shifter circuit configured to generate intermediate voltages based on the reference voltage, a first current reference circuit configured to generate intermediate currents based on the intermediate voltages, where the intermediate currents are correlated to the reference voltage, and a second current reference circuit configured to combine the intermediate currents to generate the reference current. Other embodiments are also described.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: A calibration circuit includes at least two compensation circuits and a comparator. The at least two compensation circuits are coupled to an input signal for outputting at least a first compensation signal and a second compensation signal respectively. The comparator is coupled to the first compensation signal and the second compensation signal for outputting a calibration signal, where the calibration signal is used for determining an oscillation frequency of a crystal oscillator to achieve a purpose of frequency compensation with a temperature.