Abstract: Methods and apparatus for producing EUV from plasma are disclosed. The apparatus includes a plasma generating system comprising a source of target material droplets and a laser producing a beam irradiating the droplets at an irradiation region. The plasma produces EUV radiation, wherein the droplet source comprises a nozzle having an orifice configured for ejecting a fluid and a sub-system having an electro-actuable element producing a disturbance in the fluid to cause at least some of the droplets to coalesce prior to being irradiated. The electro-actuable element is coupled to nozzle using an adhesive that has a high modulus at the nozzle operating temperature. Improvements also include tuning the nozzle assembly to more closely match the modulation waveform frequency with one of the resonance frequencies of the nozzle assembly by optimizing one of a mass, a shape, or material composition of at least one component in the nozzle assembly.

Abstract: In certain exemplary embodiments of the present invention, three-dimensional micro-mechanical devices and/or micro-structures can be made using a production casting process. As part of this process, an intermediate mold can be made from or derived from a precision stack lamination and used to fabricate the devices and/or structures. Further, the micro-devices and/or micro-structures can be fabricated on planar or nonplanar surfaces through use of a series of production casting processes and intermediate molds. The use of precision stack lamination can allow the fabrication of high aspect ratio structures. Moreover, via certain molding and/or casting materials, molds having cavities with protruding undercuts also can be fabricated.

Abstract: A proximity sensor includes a sensor package having an attachment pad with a radiation source and a radiation detector housed within the sensor package. The source and the detector are held in a fixed relation to the attachment pad, and are mounted by one of a direct or indirect attachment to the attachment pad. A portion of the attachment pad is adapted to form a baffle which forms at least part of an optical isolator. The optical isolator is adapted to substantially prevent the internal propagation of radiation between the source and the detector within the sensor package.

Abstract: An off-axis telescope having a primary optical element configured to reflect an energy beam from an optical reference source that emits the energy beam along an optical path. The telescope includes angle sensors arranged on a periphery of the primary optical element to determine angular motion of the energy beam from the optical reference source. The angle sensors are operable to be biased to positional settings associated with a desired pointing direction of the energy beam. A secondary optical element is arranged in the optical path and translated along three orthogonal axes. A plurality of steering mirrors arranged between the optical reference source and the secondary optical element is configured to be tilted in response to a control signal. A controller auto-aligns the telescope by at least translating the secondary optical element and tilting the steering mirrors via the control signal using at least inputs from the plurality of angle sensors.

Abstract: A processing device includes a control section adapted to perform emission control of first and second light source sections based on a light reception result of a light receiving section adapted to receive a reflected light beam caused by an object reflecting irradiation light beams from the first and second light source sections, and a determination section adapted to determine a positional relationship of the object with respect to the first and second light source sections based on emission current control information for performing the emission control. The determination section determines the positional relationship of the object based on first period emission current control information as the emission current control information in a first period in which no object exists in the detection area and second period emission current control information as the emission current control information in a second period in which the object exists in the detection area.

Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.

Abstract: An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.

Abstract: Compound semiconductors capable of emitting light in the green spectrum are provided. The compound semiconductors may display improved quantum efficiencies when applied to various optical devices. Also, light emitting diodes and light emitting diode modules comprising the compound semiconductors are provided.

Abstract: A light emitting device may include a light emitting structure that includes a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the active layer includes a light emitting layer adjacent to the second semiconductor layer and that includes a well layer and a barrier layer and a super-lattice layer between the light emitting layer and the first semiconductor layer, the super-lattice layer including at least six pairs of a first layer and a second layer, wherein a composition of the first layer includes indium (In) and the second layer includes indium (In), and the composition of the first layer is different from the composition of the second layer.

Abstract: A light emitting device includes a metal backing layer, a reflective electrode layer disposed on the metal backing layer, and a plurality of nanorods disposed on the reflective electrode layer. Each nanorod includes a p-semiconductor layer, an active layer, and an n-semiconductor layer, which are sequentially stacked on the reflective electrode layer. The light emitting device further includes an anti-reflection electrode layer disposed on the nanorods, and quantum dots disposed between the nanorods. The method includes sequentially growing the n-semiconductor layer, the active layer, and the p-semiconductor layer on a substrate; forming the nanorods by etching the p-semiconductor layer using a mask pattern; sequentially forming the reflective electrode layer and the metal backing layer on the p-semiconductor layer and then removing the substrate; disposing quantum dots between the nanorods; and forming the anti-reflection electrode layer on the nanorods.

Abstract: Disclosed are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package and a lighting system. The light emitting device includes a first conductive semiconductor layer; an active layer including a quantum well and a quantum barrier and disposed on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The active layer includes a first quantum well adjacent to the second conductive semiconductor layer, a second quantum well adjacent to the first quantum well, and a first quantum barrier between the first quantum well and the second quantum well. A recombination rate of electron-hole in the second quantum well is higher than the recombination rate of the electron-hole in the first quantum well, and the first quantum well has an energy level higher than the energy level of the second quantum well.

Abstract: A nitride semiconductor light emitting device includes first and second type nitride semiconductor layers. An active layer is disposed between the first and second type nitride semiconductor layers. A current spreading layer is disposed between the second type nitride semiconductor layer and the active layer. The current spreading layer includes first nitride thin films and second nitride thin films which are alternately laminated. The first nitride thin films have band gaps larger than those of the second nitride thin films. A first plurality of first nitride thin films are positioned at outer first and second sides of the current spreading layer. The first plurality of first nitride thin films have a thickness greater than that of a second plurality of first nitride thin films positioned between the first plurality of first nitride thin films.

Abstract: Provided are a light emitting device, a method of fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a substrate, a first semiconductor layer containing indium (In) over the substrate, and a light emitting structure over the first semiconductor layer. A dislocation mode is disposed on a top surface of the first semiconductor layer.

Abstract: For a nitride semiconductor light emitting device, a c-axis vector of hexagonal GaN of a support substrate is inclined to an X-axis direction with respect to a normal axis Nx normal to a primary surface. In a semiconductor region an active layer, a first gallium nitride-based semiconductor layer, an electron block layer, and a second gallium nitride-based semiconductor layer are arranged along the normal axis on the primary surface of the support substrate. A p-type cladding layer is comprised of AlGaN, and the electron block layer is comprised of AlGaN. The electron block layer is subject to tensile strain in the X-axis direction. The first gallium nitride-based semiconductor layer is subject to compressive strain in the X-axis direction. The misfit dislocation density at an interface is smaller than that at an interface. A barrier to electrons at the interface is raised by piezoelectric polarization.

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract: A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.

Abstract: The present invention relates to an organic transistor comprising a conductive element which forms a drain; a conductive element which forms a source located away from the drain; a conductive element which forms a gate having a surface which faces the drain and a surface which faces the source; a semiconducting layer which is in contact with the drain and the source; and a dielectric layer located between, firstly, the gate and, secondly, the source and the drain with the dielectric layer having a dielectric permittivity which varies depending on its thickness. According to the invention, the dielectric layer comprises a layer of a first dielectric material having a dielectric permittivity of less than four in which there is formed, at least between said opposite-facing surfaces, a volume of a second material, said volume having an overall cross-section which tapers from gate towards the space between drain and source and in that the relative dielectric permittivity of the second material exceeds four.

Abstract: A thin film transistor has a dual semiconducting layer comprising two semiconducting sublayers. The first sublayer comprises a polythiophene and carbon nanotubes. The second sublayer comprises the polythiophene and has no carbon nanotubes. Devices comprises the dual semiconducting layer exhibit high mobility.

Abstract: A protein photoelectric conversion device including a gold electrode; and a substance selected from the group consisting of a metal-substituted cytochrome b562, a zinc chlorin cytochrome b562, a derivative thereof, and a variant thereof immobilized on the gold electrode.

Abstract: An organic electro-luminescence (EL) display device according to the present invention includes: a main substrate; a display section provided above the main substrate and including a red light-emitting layer, a green light-emitting layer, a blue light-emitting layer, and a bank; a blue color filter provided above the display section, which selectively transmits blue light and selectively absorbs green light and red light; and a red color filter provided above the display section, which selectively transmits the red light and selectively absorbs the blue light and the green light, wherein the blue color filter has openings each at a position corresponding to the red light-emitting layer or the green light-emitting layer, and the red color filter has openings each at a position corresponding to the green light-emitting layer or the blue light-emitting layer.

Abstract: A light-emitting element, a light-emitting module, a light-emitting panel, or a light-emitting device in which loss due to electrical resistance is reduced is provided. The present invention focuses on a surface of an electrode containing a metal and on a layer containing a light-emitting organic compound. The layer containing a light-emitting organic compound is provided between one electrode including a first metal, whose surface is provided with a conductive inclusion, and the other electrode.

Abstract: The invention provides a material for forming a passivation film for a semiconductor substrate. The material includes a polymer compound having an anionic group or a cationic group.

Abstract: The present application provides a thin film transistor and a method of manufacturing same capable of suppressing diffusion of aluminum to oxide semiconductor and selectively etching oxide semiconductor and aluminum oxide. The thin film transistor includes: a gate electrode; a channel layer whose main component is oxide semiconductor; a gate insulating film provided between the gate electrode and the channel layer; a sealing layer provided on the side opposite to the gate electrode, of the channel layer; and a pair of electrodes which are in contact with the channel layer and serve as a source and a drain. The sealing layer includes at least a first insulating film made of a first insulating material, and a second insulating film made of a second insulting material having etching selectivity to each of the oxide semiconductor and the first insulating material and provided between the first insulating film and the channel layer.

Abstract: A semiconductor device, a thin film transistor, and a method for producing the same capable of decreasing the management cost, and capable of decreasing the production steps to reduce the production cost are proposed. A method for producing a thin film transistor 2 provided with a semiconductor which is composed of a prescribed material and serves as an active layer 41 and a conductor which is composed of a material having the same composition as that of the prescribed material and serves as at least one of a source electrode 51, a drain electrode 53 and a pixel electrode 55, which includes the steps of simultaneously forming into a film an object to be processed and a conductor (a source electrode 51, a source wire 52, a drain electrode 53, a drain wire 54 and a pixel electrode 55) which are composed of the amorphous prescribed material, followed by simultaneous shaping, and crystallizing the object to be processed which has been shaped to allow it to be the active layer 41.

Abstract: Provided is a semiconductor device for high power application including a novel semiconductor material with high productivity. Alternatively, provided is a semiconductor device having a novel structure in which the novel semiconductor material is used. Provided is a vertical transistor including a channel formation region formed using an oxide semiconductor which has a wider band gap than a silicon semiconductor and is an intrinsic semiconductor or a substantially intrinsic semiconductor with impurities that can serve as electron donors (donors) in the oxide semiconductor removed. The thickness of the oxide semiconductor is greater than or equal to 1 ?m, preferably greater than 3 ?m, more preferably greater than or equal to 10 ?m, and end portions of one of electrodes that are in contact with the oxide semiconductor is placed inside end portions of the oxide semiconductor.

Abstract: An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

Abstract: A thin film transistor is provided. The thin film transistor includes a gate electrode, a gate insulating film, and an oxide semiconductor film, wherein at least a portion of the gate electrode includes a metal oxide. An electric device and a display device that include the thin film transistor are also provided in addition to a manufacture method.

Abstract: A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed.

Abstract: A semiconductor device including a first wafer assembly having a first substrate and a first oxide layer over the first substrate. The semiconductor device further includes a second wafer assembly having a second substrate and a second oxide layer over the second substrate. The first oxide layer and the second oxide layer are bonded together by van der Waals bonds or covalent bonds. A method of bonding a first wafer assembly and a second wafer assembly including forming a first oxide layer over a first substrate. The method further includes forming a second oxide layer over a second wafer assembly. The method further includes forming van der Waals bonds or covalent bonds between the first oxide layer and the second oxide layer.

Abstract: A transistor which is formed using an oxide semiconductor layer and has electric characteristics needed for the intended use, and a semiconductor device including the transistor are provided. The transistor is formed using an oxide semiconductor stack including at least a first oxide semiconductor layer in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which is provided over the first oxide semiconductor layer and has an energy gap different from that of the first oxide semiconductor layer. There is no limitation on the stacking order of the first oxide semiconductor layer and the second oxide semiconductor layer as long as their energy gaps are different from each other.

Abstract: An object is to increase field effect mobility of a thin film transistor including an oxide semiconductor. Another object is to stabilize electrical characteristics of the thin film transistor. In a thin film transistor including an oxide semiconductor layer, a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor is formed over the oxide semiconductor layer, whereby field effect mobility of the thin film transistor can be increased. Further, by forming a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor between the oxide semiconductor layer and a protective insulating layer of the thin film transistor, change in composition or deterioration in film quality of the oxide semiconductor layer is prevented, so that electrical characteristics of the thin film transistor can be stabilized.

Abstract: A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.

Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.

Abstract: A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base.

Abstract: A manufacturing process of an LCD device of the invention includes forming a first substrate provided with a pixel part with thin film transistors and a seal portion arranged around the pixel part, forming a second substrate opposed to the first substrate, filling a liquid crystal layer between the first substrate and the second substrate, and adhering the first substrate to the second substrate with a sealant provided for the seal portion, wherein the forming the first substrate includes forming a semiconductor layer composing the thin film transistor, forming in the seal portion a semiconductor connection layer made of a same material as the semiconductor layer, and forming an organic interlayer insulating film, wherein the forming the semiconductor layer and the forming the semiconductor connection layer are performed in the same step.

Abstract: The present invention relates to a thin-film transistor in a liquid crystal display device and a method of fabricating the same, and the thin-film transistor may be configured by including a first gate electrode formed on an insulating substrate; a first gate insulation film formed on the insulating substrate including the first gate electrode; an active layer formed on the first gate insulation film; source/drain electrodes formed on the active layer and arranged at both sides of the first gate electrode; a second gate insulation film formed on the active layer and the first gate insulation film including the source/drain electrodes and provided with a contact hole for exposing part of the drain electrode; a second gate electrode overlapped with the first gate electrode on the second gate insulation film; and a pixel electrode electrically connected to the drain electrode through the contact hole.

Abstract: An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode and including a gate opening; an active layer on the gate insulating layer and overlapping the gate electrode; an ohmic contact layer on the active layer; a source electrode on the ohmic contact layer; a drain electrode on the ohmic contact layer and spaced apart from the source electrode, wherein one end of the drain electrode is disposed in the gate opening; a data line on the gate insulating layer and connected to the source electrode, the data line crossing the gate line; a passivation layer on the data line and the source and drain electrodes and including a pixel opening, wherein the pixel opening exposes the drain electrode in the gate opening and a portion of the gate insulating layer; and a pixel electrode on the gate insulating layer and in the pixel opening, the pixel electrode contacting the one end

Abstract: Discussed is a composition of an organic insulating layer comprising a photosensitizer, a binder, an additive and a solvent, wherein the photosensitizer includes a photoacid generator (PAG), and a thin film transistor substrate and display device using the same, wherein the composition of the present invention enables to realize a simplified process by omitting an additional entire-surface exposing process for a color change, and a baking process after an exposing process; and to minimize a problem of color-coordinates shift by realizing a good light transmittance.

Abstract: Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided.

Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm3 to about 4E23 atoms/cm3. The source and the drain are connected with the silicon-rich channel layer.

Abstract: An array substrate for an organic electroluminescent display device includes a substrate including a display area and a non-display area; a gate line and a data line; a thin film transistor including a semiconductor layer of polycrystalline silicon, a gate insulating layer, a gate electrode, an inter insulating layer, a source electrode, and a drain electrode; auxiliary lines formed of a same material and on a same layer as the data line; a passivation layer of organic insulating material and including a drain contact hole exposing the drain electrode, and an auxiliary line contact hole exposing one of the auxiliary lines; and a first electrode and a line connection pattern on the passivation layer, wherein the first electrode contacts the drain electrode and the line connection pattern contacts the one of the first auxiliary pattern.

Abstract: A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217-220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.

Abstract: A nitride-based semiconductor device according to the present disclosure includes a nitride-based semiconductor multilayer structure 20 with a p-type semiconductor region, of which the surface 12 defines a tilt angle of one to five degrees with respect to an m plane, and an electrode 30, which is arranged on the p-type semiconductor region. The p-type semiconductor region is made of an AlxInyGazN (where x+y+z=1, x?0, y?0 and z?0) semiconductor layer 26. The electrode 30 includes an Mg layer 32, which is in contact with the surface 12 of the p-type semiconductor region, and a metal layer 34 formed on the Mg layer 32. The metal layer 34 is formed from at least one metallic element that is selected from the group consisting of Pt, Mo and Pd.

Abstract: A method of fabricating a rare earth silicide gate electrode on III-N material grown on a silicon substrate includes growing a single crystal stress compensating template on a silicon substrate. The template is substantially crystal lattice matched to the surface of the silicon substrate. A single crystal GaN structure is grown on the surface of the template and substantially crystal lattice matched to the template. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched to the GaN structure. A single crystal monoclinic rare earth oxide dielectric layer is grown on the active layer of III-N material and a single crystal rare earth silicide gate electrode is grown on the dielectric layer, the silicide. Relative portions of the gadolinium metal and the silicon are adjusted during deposition so they react to form rare earth silicide during deposition.

Abstract: This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

Abstract: The present invention relates to a method of manufacturing an LED device which emits light of multi-wavelengths. The invention also relates to a method of manufacturing LED devices which emit light of high quality from throughout the whole surface in a uniform manner. In particular, utilizing the manufacturing method of LED devices which emit light of multi-wavelengths makes it possible to produce LED devices of high quality in a simple and cost-efficient way, not by using adhesives, but by a sputtering or PLD method. In addition, since the characteristics of the desired emitted light can be controlled by controlling the amount and type of the phosphors during the manufacture of sputtering targets, high quality LED devices can be manufactured easily.

Abstract: A semiconductor light emitting element (1) provided with an n-type semiconductor layer (140), a light emitting layer (150), a p-type semiconductor layer (160), a transparent electrode (170), a p-side electrode (300) formed on the transparent electrode, and an n-side electrode (400) formed on the n-type semiconductor layer. The p-side electrode has a p-side joining layer (310) and a p-side bonding pad electrode (320), which are laminated on the transparent electrode, and the n-side electrode has an n-side joining layer (410) and an n-side bonding pad electrode (420), which are laminated on the n-type semiconductor layer. The p-side joining layer and the n-side joining layer are configured of a mixed layer composed of TaN and Pt, and the p-side bonding pad electrode and the n-side bonding pad electrode are configured of a laminated structure composed of Pt and Au.

Abstract: Low loss optical apertures are provided. A silicon intermediate layer sandwiched between a metal aperture layer and a dielectric layer has been found to offer a good combination of low optical loss combined with superior mechanical properties.