Patents Issued in July 1, 2014
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Patent number: 8765522Abstract: One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming a first oxide component over a base component, causing crystal growth which proceeds from a surface toward an inside of the first oxide component by first heat treatment to form a first oxide crystal component at least partly in contact with the base component, forming a second oxide component over the first oxide crystal component; and causing crystal growth by second heat treatment using the first oxide crystal component as a seed to form a second oxide crystal component.Type: GrantFiled: November 22, 2010Date of Patent: July 1, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8765523Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.Type: GrantFiled: November 6, 2012Date of Patent: July 1, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Takeyoshi Masuda
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Patent number: 8765524Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.Type: GrantFiled: August 15, 2013Date of Patent: July 1, 2014Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
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Patent number: 8765525Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.Type: GrantFiled: June 16, 2011Date of Patent: July 1, 2014Assignee: STATS ChipPAC Ltd.Inventors: In Sang Yoon, DeokKyung Yang, Sungmin Song
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Patent number: 8765526Abstract: Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.Type: GrantFiled: December 21, 2011Date of Patent: July 1, 2014Inventor: Akira Ide
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Patent number: 8765527Abstract: A method of assembling Redistributed Chip Package (RCP) semiconductor devices. An active die structure is encapsulated in a molding compound with internal electrical contacts of the active die structure positioned at an active face of an encapsulation layer. A dummy die structure is positioned at a back face of the encapsulation layer. A redistribution layer is formed at an active face of the encapsulation layer. The redistribution layer includes a layer of insulating material and redistribution electrical interconnections. The insulating material is built up with grooves along saw streets. External electrical contacts exposed at a surface of the redistribution layer are connected with the redistribution electrical interconnections. The dummy die structure is removed and then the semiconductor devices are singulated.Type: GrantFiled: June 13, 2013Date of Patent: July 1, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Dominic Koey
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Patent number: 8765528Abstract: A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 4, 2013Date of Patent: July 1, 2014Assignee: Intel CorporationInventors: Sabina J. Houle, James P Mellody
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Patent number: 8765529Abstract: A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.Type: GrantFiled: October 30, 2013Date of Patent: July 1, 2014Assignee: Spansion LLCInventor: Naomi Masuda
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Patent number: 8765530Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: March 15, 2013Date of Patent: July 1, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8765531Abstract: A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.Type: GrantFiled: August 21, 2012Date of Patent: July 1, 2014Assignee: Infineon Technologies AGInventors: Johann Gatterbauer, Bernhard Weidgans, Joerg Busch
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Patent number: 8765532Abstract: A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.Type: GrantFiled: January 11, 2010Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Zhibin Ren, Xinhui Wang, Haizhou Yin
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Patent number: 8765533Abstract: A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin.Type: GrantFiled: December 4, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsing Hsieh, Zhiqiang Wu, Ching-Fang Huang, Jon-Hsu Ho
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Patent number: 8765534Abstract: A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation.Type: GrantFiled: February 8, 2013Date of Patent: July 1, 2014Assignee: National Semiconductor CorporationInventor: Alexander H. Owens
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Patent number: 8765535Abstract: In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed.Type: GrantFiled: October 21, 2011Date of Patent: July 1, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kengo Akimoto
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Patent number: 8765536Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.Type: GrantFiled: September 28, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Solomon Assefa, Tymon Barwicz, Swetha Kamlapurkar, Marwan H. Khater, Steven M. Shank, Yurii A. Vlasov
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Patent number: 8765537Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.Type: GrantFiled: September 7, 2012Date of Patent: July 1, 2014Assignee: Globalfoundries Inc.Inventors: Man Fai Ng, Bin Yang
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Patent number: 8765538Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.Type: GrantFiled: October 23, 2013Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Bio Kim, Kihyun Hwang, Jaeyoung Ahn, SeungHyun Lim, Dongwoo Kim
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Patent number: 8765539Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: GrantFiled: January 15, 2014Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Patent number: 8765540Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain regionType: GrantFiled: May 16, 2012Date of Patent: July 1, 2014Assignee: The Institute of Microelectronics Chinese Academy of ScienceInventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
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Patent number: 8765541Abstract: A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed.Type: GrantFiled: August 19, 2011Date of Patent: July 1, 2014Assignee: Altera CorporationInventors: Girish Venkitachalam, Che Ta Hsu, Fangyun Richter, Peter J. McElheny
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Patent number: 8765542Abstract: One method disclosed includes forming a gate structure of a transistor above a surface of a semiconducting substrate, forming a sidewall spacer proximate the gate structure, forming a sacrificial layer of material above the protective cap layer, sidewall spacer and substrate, forming an OPL layer above the sacrificial layer, reducing a thickness of the OPL layer such that, after the reduction, an upper surface of the OPL layer is positioned at a level that is below a level of an upper surface of the protective cap layer, performing a first etching process to remove the sacrificial layer from above the protective cap layer to expose the protective cap layer for further processing, performing a second etching process to remove the protective cap layer and performing at least one process operation to remove at least one of the OPL layer or the sacrificial layer from above the surface of the substrate.Type: GrantFiled: February 13, 2013Date of Patent: July 1, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Frank Seliger, Markus Lenski, Stephan Kronholz
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Patent number: 8765543Abstract: A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first layer and a second layer over a substrate, where the first layer includes a conductive or semiconductor control gate material and the second layer includes an insulating material. The method also includes etching the stack to form at least one opening in the stack, selectively etching the first layer to form first recesses, forming a conductive or semiconductor liner having a clam shape in the first recesses, forming a blocking dielectric over the conductive or semiconductor liner in the first recesses, forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric, forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening, and forming a semiconductor channel in the opening.Type: GrantFiled: October 11, 2013Date of Patent: July 1, 2014Assignee: SanDisk Technologies, Inc.Inventors: Johann Alsmeier, George Samachisa
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Patent number: 8765544Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.Type: GrantFiled: September 5, 2012Date of Patent: July 1, 2014Assignee: Broadcom CorporationInventor: Akira Ito
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Patent number: 8765545Abstract: A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.Type: GrantFiled: May 30, 2013Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mei-Hsuan Lin, Chih-Kang Chao, Chih-Hsun Lin, Ling-Sung Wang
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Patent number: 8765546Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a first gate structure on the fin-shaped structure; forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure; forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer; forming an opening in the interlayer dielectric layer to expose the first epitaxial layer; forming a silicon cap on the first epitaxial layer; and forming a contact plug in the opening.Type: GrantFiled: June 24, 2013Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Jia-Rong Wu, Chih-Sen Huang
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Patent number: 8765547Abstract: An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.Type: GrantFiled: August 19, 2013Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Damon B. Farmer, Aaron D. Franklin, Shu-Jen Han, George S. Tulevski
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Patent number: 8765548Abstract: Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.Type: GrantFiled: September 3, 2013Date of Patent: July 1, 2014Assignee: Infineon Technologies AGInventors: Martin Ostermayr, Richard Lindsay
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Patent number: 8765549Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.Type: GrantFiled: April 27, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hua Chang, Shin-Puu Jeng, Der-Chyang Yeh, Shang-Yun Hou, Wen-Chih Chiou
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Patent number: 8765550Abstract: In an embodiment of the invention, a method of fabricating a floating-gate NMOSFET (n-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves as the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.Type: GrantFiled: February 6, 2012Date of Patent: July 1, 2014Assignee: Texas Instruments IncorporatedInventors: Shanjen Pan, Alan T. Mitchell, Jack G. Qian
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Patent number: 8765551Abstract: According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.Type: GrantFiled: December 28, 2012Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-youl Yang, Dae-hong Eom, Byoung-moon Yoon, Kyung-hyun Kim, Se-ho Cha
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Patent number: 8765552Abstract: A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.Type: GrantFiled: April 12, 2013Date of Patent: July 1, 2014Assignee: SanDisk Technologies Inc.Inventor: Masaaki Higashitani
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Patent number: 8765553Abstract: Nonvolatile memory has a modified channel region interface, such as a raised source and drain or a recessed channel region.Type: GrantFiled: May 18, 2010Date of Patent: July 1, 2014Assignee: Macronix International Co., Ltd.Inventor: Yi Ying Liao
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Patent number: 8765554Abstract: A gate electrode is formed so as to embed an electrode material in a recess for an electrode, which has been formed in a structure of stacked compound semiconductors, through a gate insulation film, and also a field plate electrode that comes in Schottky contact with the structure of the stacked compound semiconductors is formed by embedding an electrode material in a recess for an electrode, which has been formed in the structure of the stacked compound semiconductors so that the field plate electrode directly comes in contact with the structure of the stacked compound semiconductors at least on the bottom face of the recess for the electrode.Type: GrantFiled: December 14, 2011Date of Patent: July 1, 2014Assignee: Fujitsu LimitedInventors: Tadahiro Imada, Toshihide Kikkawa
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Patent number: 8765555Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.Type: GrantFiled: April 30, 2012Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventor: Damon E. Van Gerpen
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Patent number: 8765556Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate.Type: GrantFiled: December 23, 2009Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Rung Hsu, Chen-Hua Yu, Chao-Cheng Chen, Ming-Huan Tsai, Hsien-Hsin Lin, Hsueh-Chang Sung
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Patent number: 8765557Abstract: A first layer constituting a first surface of a silicon carbide layer and of a first conductivity type is prepared. An internal trench is formed at a face opposite to the first surface of the first layer. Impurities are implanted such that the conductivity type of the first layer is inverted on the sidewall of the internal trench. By the implantation of impurities, there are formed from the first layer an implantation region located on the sidewall of the internal trench and of a second conductivity type, and a non-implantation region of the first conductivity type. A second layer of the first conductivity type is formed, filling the internal trench, and constituting the first region together with the non-implantation region.Type: GrantFiled: January 8, 2013Date of Patent: July 1, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideki Hayashi, Takeyoshi Masuda
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Patent number: 8765558Abstract: A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.Type: GrantFiled: March 22, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Haining S. Yang
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Patent number: 8765559Abstract: When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.Type: GrantFiled: January 25, 2012Date of Patent: July 1, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Stephan Kronholz, Gunda Beernink, Markus Lenski, Frank Seliger, Frank Richter
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Patent number: 8765560Abstract: A method of manufacturing a semiconductor device, the semiconductor device including a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.Type: GrantFiled: June 19, 2013Date of Patent: July 1, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Naoyoshi Tamura
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Patent number: 8765561Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.Type: GrantFiled: June 6, 2011Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8765562Abstract: A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate.Type: GrantFiled: September 13, 2012Date of Patent: July 1, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
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Patent number: 8765563Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.Type: GrantFiled: September 28, 2012Date of Patent: July 1, 2014Assignee: Intel CorporationInventors: Ravi Pillarisetty, Seung Hoon Sung, Niti Goel, Jack T. Kavalieros, Sansaptak Dasgupta, Van H. Le, Willy Rachmady, Marko Radosavljevic, Gilbert Dewey, Han Wui Then, Niloy Mukherjee, Matthew V. Metz, Robert S. Chau
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Patent number: 8765564Abstract: A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern.Type: GrantFiled: June 13, 2012Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Myung Jin Kang
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Patent number: 8765565Abstract: According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.Type: GrantFiled: July 9, 2013Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Aoyama, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
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Patent number: 8765566Abstract: A non-volatile memory device includes first wiring structures elongated in a first direction and separated by a first gap region in a second direction, the first gap region comprising first dielectric material formed in a first process, second wiring structures elongated in a second direction and separated by a second gap region in a first direction, the second gap region comprising second dielectric material formed in a second process, and a resistive switching devices comprising active conductive material, resistive switching material, and a junction material, wherein resistive switching devices are formed at intersections of the first wiring structures and the second wiring structures, wherein the junction material comprising p+ polysilicon material overlying the first wiring material, wherein some resistive switching devices are separated by the first gap region and some resistive switching devices separated by the second gap region.Type: GrantFiled: May 10, 2012Date of Patent: July 1, 2014Assignee: Crossbar, Inc.Inventor: Steven Patrick Maxwell
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Patent number: 8765567Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.Type: GrantFiled: October 24, 2013Date of Patent: July 1, 2014Assignee: Intermolecular, Inc.Inventors: Sandra G Malhotra, Sean Barstow, Tony P. Chiang, Pragati Kumar, Prashant B Phatak, Sunil Shanker, Wen Wu
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Patent number: 8765568Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.Type: GrantFiled: October 8, 2013Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Joseph M. Lukaitis, Deborah M. Massey, Timothy D. Sullivan, Ping-Chuan Wang, Kimball M. Watson
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Patent number: 8765569Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.Type: GrantFiled: June 14, 2011Date of Patent: July 1, 2014Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Hanhong Chen, Wim Deweerd, Hiroyuki Ode
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Patent number: 8765570Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (<2 nm) or highly doped so that it remains amorphous after subsequent anneal treatments. A second dielectric material is formed above the first dielectric material. The second dielectric material is sufficiently thick (>3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.Type: GrantFiled: June 12, 2012Date of Patent: July 1, 2014Assignee: Intermolecular, Inc.Inventors: Sandra Malhotra, Wim Deweerd, Hiroyuki Ode
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Patent number: 8765571Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing a semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.Type: GrantFiled: March 21, 2012Date of Patent: July 1, 2014Assignee: SoitecInventors: Oleg Kononchuk, Frederic Allibert