Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.

Abstract: According to the embodiment, a storage device includes row lines arranged parallel to one another, column lines arranged parallel to one another to intersect with the row lines, and a memory cell disposed at each of intersections of the row lines and the column lines and including a resistance-change element and a diode connected in series to the resistance-change element. The diode includes a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type. An impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region.

Abstract: According to one embodiment, a memory cell includes a resistance change layer, an upper electrode layer, a lower electrode layer, a diode layer, a first oxide film, and a second oxide film. The upper electrode layer is arranged above the resistance change layer. The lower electrode layer is arranged below the resistance change layer. The diode layer is arranged above the upper electrode layer or below the lower electrode layer. The first oxide film exists on a side wall of at least one electrode layer of the upper electrode layer or the lower electrode layer. The second oxide film exists on a side wall of the diode layer. The film thickness of the first oxide film is thicker than a film thickness of the second oxide film.

Abstract: A vertically oriented memory element having a narrower area near its center away from its ends is formed. Current density and heating are higher away from the ends of the memory element, thus increasing its lifetime.

Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. The device further includes at least one of dopant initiators or dopants localized at an interface between i) the first electrode and the active region, or ii) the second electrode and the active region, or iii) the active region and each of the first and second electrodes.

Abstract: An electronic device includes a first electrode, a second electrode, and a solid electrolyte made of an ion-conducting material, the first and second electrodes being configured to form a metal dendrite. The device further includes a third electrode, an interface layer contacting the third electrode and a third surface of the electrolyte, the interface layer being an ionic insulator and an electronic insulator. The third electrode and the dendrite are arranged such that the device has two resistive states.

Abstract: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.

Abstract: On example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and a device layer. The device layer comprises a first dielectric material, between the first and second conductive electrodes, that includes an effective device layer, a first barrier layer near a first interface between the first conductive electrode and the device layer, and a second barrier layer near a second interface between the second conductive electrode and the device layer. A second example of the present invention is an integrated circuit that incorporates nanoscale electronic devices of the first example.

Abstract: According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.

Abstract: A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.

Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.

Abstract: A homo-material heterophased quantum well includes a first structural layer, a second structural layer and a third structural layer. The second structural layer is sandwiched between the first and third structural layers. The first structural layer, second structural layer and third structural layer are formed by growing atoms of a single material in a single growth direction. The energy gap of the second structural layer is smaller than that of the first and third structural layers.

Abstract: The present invention relates to light-emitting devices and in particular organic light-emitting devices (OLEDs). In particular, the invention relates to emitter materials in which charged metal complexes are bonded to a polymer by electrostatic interactions.

Abstract: The present invention relates to buffer bilayers, and their use in electronic devices. The bilayer has a first layer including at least one electrically conductive polymer doped with at least one highly-fluorinated acid polymer. The second layer is a reacted layer from a metal which can be one or more transition metals, Group 13 metals, Group 14 metals, or lanthanide metals.

Abstract: A permeation barrier film structure for organic electronic devices includes one or more bilayers having a hybrid permeation barrier composition. Each of the one or more bilayers includes a first region having a first composition corresponding to a first CF4—O2 Plasma Reactive Ion Etch Rate and a second region having a second composition corresponding to a second CF4—O2 Plasma Reactive Ion Etch Rate, wherein the second Etch Rate is greater than the first Etch Rate by a factor greater than 1.2 and the hybrid permeation barrier film is a homogeneous mixture of a polymeric material and a non-polymeric material, wherein the mixture is created from a single precursor material.

Abstract: The present invention relates to an organic light-emitting device capable of suppressing deterioration of organic EL elements at the corners of an emission region. The organic light-emitting device includes a planarization film which planarizes thin film transistors arranged in an emission region where pixels are arranged, an element separation film which defines the pixels formed on the planarization film, a charge transport layer formed on the planarization film in each pixel. The charge transport layer contains any one of alkali metals and alkaline-earth metals and extends to outside of the emission region so as to cover the side surface of a peripheral portion of the planarization film, which is disposed in a peripheral region, the planarization film being formed in the emission region.

Abstract: This invention relates to dibenzothiopyran compounds. This invention also relates to layers and devices including at least one of these compounds.

Abstract: A compound represented by the following formula (I), provided that the compound in which all of R1 to R14 are hydrogen atoms is excluded.

Abstract: Pixel control structure for use in a backplane for an electronic display, including a transistor that has a gate, a source, a drain, and an organic semiconductor element. The pixel control structure is formed by a first patterned conductive layer portion, a second patterned conductive layer portion, a dielectric layer portion, and an organic patterned semiconductive layer portion. The dielectric layer portion comprises an overlap region defined by overlap of the second conductive layer portion over the first conductive layer portion. The overlap region defines an overlap boundary, defined by an edge portion of the first patterned conductive layer portion and an edge portion of the second patterned conductive layer portion. The patterned semiconductive layer portion extends over the overlap region and away from the overlap region so as to extend from both first and second edge portions.

Abstract: A transparent electrode is provided for an organic light emitting diode (OLED) device. The electrode may be made according to a method including: sputter-depositing a first layer of or including indium tin oxide (ITO) on a substrate; sputter-depositing a thin second metallic or substantially metallic layer on the glass substrate over the first layer to form an electrode structure, and heat treating the electrode structure at temperature(s) of at least about 400 degrees C. in order to thermally activate at least the first layer of or including ITO. The electrode structure may then be provided in an OLED device on the light-emitting side of the organic light emitting semiconductor layer.

Abstract: An electronic or electro-optic device has a first electrode, a second electrode spaced apart from the first electrode, and a dielectric layer disposed between the first and second electrodes. The dielectric layer has electrically insulating planar layers with intercalated ions therebetween such that the electrically insulating planar layers provide a barrier to impede movement of the intercalated ions to the first and second electrodes under an applied voltage while permitting a polarization of the dielectric layer while in operation.

Abstract: An organic light emitting device includes a substrate divided into and defined by first to third pixels, a first electrode disposed on the substrate and a second electrode facing the first electrode, a first light emitting layer and a second light emitting layer disposed in the first pixel and in the second pixel, respectively, between the first electrode and the second electrode, a first triplet exciton confinement layer, a third light emitting layer and a second triplet exciton confinement layer disposed over the first to third pixels in this order, on the first light emitting layer and the second light emitting layer, and a first common layer disposed between the first light emitting layer and the second light emitting layer, and the first electrode, and a second common layer disposed between the second triplet exciton confinement layer and the second electrode.

Abstract: Provided are a nitrogen-containing aromatic heterocyclic compound useful as an organic semiconductor material and an organic electronic device using this compound. The nitrogen-containing aromatic heterocyclic compound has a fused indole skeleton represented by the following formula (1), the organic semiconductor material contains the compound, and the organic electronic device uses the organic semiconductor material. In general formula (1), X is N-A?, O, S, or Se; A is an alkyl group, a cycloalkyl group, an alkenyl group, an alkynyl group, an aromatic hydrocarbon group, or an aromatic heterocyclic group exclusive of a fused heterocycle consisting of 4 rings or more; and R is a hydrogen atom, an alkyl group, a cycloalkyl group, an alkenyl group, an alkynyl group, an aromatic hydrocarbon group, or an aromatic heterocyclic group exclusive of a fused heterocycle consisting of 4 rings or more.

Abstract: Provided are a novel nitrogen-containing aromatic heterocyclic compound and an organic electronic device using the compound. This nitrogen-containing aromatic compound is represented by the general formula (1). Further, the present invention relates to organic electronic devices such as a light-emitting device, a thin-film transistor, and a photovoltaic device each using the nitrogen-containing aromatic compound. (L represents an m+n-valent aromatic hydrocarbon group or aromatic heterocyclic group, or a group arising from a triarylamine or a diaryl sulfone; X represents N-A, O, S, or Se; A represents an alkyl group or the like; R represent hydrogen, an alkyl group, an aromatic group, or the like; and m+n is an integer of 2 to 4.

Abstract: A thin film transistor including an oxide semiconductor with favorable electrical characteristics is provided. The thin film transistor includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and on the gate insulating film, a metal oxide film provided on the oxide semiconductor film, and a metal film provided on the metal oxide film. The oxide semiconductor film is in contact with the metal oxide film, and includes a region whose concentration of metal is higher than that of any other region in the oxide semiconductor film (a high metal concentration region). In the high metal concentration region, the metal contained in the oxide semiconductor film may be present as a crystal grain or a microcrystal.

Abstract: The invention relates to a printable precursor comprising an organometallic aluminum, gallium, neodymium, ruthenium, magnesium, hafnium, zirconium, indium and/or tin complex or a mixture thereof which contains at least one ligand from the class of the oximates, for electronic components, and to a preparation process. The invention furthermore relates to corresponding printed electronic components, preferably field-effect transistors.

Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

Abstract: To provide a semiconductor device including a transistor formed using a highly reliable oxide semiconductor. To provide a semiconductor device which can be manufactured with high productivity and high yield by reducing the number of photolithography steps. The semiconductor device includes a first wiring, a second wiring, and a third wiring whose potential is lower than those of the first wiring and the second wiring between the first wiring and the second wiring.

Abstract: A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased.

Abstract: The present disclosure relates to a device and method for fabricating a semiconductor memory device arrangement comprising a butted a contact arrangement configured to couple two transistors, wherein an active area of a first transistor is coupled to an active gate of a second transistor. The active gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active area of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.

Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Abstract: The present disclosure relates to secure devices having a physical unclonable function and methods of manufacturing such secure devices. One device includes at least one graphene layer representing a physical unclonable function and a measurement circuit for measuring at least one property of the at least one graphene layer. Another device includes at least a first graphene layer and a second graphene layer representing a physical unclonable function, where one of the graphene layers has been subjected to a variability enhancement such that a measurable property is different for each of the layers. A method includes providing a substrate for a secure device and providing at least one graphene layer on the substrate, the at least one graphene layer representing a physical unclonable function. The providing of the at least one graphene layer includes applying at least one variability enhancement to the at least one graphene layer.

Abstract: A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer.

Abstract: A substrate; a gate electrode formed above the substrate; a gate insulating film formed above the gate electrode; a crystalline silicon semiconductor layer formed above the gate insulating film; an amorphous silicon semiconductor layer formed above the crystalline silicon semiconductor layer; an organic protective film made of an organic material and formed above the amorphous silicon semiconductor layer; and a source electrode and a drain electrode formed above the amorphous silicon semiconductor layer interposing the organic protective film are included, and a charge density of the negative carriers in the amorphous silicon semiconductor layer is at least 3×1011 cm?2.

Abstract: An organic light-emitting display device preventing edge defects between a pixel define layer and a pixel electrode, and a method of manufacturing the same. The organic light-emitting display device, comprises: a substrate; a pixel electrode disposed on the substrate and comprising a first patterned unit and a second patterned unit which are electrically disconnected; a pixel define unit disposed on the substrate and exposing the pixel electrode; an intermediate layer disposed on the pixel electrode and emitting light; and a counter electrode disposed on the intermediate layer and the pixel define layer.

Abstract: In an IPS type liquid crystal display device having a reduced number of layers and formed through a reduced number of photolithography steps, an off current of a TFT is prevented from increasing due to photocurrent. A drain line, a TFT drain electrode, and a source electrode each have a multilayer structure including metal and a semiconductor layer. The drain line and the semiconductor layer formed thereunder are separated from the drain electrode and the semiconductor layer formed thereunder with the drain line and the drain electrode connected by a blocking conductive film formed of ITO of which the pixel electrode is also formed. Photocurrent generated by backlight is blocked by the blocking conductive film without flowing into the TFT. Therefore, the number of photomasks required in the production process can be decreased without an increase of causing the off current of the TFT.

Abstract: An embodiment of the disclosed technology provides a thin film transistor device comprising a source electrode, a drain electrode, a gate electrode, an active layer corresponding to the gate electrode, and a gate insulation layer formed between the gate electrode and the active layer; a concave region corresponding to the gate electrode is provided in the gate insulation layer.

Abstract: An OLED device includes: a TFT including an active layer, gate, source and drain electrodes, a first insulating layer between the active layer and the gate electrode, and a second insulating layer between the source and drain electrodes, a pixel electrode on the first and second insulating layers, connected to one of the source and drain electrodes, a capacitor including a first electrode on the same layer as the active layer, a second electrode on the same layer as the gate electrode, and a third electrode formed of the same material as the pixel electrode, a third insulating layer between the second insulating layer and the pixel electrode and between the second and third electrodes, a fourth insulating layer covering the source, drain and third electrodes, exposing a portion of the pixel electrode, an organic light-emitting layer on the pixel electrode, and a counter electrode on the organic light-emitting layer.

Abstract: A semiconductor substrate includes: a thin-film transistor including an organic semiconductor layer; and a light absorption-transmission layer provided in a pathway that leads external light to the organic semiconductor layer. The light absorption-transmission layer absorbs light of a wavelength range that includes at least a part of a light absorption wavelength range of the organic semiconductor layer, and allows light of a remaining wavelength range to pass therethrough.

Abstract: A pixel structure including a semiconductor layer having at least one source region and at least one drain region; a first insulating layer covering the semiconductor layer; a first conductive layer on the first insulating layer and including at least one gate; a second insulating layer covering the first conductive layer; a second conductive layer on the second insulating layer and including at least one source electrode, at least one drain electrode and at least one bottom electrode, the source region, the source electrode, the drain region, the drain electrode and the gate forming at least one thin film transistor; a third insulating layer covering the second conductive layer; a third conductive layer on the third insulating layer and including at least one top electrode, the top electrode and the bottom electrode forming at least one capacitor; and a pixel electrode electrically connected to the thin film transistor.

Abstract: A thin film transistor (TFT) array panel includes: first and second pixel electrodes neighboring each other; a data line extending between the first and the second pixel electrodes; first and second gate lines extending perpendicularly to the data line; a first TFT including a first gate electrode connected to the first gate line, a first source electrode connected to the data line, and a first drain electrode facing the first source electrode and connected to the first pixel electrode; and a second TFT including a second gate electrode connected to the second gate line, a second source electrode connected to the data line, and a second drain electrode facing the second source electrode and connected to the second pixel electrode. The first source electrode has the same relative position with respect to the first drain electrode as the second source electrode with respect to the second drain electrode.

Abstract: It is an object to provide a flexible light-emitting device with high reliability in a simple way. Further, it is an object to provide an electronic device or a lighting device each mounted with the light-emitting device. A light-emitting device with high reliability can be obtained with the use of a light-emitting device having the following structure: an element portion including a light-emitting element is interposed between a substrate having flexibility and a light-transmitting property with respect to visible light and a metal substrate; and insulating layers provided over and under the element portion are in contact with each other in the outer periphery of the element portion to seal the element portion. Further, by mounting an electronic device or a lighting device with a light-emitting device having such a structure, an electronic device or a lighting device with high reliability can be obtained.

Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.

Abstract: A flexible display apparatus is disclosed. The flexible display apparatus includes: a substrate on which a display unit for displaying an image, a non-display area formed outside the display unit, and at least one pad for inputting an electrical signal to the display unit are located; and a circuit board including circuit terminals to be electrically connected to the at least one pad. A stiffener including a plurality of reinforcement lines that are patterned to reduce or prevent thermal deformation of the substrate is formed on the substrate.

Abstract: “An imaging device formed as an active pixel array combining a CMOS fabrication process and a nanowire fabrication process. The pixels in the array may include a single or multiple photogates surrounding the nanowire. The photogates control the potential profile in the nanowire, allowing accumulation of photo-generated charges in the nanowire and transfer of the charges for signal readout. Each pixel may include a readout circuit which may include a reset transistor, charge transfer switch transistor, source follower amplifier, and pixel select transistor. A nanowire is generally structured as a vertical rod on the bulk semiconductor substrate to receive light energy impinging onto the tip of the nanowire. The nanowire may be configured to function as either a photodetector or a waveguide configured to guild the light to the substrate. Light of different wavelengths can be detected using the imaging device.

Abstract: It is possible to manufacture a large-size, high-accuracy organic EL display using a plastic substrate and an organic EL display using a roll-shaped long plastic substrate. The organic EL display includes an organic EL device A having at least a lower electrode 300, an organic layer including at least a light emitting layer, and an upper electrode 305 and a thin film transistor B on a transparent plastic substrate 100, a source electrode or drain electrode of the thin film transistor B is connected to the lower electrode 300, the plastic substrate 100 has a gas barrier layer 101a, the thin film transistor B is formed on the gas barrier layer 101a, the thin film transistor B includes an active layer 203 containing a non-metallic element which a mixture of oxygen (O) and nitrogen (N) and has a ratio of N to O (N number density/O number density) from 0 to 2, and the organic EL device A is formed at least on the gas barrier layer 101a or one the thin film transistor B.

Abstract: Disclosed are methods and materials useful in the preparation of semiconductor devices. In particular embodiments, disclosed are methods for engineering polycrystalline aluminum nitride substrates that are thermally matched to further materials that can be combined therewith. For example, the polycrystalline aluminum nitride substrates can be engineered to have a coefficient of thermal expansion (CTE) that is closely matched to the CTE of a semiconductor material and/or to a material that can be used as a growth substrate for a semiconductor material. The invention also encompasses devices incorporating such thermally engineered substrates and semiconductor materials grown using such thermally engineered substrates. The thermally engineered substrates are advantageous for overcoming problems caused by damage arising from CTE mismatch between component layers in semiconductor preparation methods and materials.

Abstract: This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.