Abstract: A control device for controlling an oxygen concentration sensor includes: a voltage sweeping unit for applying a voltage to the sensor for a time interval during an impedance detection process; a pre-sweeping voltage memory for storing a terminal voltage of the sensor as an initial terminal voltage just before applying the voltage; an impedance detection unit for detecting an element impedance; a voltage returning unit for returning the terminal voltage to the initial terminal voltage after a predetermined time interval has elapsed; a monitoring unit for monitoring the terminal voltage after the voltage returning unit starts returning the terminal voltage; a determination unit for determining whether a monitored terminal voltage of the sensor reaches a stored terminal voltage in the memory; and a stop unit for stopping a returning operation of the voltage returning unit when the monitored terminal voltage reaches the stored terminal voltage.

Abstract: The present invention relates to an apparatus for measuring winding resistances of windings in a delta-connected transformer, comprising at least a first and a second DC current source (S1, S2) connected each between the phase ends of a first (A) and a second leg (C; B) respectively of the primary side (P) of the transformer and at least a third DC current source (S3) connected between two nodes (a, b) of the secondary side (S) of the transformer.

Abstract: The present invention is directed to structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads and the apparatus for use thereof and to methods of fabrication thereof. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.

Abstract: Embodiments of methods and systems for identifying or determining spatially resolved properties in indirect bandgap semiconductor devices such as solar cells are described. In one embodiment, spatially resolved properties of an indirect bandgap semiconductor device are determined by externally exciting the indirect bandgap semiconductor device to cause the indirect bandgap semiconductor device to emit luminescence (110), capturing images of luminescence emitted from the indirect bandgap semiconductor device in response to the external excitation (120), and determining spatially resolved properties of the indirect bandgap semiconductor device based on a comparison of relative intensities of regions in one or more of the luminescence images (130).

Abstract: A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit.

Abstract: An approach for monitoring electrostatic discharge (ESD) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an ESD pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure. The approach further includes circuit source and logic gates of the canary device, connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure. The approach further includes a logic gate of the ESD transistor, connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure. In addition, the enable signal is also connected to the input terminal through a resistor of the circuit structure.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: A load device for applying an active load to a power source such as a wind turbine is characterized by an inductance and a resistive element both connected in parallel with the source. A relay is connected in series with the inductance and the resistive element and a controller is connected with the relays to selectively connect the inductance or resistive element with the source. By connecting a selected load with the power source, the source can be tested to evaluate that it is operating and performing properly.

Abstract: Introduced is an active shield method providing security to a security critical integrated circuit against some physical attacks like probing, manipulation and modification, while providing the ability to detect any physical modification made on the active shield itself. Electrically controllable switching circuits are used to construct the upper layer conductive bit lines with electrically selectable different interconnection configurations. These bit lines arranged in a shielding pattern are used to carry a test data between a transmitter circuitry and a number of receiver circuitries which verify the integrity of the shielding lines to provide the security for the integrated circuit. By changing the selected interconnection configuration of the bit lines with a select signal produced by the transmitter, the self detection ability of the proposed active shield is provided as a countermeasure against the vulnerability to physical modification made on the active shield itself.

Abstract: A technique for calibration of on-chip resistance (R) and capacitance (C) values using an on-board bypass capacitor may include configuring an on-chip switch to selectively couple an on-chip calibration circuit to an on-chip port. The on-chip calibration circuit may include an RC oscillator having an RC time constant (RCTC). The on-board bypass capacitor may be coupled to the on-chip calibration circuit, by using the on-chip port. The on-chip R and C values may be calibrated using the on-chip calibration circuit and the on-board bypass capacitor.

Abstract: A circuit may include a controller, at least one bridge circuit, and a plurality of switches. The plurality of switches may be connected parallel to each other, each may have a switch output connected to the bridge circuit. The bridge circuit, upon receiving a current from the plurality of switches, may generate an output based on a reference voltage. The controller may generate a plurality of control signals, based on a voltage transition range, to selectively turn on the plurality of the switches in more than one combination, to supply a current to the output.

Abstract: The dead time is secured stably in a semiconductor drive circuit for switching devices using a wide band gap semiconductor. The drain terminal of the switching device of an upper arm is connected to the positive terminal of a first power supply, the source terminal of the switching device of a lower arm is connected to the negative terminal of the first power supply, and the source terminal of the switching device of the upper arm is connected with the drain terminal of the switching device of the lower arm. A gate drive circuit provided for each switching device includes an FET circuit and a parallel circuit made of a parallel connection of a first resistor and a first capacitor and having a first terminal connected to the gate terminal of the switching device.

Abstract: A frequency compensation apparatus includes a first counter setting a reference period using a main clock, a second counter sensing a change in the frequency of a sub clock using the reference period, and a frequency compensator providing a compensated frequency using information on the changed frequency of the sub clock. Related methods are also described.

Abstract: A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.

Abstract: A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.

Abstract: Provided is a semiconductor device for compensating for an internal skew without training with an external device. The semiconductor device includes a signal generating unit configured to generate and output a reference signal, a first receiving unit configured to receive the reference signal and output a first output signal, a second receiving unit configured to receive the reference signal and output a second output signal, a delay unit configured to delay the first output signal by a certain time and output a delayed signal, a sampling unit configured to sample the second output signal based on the delayed signal and output sampling data, and a skew controlling unit configured to control the delaying unit based on the sampling data.

Abstract: In various embodiments, an active vector generator may comprise a vector component switch and a first amplitude adjustment component in parallel with a second amplitude adjustment component. The first and second amplitude adjustment components may operate with different ranges of amplitude. For example, the first amplitude adjustment component may have a full range of amplitude and the second amplitude adjustment component may have a partial range of amplitude. The vector component switch may operate to receive two signals and route the signals to the various amplitude adjustment components based on the relative magnitudes of the two signals. A benefit of having two amplitude adjustment components with selectable signal pathways is that the all the phase states may be obtained but using less robust and expensive amplitude adjustment components.

Abstract: When a voltage is applied from outside such that a current flowing in a Hall element is switched, each of a plurality of capacitors is charged with an output voltage of the Hall element in each state. A dummy switching element is connected to a switching element which connects the plurality of capacitors in parallel to each other, the dummy switching element and the switching element being controlled to be switched ON and OFF exclusively with respect to each other.

Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.

Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high threshold voltage channel region is formed in the first well and extending down from the surface of the substrate.

Abstract: It is presented a power supply for providing power to control a power switch for a high voltage application. The power supply comprises: a high voltage divider arranged to be connected to a first current terminal of the power switch; a step down DC/DC converter connected to an output of the high voltage divider, wherein the step down DC/DC converter is arrange to provide an output voltage for control of the at least one power switch to an output of the power supply; and a bypass control unit arranged to control the high voltage divider to short circuit an main input and a main output of the high voltage divider when the voltage across the power switch is lower than a threshold voltage.

Abstract: An integrated circuit (IC) includes an adaptive voltage scaling (AVS) controller configured to control a voltage supplied to a portion of the IC and at least one sensor configured to sense at least one state of the IC and to provide an output signal indicative of the at least one sensed state to the AVS controller, the IC having a first setting and a second setting, the AVS controller being configured to use the output signal to control the voltage in the first setting and the AVS controller being configured to control the voltage independently of the output signal in the second setting. Also a method of performing AVS is provided.

Abstract: A method for controlling an input device is provided. The input device has a resistor matrix having M first traces, N second traces and M×N resistors. Each second trace is coupled to a reference resistor and M?1 variable resistors. M and N are integers greater than 1. A first voltage level of each second trace is measured when a first voltage is applied to a first end of the reference resistor and a second voltage is applied to first ends of the M?1 variable resistors via the M first traces. Variations of the first voltage level of each second trace are measured, such that it could be determined whether any touch point of the input device exists according to the variations of the first voltage level of each second trace.

Abstract: According to an aspect of the present invention, in a semiconductor device, a plurality of commands for specifying a circuit configuration of an analog front-end unit are transmitted from a processing unit to the analog front-end unit, an analysis is performed on the plurality of commands received by the analog front-end unit, and when a circuit configuration of the analog front-end unit which is to be updated and is determined according to the plurality of commands includes a forbidden condition that has been previously set, updating processing of the circuit configuration according to the plurality of commands is stopped.

Abstract: The present invention relates to a system for boosting the power supply of an RF power amplifier in high peak to average power ratio applications, wherein said power amplifier is coupled to receive and amplify a digital data stream of a baseband signal, (e.g., which after modulation with a carrier wave are supplied as the RF input signal to said power amplifier to generate an RF output signal).

Abstract: A transmission signal power control apparatus includes a power amplifier model unit which generates a learning digital signal by multiplying part of a predistortion signal by model coefficients which tentatively represent the input-output characteristics of a power amplifier, and an adaptive low-pass filter which generates a pseudo feedback signal by attenuating the high frequency components of the learning digital signal by multiplying the learning digital signal by weighting coefficients. Then, the power amplifier model unit updates the model coefficients such that the error between the feedback signal whose the high frequency components are attenuated by the low-pass filter and which is digitized, and the pseudo feedback signal is minimized, and the adaptive low-pass filter updates the weighting coefficients such that the error is minimized.

Abstract: In a predistorter that can compensate an intermodulation distortion component generated in a power amplifier even when employing carrier aggregation, a linear transmission path delays and transmits an input signal. Signal generation units generate individual carrier distortion signals for respective carriers included in an input signal to output an individual carrier distortion compensation signal. A sub-signal generation unit generates a carrier inter-modulation distortion signal from the input signal and the individual carrier distortion signal and outputs a carrier inter-modulation distortion compensation signal. A signal divider divides the input signal among the linear transmission path, the signal generation units, and the sub-signal generation unit. A signal combiner combines the individual carrier distortion compensation signal and the carrier inter-modulation distortion compensation signal to generate an output signal to an amplifier.

Abstract: An integrated circuit includes a radio frequency (RF) amplifier having a trifilar transformer coupled to a gain device in two negative feedback paths. The trifilar transformer includes a first winding, a second winding and a third winding, a first dielectric core is disposed between the first winding and the second winding, and a second dielectric core is disposed between the second winding and the third winding. A first winding ratio between the first winding and the second winding combined with a second winding ratio between the second winding and the third winding affects a total gain of the RF amplifier. In a specific embodiment, the gain device is a transistor, the first winding is coupled to a base of the transistor, the second winding is coupled to a collector of the transistor, and the third winding is coupled to an emitter of the transistor.

Abstract: The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the Class-S RF-PA. The drive circuit provides a high slew-rate, large-swing, quasi-digital gate drive circuit to drive the significant gate capacitance of the RF-PA with sufficient rise times. A combination of bipolar transistor current switches and cascoded CMOS devices is employed to attain requisite performance. For example, the driving circuit is well suited for use with Class-S RF-PAs used in wireless communication systems.

Abstract: An amplifier system may include a power stage having inputs for three different supply voltages and an output for coupling to a load, a controller to generate control signals to the power stage that cause the power stage to vary an output voltage applied to the load among more than three distinct voltage levels, a monitor to provide a first control signal to the controller based on an input voltage signal, and a feedback system to provide a second control signal to the controller based on comparison of the output voltage and the input signal.

Abstract: A continuous variable gain amplifier includes an attenuator network, a boost network, a first amplifying network, and a second amplifying network, where the attenuator network generates first differential output signals according to an input signal and sends the first differential output signals to the first amplifying network and the second amplifying network; the first amplifying network and the second amplifying network receive one output of the first differential output signals each, and generate a first final output signal and a second final output signal respectively according to an externally input control voltage; and the boost network receives the first final output signal and the second final output signal, generates second differential output signals, and sends a first output and a second output of the second differential output signals to the first amplifying network and the second amplifying network, respectively

Abstract: A variable gain amplifier (100) includes a transistor (110), an FB impedance section (120), a source impedance section (130), a drain impedance section (140), a gain controller (150), and a frequency characteristic controller (160). The gain controller (150) varies impedance of one of the FB impedance section (140), the source impedance section (130), and the drain impedance section (140), and outputs a gain control signal. The frequency characteristic controller (160) varies the impedance of different impedance section, based on the gain control signal.

Abstract: A power amplifier using N-way Doherty structure with adaptive bias supply power tracking for extending the efficiency region over the high peak-to-average power:ratio of the multiplexing modulated signals such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. In an embodiment, present invention uses a dual-feed distributed structure to an N-way Doherty amplifier to improve the isolation between at least one main amplifier and at least one peaking amplifier and, and also to improve both gain and efficiency performance at high output back-off power. Hybrid couplers can be used at either or both of the input and output. In at least some implementations, circuit space is also conserved due to the integration of amplification, power splitting and combining.

Abstract: A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a bias circuit, an output stage circuit and dynamic bias controlling circuit. The bias circuit receives a first system voltage and provides a working voltage accordingly. The output stage circuit receives the working voltage so as to work at an operation bias point. The dynamic bias controlling circuit detects a RF input signal and outputs a compensation voltage to the bias circuit according to variation of the RF input signal, wherein the dynamic bias controlling circuit is an open loop configuration. When an input power of the RF input signal increases and makes the working voltage decreases so as to shift the operation bias point, the bias circuit adjusts the working voltage upward so as to recover or enhance the operation bias point according to the compensation voltage received.

Abstract: Various embodiments described herein provide systems and methods for improved performance for power amplifiers, particularly GaN power amplifiers. According to some embodiments, a power amplifier (e.g., GaN power amplifier) utilizes an adaptive closed loop control of the drain current of the power amplifier to achieve improved performance for the power amplifier.

Abstract: Various embodiments described herein provide systems and methods for improved performance for power amplifiers, particularly GaN power amplifiers. According to some embodiments, a power amplifier (e.g., GaN power amplifier) utilizes an adaptive closed-loop control of the drain current of the power amplifier to achieve improved performance for the power amplifier. Additionally, for some embodiments, use of the adaptive closed-loop control of the drain current of the power amplifier depends on the power region in which the power amplifier is operating (e.g., depends on the radio frequency power region).

Abstract: A radio frequency amplifier circuit includes a transistor and an output-side matching circuit. The output-side matching circuit includes a first distributed constant line to which a radio frequency signal from the transistor is transmitted, a flat plate lead terminal transmitting the radio frequency signal from the first distributed constant line to an outside of the package, and a capacitive element having one electrode that is connected to the lead terminal and the other electrode that is grounded. A back surface of the lead terminal is joined to a resin substrate, and the capacitive element and the first distributed constant line are disposed adjacent to each other, with an alignment direction of the capacitive element and the first distributed constant line intersecting an alignment direction of the first distributed constant line and the lead terminal.

Abstract: This disclosure includes systems and methods for frequency synthesis using a voltage-controlled oscillator (VCO) with a programmable array of capacitors. A suitable setting for the capacitor array may be derived through a non-successive iterative numerical technique. In one aspect, the iterative numerical technique may apply Newton's method to an equation relating frequency generated by the VCO and the capacitor setting of the first programmable array of capacitors. In another aspect, a secant method may be applied to determine a capacitor array setting based on previously and currently applied capacitor settings and the corresponding measured frequencies.

Abstract: A calibration circuit includes a combinational gate configured to receive a voltage-controlled oscillator (VCO) output signal and a selected reference signal to detect a phase difference between the VCO output signal and the selected reference signal and generate an output binary signal, in which the VCO output signal has one or more unwanted frequency components. The calibration circuit also includes a loop filter configured to filter the output binary signal and generate a filtered calibration signal. The calibration circuit also includes an analog-to-digital converter configured to convert the filtered calibration signal from the analog domain to the digital domain and generate a converted calibration signal. The calibration circuit also includes a processor configured to compute the converted calibration signal and determine components of a baseband signal that cancels the one or more unwanted frequency components of the VCO output signal.

Abstract: A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a current source applied to the output detection signal to form a correction voltage that is a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal.

Abstract: A random number generator and method for testing the same are described. In one embodiment, the random number generator comprises one or more ring oscillator structures, each of the one or more ring oscillator structures having a ring oscillator for use in generating random numbers and having a test structure to reconfigure the ring oscillator into a testable structure.

Abstract: An oscillation control circuit for a ring oscillator includes a bandgap reference circuit and an oscillation frequency control circuit. The bandgap reference circuit is arranged for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature current. The oscillation frequency control circuit is coupled to the bandgap reference circuit, and is arranged for biasing the ring oscillator according to the bandgap reference signal. When the ring oscillator has a plurality of stages, the oscillation frequency control circuit includes one current source and a plurality of current mirrors for biasing the plurality of stages of the ring oscillator, respectively.

Abstract: A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a frequency divider that is configured to apply a correction voltage to a feedback of the output frequency signal, the correction voltage being a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal.

Abstract: Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second node; inductor; first capacitive network (FCN) that allows the design structure to obtain a target FOO; compensating capacitive (CCN) network that compensates for a change in the design structure's FOO; second capacitive network (SCN) that allows the design structure to obtain a desired FOO; a filter that supplies a voltage to the SCN and is coupled to the SCN; a transconductor that compensates for a change in the design structure's FOO; and a sub-circuit coupled to the SCN that generates and supplies voltage to the CCN sufficient to allow the CCN to compensate for a reduction in the design structure's FOO. The first and second nodes are coupled to the inductor, FCN, CCN, SCN, and sub-circuit.

Abstract: A PWM signal generating circuit, printer, and PWM signal generating method are described. The PWM signal generating circuit includes: a single counter configured to count values expressed in N bits; and at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated, and an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data. A signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.

Abstract: A resonant matching circuit (310) for matching a resonant frequency of a wireless power transfer system to a frequency of a power signal comprises a switch (311) connected in parallel with a resonant element (302) of the wireless power transfer N system; and a controller (312) connected to the switch (311) and configured to detect a zero-voltage level crossing of a signal flowing through the resonant element (302) and to close the switch (311) for a predefined amount of time upon detection of the zero-voltage level crossing, wherein closing the switch (311) for the predefined amount of time adds any one of an inductive value and a capacitive value to the resonant frequency of a wireless power transfer system.

Abstract: In an impedance matching device, a storage unit stores a control value representing a load value and a value equivalent to input impedance in advance. The control value identifies inductance and capacitance values matching a predetermined impedance value by use of either a first or second matching circuit. An impedance estimation unit estimates input impedance of the power transmission antenna. The load value estimation unit estimates load value of a circuit connected to a power reception antenna and consuming transmitted electric power. A circuit selection unit electrically connects the first matching circuit, the second matching circuit, or a through circuit per the load value and the input impedance equivalent value. A control value output unit reads out the control value stored in the storage unit based on the load value and the input impedance equivalent value, and outputs the control value to the circuit selected by the circuit selection unit.

Abstract: The invention relates to a coaxial-impedance synthesizer, comprising: a longitudinal central (0x) conductor (1); an outer conductive tube (2) arranged coaxially to the conductor (1); and at least one probe (4) mounted so as to longitudinally translate around the conductor (1), the coaxial-impedance synthesizer being characterized in that the outer tube (2) includes two separable half-tubes, such that the probe (4) is permitted to move longitudinally, relative to the central conductor (1), to a desired position when the two half-tubes are spaced apart from each other, and when the two half-tubes are near each other, the outer periphery of the probe (4) and the inner wall of the outer tube are in contact with each other.

Abstract: An improved nondirectional radiofrequency power divider is characterized by the following features:—having an outer conductor (1) and/or outer conductor housing (1?), with a first inner conductor (11), wherein the first inner conductor (11) runs in the outer conductor (1) or in the outer conductor housing (1?),—with a second inner conductor (13), wherein the second inner conductor (13) runs in the space (15) which is formed between the first inner conductor (11) and the outer conductor (1) or the outer conductor housing (1?),—the second inner conductor (13) is electrically connected to a branch line running away therefrom or is provided therewith, the second inner conductor (13) is relatively adjustable and/or positionable in terms of the distance of said second inner conductor from the first inner conductor (11) and/or in terms of the distance of said inner conductor from the outer conductor (1) or from the outer conductor housing (1?) so as to effect a variable power distribution.

Abstract: Embodiments disclosed include transmission line phase shifters and methods for fabricating transmission line phase shifters that switch signal and ground conductors to reverse electromagnetic fields in a transmission line structure.