Patents Issued in July 29, 2014
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Patent number: 8792247Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.Type: GrantFiled: August 17, 2012Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventor: Timothy M. Hollis
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Patent number: 8792248Abstract: The present invention provides a method for embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blind vias are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. With this methodology a resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.Type: GrantFiled: June 22, 2012Date of Patent: July 29, 2014Assignee: R & D Circuits, Inc.Inventor: James V Russell
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Patent number: 8792249Abstract: A waterproofing structure for a mobile terminal, includes an annular groove that surrounds an outer edge of a predetermined waterproof area of a mobile terminal. A waterproof lid covers an entire surface of the waterproof area, and includes an annular protrusion that fits into the annular groove in the waterproof area, and an elastic resin portion that covers the annular protrusion. The elastic resin portion press-contacts and adheres to only one of two side wall surfaces of the annular groove when the annular protrusion is fitted into the annular groove.Type: GrantFiled: November 19, 2010Date of Patent: July 29, 2014Assignees: Sony Corporation, Sony Mobile Communications Inc.Inventors: Keiichi Sasamori, Mizuho Ikeda, Hiroshi Yamamoto, Katsumi Saito
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Patent number: 8792250Abstract: A connector for connecting surface mount devices, such as light emitting diodes (LEDs), to printed circuit boards (PCBs). The connector may be prepackage with an LED assembly or on a PCB to which the LED assembly will be mounted. Connection complexity can be moved from the PCB to the connector, and LED assemblies may be customized differently for different customers. One to many and many to one connections are readily supported with variations on the connector.Type: GrantFiled: December 18, 2012Date of Patent: July 29, 2014Assignee: Cree, Inc.Inventor: Gregory S. Bibee
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Patent number: 8792251Abstract: An electronic device includes an enclosure and a locking assembly. The locking assembly includes a fixing sleeve including a fixing end hermetically fixed to the enclosure, and an opening end away from the enclosure, and a locking bracket. The locking bracket is attached to the fixing sleeve and defines a through hole defining a passing portion and at least one locking portion communicating with each other. The electronic device is position to a fastener by the fastener passing through the passing portion and being positioned in the locking portion of the through hole.Type: GrantFiled: August 31, 2011Date of Patent: July 29, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Cheng-Feng Shih
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Patent number: 8792252Abstract: A display apparatus includes a display panel including lower and upper substrates confronting each other, and a film member combined with the upper substrate; and a panel support member to support the display panel to expose the front and lateral sides of the display panel to the outside.Type: GrantFiled: November 14, 2011Date of Patent: July 29, 2014Assignee: LG Display Co., Ltd.Inventors: Hak Mo Hwang, In Jue Kim, Yong Joong Yoon, Sung Hwan Yoon, In-Han Ga
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Patent number: 8792253Abstract: A voltage conversion system and methods are disclosed. Phase-shift modulation signals are generated and interleaved to provide interleaved phase-shift modulation signals. A plurality of voltage converters are controlled using the interleaved phase-shift modulation signals to convert an input electrical current at an input voltage to an output electrical current at an output voltage.Type: GrantFiled: October 3, 2011Date of Patent: July 29, 2014Assignee: The Boeing CompanyInventors: Duanyang Wang, Dariusz Czarkowski, Francisco de Leon, Kamiar J. Karimi, Lijun Gao, Shengyi Liu
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Patent number: 8792254Abstract: A power converter includes an input stage connected to receive a three phase AC input voltage and to provide multiple DC voltage levels. The power converter also includes an output stage of a plurality of interleaved LLC converters having series-connected inputs coupled to the multiple DC voltage levels and parallel-connected outputs to provide a DC output voltage. Additionally, the power converter includes a balancing circuit interconnected to the input and output stages to provide substantially balanced output currents from the plurality of interleaved LLC converters for the DC output voltage. Methods of manufacturing and operating a power converter are also provided.Type: GrantFiled: June 28, 2011Date of Patent: July 29, 2014Assignee: General Electric CompanyInventor: Raghothama Reddy
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Patent number: 8792255Abstract: A converter supplies output power according to a first output current and a second output current generated according to each switching operation of a first switch and a second switch. A duty adjuster circuit generates an adjuster current to compensate the difference between the peak of the first output current and the peak of the second output current to adjust duty of the first and second switches.Type: GrantFiled: August 22, 2011Date of Patent: July 29, 2014Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Jin-Tae Kim, Kwang-Il Lee
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Patent number: 8792256Abstract: A controller for a switch and a method of operating the same. In one embodiment, the controller is configured to measure a voltage of a control terminal of the switch and select a first mode of operation if the voltage of the control terminal is greater than a threshold voltage, and a second mode of operation if the voltage of the control terminal is less than the threshold voltage.Type: GrantFiled: January 27, 2012Date of Patent: July 29, 2014Assignee: Power Systems Technologies Ltd.Inventors: Ralf Schroeder genannt Berghegger, Michael Frey
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Patent number: 8792257Abstract: A power converter with reduced power dissipation at light loads and method of operating the same. In one embodiment, the power converter includes an opto-isolator circuit configured to produce an output signal dependent on an output characteristic of the power converter. The power converter also includes a controller configured to control the output characteristic to a first regulated value when the output signal is greater than or equal to a threshold level, and control the output characteristic to a second regulated value less than the first regulated value when the output signal is less than the threshold level.Type: GrantFiled: March 25, 2011Date of Patent: July 29, 2014Assignee: Power Systems Technologies, Ltd.Inventor: Ralf Schröder genannt Berghegger
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Patent number: 8792258Abstract: An apparatus for coupling a switching mode power supply (SMPS) controller to a rectified line voltage. The apparatus includes a high-voltage startup transistor configured to provide a charging current during a startup phase of the SMPS controller and to provide substantially no current during a normal operation phase of the SMPS controller. A switch coupled to the high-voltage startup transistor. The switch receives a control signal from the SMPS controller, for turning off the switch during the startup phase and turning on the switch during the normal operation phase. A biasing device is connected in series with the switch and maintains the startup transistor in an off state when the SMPS controller is in the normal operation phase. A standby current in the apparatus is substantially lower when the SMPS controller is in the normal operation phase than the charging current in the apparatus when the SMPS is in the startup phase.Type: GrantFiled: October 9, 2008Date of Patent: July 29, 2014Assignee: BCD Semiconductor Manufacturing LimitedInventors: Yajiang Zhu, Ruixia Fei, Wenhui Dong, Shaohua Fang
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Patent number: 8792259Abstract: Software embodied in a machine-readable storage medium and useful for controlling alternating-current (AC) output of a power converter connected to an AC power network. The software is designed and configured to estimate the phase of the voltage on the AC power network that will be on the network when the network recovers from a fault. Such software allows a power-network-connected power source to ride-through a fault event and continue supplying power thereto at the designed phase and frequency. In one embodiment, the software provides this estimate by tracking the phase with a response time changed in inverse proportion to the voltage on the power network.Type: GrantFiled: May 29, 2013Date of Patent: July 29, 2014Assignee: Northern Power Systems, Inc.Inventor: Jeffrey K. Petter
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Patent number: 8792260Abstract: An object is to provide a rectifier circuit of which the drop in the output voltage by the threshold voltage of a transistor used as a rectifier element is suppressed. Another object is to provide a rectifier circuit whose variations in the output voltage are suppressed even in the case where the amplitude of input AC voltage varies greatly. A transistor may be used as a rectifier element in such a way that a gate electrode of the transistor is connected to a second electrode of the transistor through a capacitor, and the potential of the gate electrode is held to be higher than the potential of the second electrode by a difference greater than or equal to the threshold voltage.Type: GrantFiled: September 15, 2011Date of Patent: July 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Masashi Fujita
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Patent number: 8792261Abstract: A power conversion device connected with a three-phase power system through a transformer, including unit converters cascade-connected so that reactors are unnecessary, and volume and weight are reduced. The secondary winding of the transformer is an open winding having six terminals. A first converter group, includes a circuit which has three converter arms, which are star-connected, connected to three of the terminals of the secondary winding. A second converter group, having three different converter arms which are star-connected, is connected to three other terminals of the secondary winding. A neutral point (the point where the star connection is made) of the first converter group, and a neutral point of the second converter group are made to be the output terminals of the power conversion device.Type: GrantFiled: February 24, 2010Date of Patent: July 29, 2014Assignee: Hitachi, Ltd.Inventors: Shigenori Inoue, Shuji Katoh, Jun Narushima, Tetsuya Kato
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Patent number: 8792262Abstract: A method of programming memory cells in a nonvolatile memory, includes applying a programming voltage to a first bitline and setting a second bitline in a floating state. The method further includes applying a compensation voltage to a shield conductive line coupled to the bitline set in the floating state, and setting in the floating state a shield conductive line coupled to the bitline receiving the programming voltage. The method is applicable to the reduction of the parasitic programming phenomena of memory cells by capacitive coupling between bitlines.Type: GrantFiled: May 29, 2012Date of Patent: July 29, 2014Assignee: STMicroelectronics (Rousset) SASInventor: Francois Tailliet
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Patent number: 8792263Abstract: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.Type: GrantFiled: December 22, 2011Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventor: Toru Tanzawa
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Patent number: 8792264Abstract: A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.Type: GrantFiled: August 12, 2013Date of Patent: July 29, 2014Assignee: Seagate Technology LLCInventors: Insik Jin, Xiaobin Wang, Yong Lu, Haiwen Xi
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Patent number: 8792265Abstract: A phase change material for use in a phase change memory device comprises germanium-antimony-tellurium-indium, wherein the phase change material comprises in total more than 30 at % antimony, preferably 5-16 at % germanium, 30-60 at % antimony, 25-51 at % tellurium, and 2-33% at % indium.Type: GrantFiled: April 29, 2010Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Michael Antoine Armand In 'T Zandt, Robertus Andrianus Maria Wolters, Hendrikus Jan Wondergem
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Patent number: 8792266Abstract: A memory cell is formed with a resistance variable element, which is interposed between first and second electrodes and can store resistance changes representing 2 or more different values, and first and second cell transistors having source terminals thereof connected to the first electrode, and gates thereof to a word line. A drain of the first cell transistor is connected to a bit line, and a drain of the second cell transistor is connected to a data line. The second electrode is connected to a source line. During a read operation, the first and second cell transistors are kept in an ON state, and a current is supplied from the bit line to the source line through the memory cell. Data is read according to the electrical potential difference between the data line and the source line.Type: GrantFiled: September 6, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Daisaburo Takashima
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Patent number: 8792267Abstract: In described embodiments, a memory circuit includes a static random access memory (SRAM) including N banks of memory cells, rows of M sense amplifiers, a controlled feedback latch storing a previous state of input data in a read cycle, a pull down select block coupled to the controlled feedback latch and the dummy sense amplifier, a dummy output latch coupled to the pull-down select block to store the read data, and a SRAM reset generation circuit coupled to the sense amplifier control circuits and the controlled feedback latch. The dummy output latch is a latch that is the same as a sense amplifier latch used in the local input/output circuit, thereby, no margin is involved between a reset of the sense amplifiers and the read data latched at the dummy output latch in the read cycle.Type: GrantFiled: January 23, 2013Date of Patent: July 29, 2014Assignee: LSI CorporationInventors: Kamal Chandwani, Rahul Sahu, Vikash
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Patent number: 8792268Abstract: A nonvolatile latch circuit according to the present invention includes: a latch operating unit in which outputs of cross-coupled connected inverter circuit and inverter circuit are connected via a series circuit which includes a transistor, a variable resistance element, and a transistor in this order, and store and restore in a latch state are controlled by control terminals of the transistors; and a comparator circuit which compares a signal obtained by amplifying the value of the sum of potentials at both ends of the variable resistance element with the logic state of the latch operating unit, wherein writing to and reading from the variable resistance element are repeated until an output of the comparator circuit indicates that normal write operation has been performed.Type: GrantFiled: November 8, 2012Date of Patent: July 29, 2014Assignee: Panasonic CorporationInventor: Yoshikazu Katoh
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Patent number: 8792269Abstract: A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.Type: GrantFiled: March 15, 2013Date of Patent: July 29, 2014Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Patent number: 8792270Abstract: A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a separate integrated circuit to provide access signals, including read and write signals suitable for binary or multi-level accesses.Type: GrantFiled: May 10, 2011Date of Patent: July 29, 2014Assignee: Ovonyx, Inc.Inventor: Ward Parkinson
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Patent number: 8792271Abstract: A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body.Type: GrantFiled: October 27, 2011Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hirofumi Morise, Hideaki Fukuzawa, Akira Kikitsu, Yoshiaki Fukuzumi
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Patent number: 8792272Abstract: A method and apparatus are provided for implementing enhanced data partial erase for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, and a data re-write after the partial erase to the MLC memory is performed using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase cycle includes a duration and voltage level based upon a degradation of the MLC memory cells.Type: GrantFiled: January 30, 2012Date of Patent: July 29, 2014Assignee: HGST Netherlands B.V.Inventors: Zvonimir Z. Bandic, Luiz M. Franca-Neto, Cyril Guyot, Robert Eugeniu Mateescu
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Patent number: 8792273Abstract: A method of operation of a data storage system includes: providing a power monitor module for detecting a loss of host power; interrupting a unit controller by the power monitor module; configuring a memory controller by the unit controller; and writing a non-volatile memory array for storing in-flight data and contents of a system control random access memory in a multi-level cell NAND flash device in response to detecting the loss of the host power.Type: GrantFiled: June 11, 2012Date of Patent: July 29, 2014Assignee: Smart Storage Systems, Inc.Inventors: Robert W. Ellis, Scott Creasman
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Patent number: 8792274Abstract: A system is provided and includes an array of cells, a first module, and a third module. The first module reads a state of a cell in the array to detect first bits stored in the cell. The third module, subsequent to the first module reading the state, performs a first operation on a first bit of the first bits and performs the first operation on a first of multiple signal inputs. The signal inputs indicate second bits of data to be stored in the cell. The third module performs a second operation on a second bit of the first bits and performs the second operation on a second one of the signal inputs. The first module, based on results of the first and second operations, performs a first erase operation or a first program operation on the cell to match the state of the cell to the second bits.Type: GrantFiled: August 21, 2012Date of Patent: July 29, 2014Assignee: Marvell International Ltd.Inventors: Qiang Tang, Bo Wang, Chih-Hsin Wang
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Patent number: 8792275Abstract: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.Type: GrantFiled: July 4, 2011Date of Patent: July 29, 2014Assignee: United Microelectronics Corp.Inventors: Ping-Chia Shih, Chung-Chin Shih
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Patent number: 8792276Abstract: Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region.Type: GrantFiled: August 12, 2013Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventor: Serguei Okhonin
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Patent number: 8792277Abstract: Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.Type: GrantFiled: September 16, 2013Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady L. Keays
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Patent number: 8792278Abstract: A non-volatile semiconductor memory device includes: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of the first wiring provided at a first position and extends to the first wiring provided at a second position higher than the first position in a laminated direction; and a second contact plug that comes into contact with a side portion of the second wiring provided at a third position between the first position and the second position and extends to the second wiring provided at a fourth position higher than the second position in the laminated direction.Type: GrantFiled: December 17, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Nagashima
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Patent number: 8792279Abstract: A data analytic system allows for analytic operations be moved from a server on to a solid state drive (SSD) type analytic system, where a CAM NAND structure can be used in the analytic operations. The server can run a software using database language can issue command to the analytic system. On the data analytic system (that can interface with common, existing database language), the software commands are translated into firmware language and broken down into multiple small tasks. The small tasks are executed on the SSD flash controllers or on NAND flash according to the task specifications. The mid-product from the NAND flash or the SSD controllers can be merged within each SSD blade and also further merged on the top server level.Type: GrantFiled: March 14, 2013Date of Patent: July 29, 2014Assignee: SanDisk Technologies Inc.Inventors: Yan Li, John R. Busch, Steven T. Sprouse
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Patent number: 8792280Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.Type: GrantFiled: May 13, 2013Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventor: Zengtao Liu
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Patent number: 8792281Abstract: A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results. An optimal set of the read thresholds is estimated by processing the multiple readout results obtained from the respective subsets using the different sets of the read thresholds.Type: GrantFiled: August 21, 2012Date of Patent: July 29, 2014Assignee: Apple Inc.Inventors: Barak Baum, Eyal Gurgi
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Patent number: 8792282Abstract: A nonvolatile memory device configured to apply a wordline erase voltage to a plurality of wordlines connected to a plurality of memory cells, apply an erase voltage to a substrate where a memory cell string is formed while applying a specific voltage to at least one ground selection line connected to at least one ground selection transistor, and float the at least one ground selection line when a target voltage of the substrate reaches a target voltage.Type: GrantFiled: July 10, 2012Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Chul Lee, Doogon Kim, Jinman Han
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Patent number: 8792283Abstract: A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command.Type: GrantFiled: June 21, 2012Date of Patent: July 29, 2014Assignee: Intel CorporationInventors: Yogesh B. Wakchaure, Kiran Pangal, Xin Guo, Qingru Meng, Hanmant Belgal
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Patent number: 8792284Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.Type: GrantFiled: August 2, 2011Date of Patent: July 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 8792285Abstract: A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.Type: GrantFiled: December 2, 2011Date of Patent: July 29, 2014Assignee: Macronix International Co., Ltd.Inventor: Ji-Yu Hung
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Patent number: 8792286Abstract: A semiconductor memory device includes a page buffer configured to store data read from a memory cell, a counter circuit configured to count the number of first data or second data in the read data for every read operation while the read operations are repeated a set number of times, and a control logic configured to determine the number of read operations and determine the read data of the memory cell based on the counted number.Type: GrantFiled: December 20, 2011Date of Patent: July 29, 2014Assignee: SK Hynix Inc.Inventor: Seok Jin Joo
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Patent number: 8792287Abstract: A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part.Type: GrantFiled: March 6, 2012Date of Patent: July 29, 2014Assignee: Lapis Semiconductor Co., Ltd.Inventors: Katsuaki Matsui, Junya Ogawa
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Patent number: 8792288Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.Type: GrantFiled: January 30, 2013Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporationInventors: Steven Craig Bartling, Sudhanshu Khanna
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Patent number: 8792289Abstract: A method for rewriting a memory array with a number of memory elements includes performing a rewrite process to change the memory array from an initial state to a target state in a manner that avoids violating a set of weight constraints at any time during the rewrite process. A memory system includes a memory array and a memory controller configured to perform a rewrite process to change the memory array from an initial state to a target state in a manner that avoids violating a set of weight constraints at any time during the rewrite process.Type: GrantFiled: July 28, 2010Date of Patent: July 29, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Erik Ordentlich, Gadiel Seroussi, Pascal Olivier Vontobel
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Patent number: 8792290Abstract: A voltage generator includes a high voltage generator configured to include a plurality of pump circuits for generating various levels of a high voltage in response to clock signals, wherein the plurality of pump circuits are configured to receive enable signals corresponding to a level of voltage to be generated, where the enable signals are generated in response to internal operation signals. And a clock transfer circuit configured to generate a clock enable signal by comparing the high voltage and a reference voltage and to selectively provide the clock signals to each of the pump circuits in response to the clock enable signal and each of the enable signals.Type: GrantFiled: December 28, 2011Date of Patent: July 29, 2014Assignee: SK Hynix Inc.Inventor: Yu Jong Noh
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Patent number: 8792291Abstract: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.Type: GrantFiled: May 6, 2013Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventor: Chang-Ki Kwon
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Patent number: 8792292Abstract: A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.Type: GrantFiled: March 11, 2011Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Jung-Ping Yang, Chung-Ji Lu, Derek C. Tao, Cheng Hung Lee, Hung-Jen Liao
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Patent number: 8792293Abstract: Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.Type: GrantFiled: October 26, 2012Date of Patent: July 29, 2014Assignee: LSI CorporationInventors: Sahilpreet Singh, Disha Singh
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Patent number: 8792294Abstract: An access method for a DRAM is provided. A row address is partitioned into a first portion and a second portion. The first portion of the row address via an address bus and a first active command via a command bus are provided to the DRAM. The second portion of the row address via the address bus and a second active command via the command bus are provided to the DRAM after the first active command is provided. A column address via the address bus and an access command via the command bus are provided to the DRAM after the second active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address, and the access command is a read command or a write command.Type: GrantFiled: December 27, 2012Date of Patent: July 29, 2014Assignee: Mediatek Inc.Inventor: Der-Ping Liu
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Patent number: 8792295Abstract: Methods and systems for monitoring a transducer array in an ultrasound probe are provided. One method includes acquiring ultrasound data using an ultrasound probe during an imaging mode of operation, wherein the ultrasound data includes echo information. The method further includes comparing the echo information from a plurality of transducer elements of a transducer array of the ultrasound probe during the imaging mode of operation, wherein the echo information is non-beamformed signal data. The method also includes determining non-uniformity information for the transducer array using the compared echo information during the imaging mode of operation.Type: GrantFiled: January 31, 2012Date of Patent: July 29, 2014Assignee: General Electric CompanyInventors: Kjell Kristoffersen, Geir Haugen, Morten Lennart Haugen, Anders R. Sornes
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Patent number: 8792296Abstract: Apparatus, computer instructions and method for deghosting seismic data related to a subsurface of a body of water. The method includes inputting data recorded by detectors that are towed by a vessel, the data being associated with waves travelling from the subsurface to the detectors; applying a migration procedure to the data to determine a first image of the subsurface; applying a mirror migration procedure to the data to determine a second image of the subsurface; joint deconvoluting the first image and the second image for deghosting a reflectivity of the subsurface; and generating a final image of the subsurface based on the deghosted reflectivity of the joint deconvoluting step.Type: GrantFiled: April 26, 2013Date of Patent: July 29, 2014Assignee: Cggveritas Services SAInventor: Robert Soubaras