Abstract: Embodiments of a bridge circuit and system are disclosed that may allow for converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The bridge circuit may be configured to receive transactions over the first bus and store parameters associated with the received transactions. The bridge circuit may be further configured to modify the received transaction, convert the modified transaction to the second communication protocol, and transmit the converted transaction over the second bus.

Abstract: Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed.

Abstract: A data storage system and method comprises a storage device located inside a cartridge housing and an adapter module removable from the storage device. A first interface directly connects the storage device to the adapter module through an opening in the cartridge housing and a second interface different than the first interface connects the adapter module to a host device.

Abstract: Provided are techniques for status information saving among multiple computers. In one embodiment, a selected computer is operated using a plurality of input/output devices over switched input/output signal paths passing through a KVM (keyboard video mouse) switch positioned between the selected computer and the plurality of input/output devices. Status data is carried over signal paths passing through the KVM switch wherein the status data represents status information for a plurality of computers connected to the KVM switch. The status data passing through the KVM switch is stored in a memory coupled to the KVM switch. Other embodiments are described and claimed. Other embodiments are contemplated, depending upon the particular application.

Abstract: There is provided a device control apparatus, a device control method and a program capable of easily initiating control of an operation of an external device through an application according to a status of the external device and a usage status of the application. An application for controlling an operation of an AV amplifier is acquired from an application server, a status of the AV amplifier and a usage status of the application are determined upon startup of the application, a screen according to the result of the determination is displayed in order to arrange an operation environment of the application and then a manipulation screen for controlling the operation of the AV amplifier through the application is displayed, and the operation of the AV amplifier is controlled according to a user manipulation performed through the manipulation screen.

Abstract: Various embodiments for transforming a logical data object for storage in a storage device operable with at least one storage protocol are provided. In one such embodiment, the logical data object into one or more segments are divided with each segment characterized by respective start and end offsets. One or more obtained variable size data chunks are processed corresponding to the logical data object to obtain processed data chunks, wherein at least one of the processed data chunks comprises transformed data resulting from the processing. Each of the variable size data chunks is associated with a respective segment of the logical data object. The processed data chunks are sequentially accommodated in accordance with an order of chunks received while keeping the association with the respective segments.

Abstract: Exemplary embodiments are directed to a system and method for integrating field devices in an automation system having a plurality of field devices connectable via at least one bus system. A respective field device is connected to the bus system of the automation system, and is automatically addressed by a superordinate controller using a predefined default address. The device addressed using the default address then registers in the system with its device address, and a fixed address which is provided from a multiplicity of unassigned addresses from an address memory is automatically allocated to the device registered in the system. An individually assigned identification (TAG) provided from the predetermined configuration of the automation system is allocated to the allocated fixed address, and, after the automatically allocated fixed address has been transmitted to the field device, the field device is changed to a suitable state for communication with the superordinate controller.

Abstract: A multi-drop serial bus to connect a master device to a plurality of slave devices on a data line includes a voltage divider network, comprising divider resistors in series on the data line between slave devices, and a voltage sensing device, connected to the data line, configured to detect a voltage order of signals from the slave devices, indicating a position of connection of each slave device.

Abstract: A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.

Abstract: A system-on-chip (SoC), an electronic system including the same, and a method of operating the same are provided. The method includes setting real-time information indicating whether a master block is a real-time block in a real-time information register of the master block. A weight is set in a weight register of the master block. Buffer information of the master block is checked. A quality-of-service (QoS) signal is generated using the buffer information and the weight. A priority of the master block to use the bus is determined based on the QoS signal.

Abstract: Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.

Abstract: Methods and apparatuses are provided for servicing an interrupt in a computer system. The method includes a device driver receiving an interrupt request. The device driver is responsive to the interrupt request to store interrupt data in a portion of the memory. The interrupt data includes identification of at least one processor of the plurality of processors capable of servicing the interrupt request; priority of the interrupt request; a thread context; and an address for instructions to service the interrupt request. The device driver then instructs the peripheral device to issue a memory write to the plurality of processors so that each may determine if it can use the thread context and the instructions to service the interrupt. A computer system is provided with the hardware needed to perform the method.

Abstract: A switch apparatus capable of being coupled to a computer and a plurality of devices, the switch apparatus includes: a first bridge coupled to the computer; a second-bridge group coupled to the devices; and a controller for controlling the connection relationship between the first bridge and the second-bridge group, wherein the controller assigns physical identifiers having different bus identifiers to the plurality of devices, assigns logical identifiers to the devices in accordance with an identifier assigned to the first bridge in response to an instruction for reading connection states of the devices received from the computer when the computer is coupled to the first bridge, and converts a physical identifier and a logical identifier of a packet transmitted between the first bridge and the second-bridge group in accordance with the correspondence relationships between the physical identifiers and the logical identifiers.

Abstract: A USB device and a detection method therefor. It can be detected whether the USB device is a master device or a slave device without the use of an ID pin, thereby saving the pin resources of the USB device.

Abstract: A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.

Abstract: Remote memory can be used for a number idle pages located on a virtual machine. A number of idle pages can be sent to the remote memory according to a placement policy, where the placement policy can include a number of weighting factors. A hypervisor on a computing device can record a local size and a remote page fault frequency of the number of virtual machines. The hypervisor can scan local memory to determine the number of idle pages and a number of idle virtual machines. The number of idle pages, including a page map and a remote address destination for each idle page, can be sent to the remote memory by the hypervisor. The number of virtual machines can be analyzed to determine a per-virtual machine local memory allocation.

Abstract: A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.

Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.

Abstract: In an embodiment, only one sector of a plurality of sectors in a physical block of a plurality of physical blocks has a sector status location configured to store information that indicates a move status of an other sector of the plurality sectors of the physical block of the plurality of physical blocks, where the only one sector of the plurality of sectors in the physical block of the plurality of physical blocks is configured to store a sector of data in addition to the information that indicates the move status.

Abstract: A shingled magnetic recording hard disk drive that uses writeable cache tracks in the inter-band gaps between the annular data bands minimizes the effect of far track erasure (FTE) in the boundary regions of annular data bands caused by writing to the cache tracks. Based on the relative FTE effect for all the tracks in a range of tracks of the cache track being written, a count increment (CI) table or a cumulative count increment (CCI) table is maintained. For every writing to a cache track, a count for each track in an adjacent boundary region, or a cumulative count for each adjacent boundary region, is increased. When the count value for a track, or the cumulative count for a boundary region, reaches a predetermined threshold the data is read from that band and rewritten to the same band.

Abstract: Consistent distributed storage communication protocol semantics, such as SCSI target semantics, in a SAN-attached clustered storage system are disclosed. The system includes a mechanism for presenting a single distributed logical unit, comprising one or more logical sub-units, as a single logical unit of storage to a host system by associating each of the logical sub-units that make up the single distributed logical unit with a single host visible identifier that corresponds to the single distributed logical unit. The system further includes a mechanism to maintain consistent context information for each of the logical sub-units such that the logical sub-units are not visible to a host system as separate entities from the single distributed logical unit.

Abstract: A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Selection logic enables selecting output of either register bank for input to processor execution logic. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

Abstract: A method includes updating a first tag access indicator of a storage structure. The tag access indicator indicates a number of accesses by a first thread executing on a processor to a memory resource for a portion of memory associated with a memory tag. The updating is in response to an access to the memory resource for a memory request associated with the first thread to the portion of memory associated with the memory tag. The method may include updating a first sum indicator of the storage structure indicating a sum of numbers of accesses to the memory resource being associated with a first access indicator of the storage structure for the first thread, the updating being in response to the access to the memory resource.

Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits, shared data lines and shared data selection circuits. The dependent data selection circuits are configured to select a subset of data from the memory system for storing in an associated dependent data line. Similarly, the shared data selection circuits are configured to select a subset of data from the memory system for storing in an associated shared data line.

Abstract: Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device.

Abstract: A cache memory system using temporal locality information and a data storage method are provided. The cache memory system including: a main cache which stores data accessed by a central processing unit; an extended cache which stores the data if the data is evicted from the main cache; and a separation cache which stores the data of the extended cache when the data of the extended cache is evicted from the extended cache and temporal locality information corresponding to the data of the extended cache satisfies a predetermined condition.

Abstract: A microcontroller system may include a microcontroller having a processor and a first memory, a memory bus and a second memory in communication with the microcontroller via the memory bus. The first memory may include instructions for accessing a first data set from a contiguous memory block in the second memory. The first data set may include a first word having a first value and a plurality of first other words. The first memory may include instructions for receiving a write instruction including a second data set to be written to the contiguous memory block. The first memory may include instructions for determining whether the first value equals the second value. If so, the first memory may include instructions for writing the second data set to the contiguous memory block and updating the first value.

Abstract: A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under the control of the hypervisor. Each domain is allocated memory resources that include accessible memory space that is exclusively accessible by that domain. Each domain is allocated one or more processor resources. The hypervisor identifies domain layout information that includes a boundary of accessible memory space of each domain. The hypervisor provides the domain layout information to each processor resource. Each processor resource is configured to implement, on a per domain basis, a restricted coherency protocol based on the domain layout information. The restricted coherency protocol bypasses, relative to the domain, downstream caches when a cache line falls within the accessible memory space of that domain.

Abstract: Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.

Abstract: A method for managing data, the method includes: providing a write-back cache unit coupled to at least one storage unit; receiving a request to write a new data version to a certain cache data allocation unit; determining, in response to a data storage policy, whether to overwrite a cached data version being cached in the certain cache data allocation unit or to perform a destage of the cached data version to a first storage unit before writing the new data version to the certain cache allocation unit; receiving a request to read a data version that corresponds to a certain point in time and scanning a first data structure representative of write operations and a second data structure representative of revert operations to determine a location of the requested data version.

Abstract: A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

Abstract: Methods and structure for improved buffer management in a storage controller. A plurality of processes in the controller each transmits buffer management requests to buffer management control logic. A plurality of reserved portions and a remaining non-reserved portion are defined in a shared pool memory managed by the buffer management control logic. Each reserved portion is defined as a corresponding minimum amount of memory of the shared pool. Each reserved portion is associated with a private pool identifier. Each allocation request from a client process supplies a private pool identifier for the associated buffer to be allocated. The buffer is allocated from the reserved portion if there sufficient available space in the reserved portion identified by the supplied private pool identifier. Otherwise, the buffer is allocated if sufficient memory is available in the non-reserved portion. Otherwise the request is queued for later re-processing.

Abstract: Large page memory pools are managed. Thresholds are used to determine if the number of pages in a large page memory pool is to be adjusted. If the number of pages is to be increased, a particular technique is provided for adding additional pages to the pool. Further, if there are too many pages in the pool, one or more pages may be removed.

Abstract: Embodiments of the present invention are directed to a method, computer-readable medium and system for deskewing data. More specifically, skewed data is accessed and written into a plurality of memories in an aligned manner. Each memory may be associated with a respective lane of a multiple lane distribution (MLD) system and may receive a respective initial portion of data associated with a frame. The memory or lane that is the last to receive an initial portion of data associated with the frame may be determined. The address at which the initial portion of data is written into the memory may be determined using a write pointer associated with the memory. At least one read pointer associated with the memories may be set to the address to allow the initial portions of data to be contemporaneously read from the memories.

Abstract: An information processing apparatus includes a calculator configured to perform a calculation, a plurality of system boards, each of the plurality of system boards including a first storage unit that stores a first program of a first type, the first program being to be used to operate the calculator, a preliminary board including a plurality of second storage units, at least one of the plurality of second storage units storing a second program of a second type, the second program corresponding to the first programs, and a controller configured to compare any one of the first types of the first programs with the second type of the second program and to write, when any one of the first types does not match the second type, the first program of the any one of the first types into the second storage unit.

Abstract: A method, apparatus and system of restoration of a parent LUN through modification of a read-write clone LUN as the parent LUN are disclosed. In one embodiment, the method includes transforming a snapshot of a parent LUN from a read-only state to a read-write clone LUN using a target module of a storage system. The method also includes changing a first data structure of a block transfer protocol to refer to the parent LUN as another clone LUN. Further, the method includes modifying a second data structure of the block transfer protocol to refer to the read-write clone LUN as the parent LUN. Then, the method includes restoring the parent LUN when the modification of the second data structure is completed.

Abstract: Described is a method and system for transparently migrating data between storage systems of a computing environment without disrupting realtime access to the stored data of the storage systems. Specifically, when adding a new storage system to the computing environment, realtime data write operations can be redirected to the new storage system instead of an existing storage system. During the redirection, the data stored on the existing storage system can be accessed for data operations. Concurrently, during the redirection, data stored on the existing storage system can be migrated to the new storage system. When the data migration completes and all the data, stored on the existing storage system prior to the redirection, resides on the new storage system, the new storage system can function as the primary storage system. Thus, storage capacity can increase or be replaced without disrupting data operations.

Abstract: A storage server receives a write request from a client system including new data and a location to store the new data. The storage server transmits a copy instruction to a storage subsystem to relocate old data at the location and transmits a write instruction to the storage subsystem to overwrite the old data with the new data. The storage subsystem includes fast stable storage in which the copy instruction and the write instruction are stored. After receiving each instruction, the storage subsystem sends an acknowledgement to the storage server. When both instructions have been acknowledged, the storage server sends an acknowledgement to the client system. The storage subsystem performs the instructions asynchronously from the client system's write request.

Abstract: A method and apparatus for of storing data comprising monitoring a plurality of storage units within a mass storage area and detecting when a storage unit within the mass storage area is overloaded. The method further comprising randomly distributing the data on the overloaded storage unit to the other storage units within the mass storage area.

Abstract: At least one of configuration information of a storage volume stored on a storage system and characteristics of a snapshot, including characteristics of one or more files stored in the snapshot, are identified. Snapshot content metadata, comprising the at least one of the identified characteristics and the configuration information, is created. The snapshot content metadata is associated with the snapshot.

Abstract: Replication requests are initiated in a virtual tape emulation system by storing a replication request in a persistent storage area that is shared between a virtual tape emulator and a control station. When the control station sees a pending replication request it initiates a request to a replication control to replicate the affected file or file system to a backup storage array. The control station deletes the replication request when the replication task completes. Deletion of the replication requests from the shared area is taken by the virtual tape task as a signal that replication has successfully completed, and can be reported to the mainframe.

Abstract: Provided are a method, system, and a computer program product handling a backup process. An instruction initiates a new backup from a source volume to a target volume using one of a plurality of backup processes. A cascade includes a cascade source volume and at least one cascade target volume, and a write to a storage location in one of the cascade volumes causes a copying of the storage location to be written in the cascade source volume to each of the cascade target volumes in the cascade according to a cascade order in which the at least one cascade target volume and the cascade source volume are linked in the cascade. The cascade is modified to include the target volume of the new backup in response to determining that there is an existing cascade, else a new cascade using the backup process of the new backup is created.

Abstract: An extended command is defined in compliance with the ATA standard. A selection number for selecting one of HDDs, one or more designated ATA commands, and an accessible time period including an available count are added to the extended command. As a result, designated normal ATA commands can access a certain one of the HDDs for a certain time period.

Abstract: A storage apparatus includes a memory that stores data groups, a rearranging unit that rearranges a transmission group order of the data groups based on each of storage positions in a storage device provided in a copy destination storage apparatus in which the each of data groups is to be stored, and a transmitting unit that transmits the data groups rearranged by the rearranging unit to the copy destination storage apparatus.

Abstract: Aspects of the present invention relate to data migration and/or disaster recovery. One embodiment enables merging of bitmaps to allow for automation of the process of switching to a different target volume on the same storage subsystem without major interruption of data recovery capability and limited interruption of host I/O to the source volumes during the migration. In one approach, the migration of data onto a new target volume within the same storage subsystem as the original target volume is automated, without requiring the user to manually create or remove any new copy relationships.

Abstract: An apparatus, system, and method are disclosed for policy-based secure destruction of data. The method for policy-based secure destruction of data is provided. In one embodiment, the method includes storing a data destruction policy, wherein the data destruction policy defines at least one predetermined data destruction parameter. The method may also include referencing the data destruction policy to obtain the data destruction parameters in response to a predetermined data operation. In a further embodiment, the method may include executing a data destruction process in accordance with the data destruction parameters.

Abstract: A transmission apparatus includes a memory and a circuit. The memory store control data included in a frame received from outside the apparatus and state information indicating a state of the control data in the transmission apparatus in association with each other. The circuit records the control data included in the frame to the memory. The circuit changes the state information to information indicating that the recording of the control data is completed. The circuit determines whether or not the control data stored in the memory is to be rewritten. The circuit rewrites the control data stored in the memory, upon determining that the control data is rewritten. The circuit changes the state information to information indicating that the rewriting of the control data is completed. The circuit reads the control data stored in the memory.

Abstract: A method, system and computer program product are provided for implementing feedback directed Non-Uniform Memory Access (NUMA) mitigation tuning in a computer system. During a page frame memory allocation for a process, predefined monitored performance metrics are compared with stored threshold values. Responsive to the compared values, selected use of local memory is dynamically modified during the page frame memory allocation.

Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

Abstract: A storage system comprises a storage medium including a plurality of physical storage areas. The storage system controls a host computer to recognize a logical volume having a plurality of virtual storage areas, reads the data from the physical storage area assigned to the virtual storage area of the logical volume, determines whether or not the read data includes only the specific pattern data, and cancels the assignment of the physical storage area to the virtual storage area if the read data includes only the specific pattern data.